Search results for "cycle-accurate"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
6	Nicolas Anciaux, Luc Bouganim, Philippe Pucheral, Patrick Valduriez	DiSC: Benchmarking Secure Chip DBMS.	IEEE Trans. Knowl. Data Eng.	2008	DBLP DOI BibTeX RDF
6	F. Ryan Johnson, JoAnn M. Paul	Interrupt modeling for efficient high-level scheduler design space exploration.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	scenario oriented design, MESH, Heterogeneous chip multiprocessors
6	Francesco Menichelli, Renato Menicocci, Mauro Olivieri, Alessandro Trifiletti	High-Level Side-Channel Attack Modeling and Simulation for Security-Critical Systems on Chips.	IEEE Trans. Dependable Secur. Comput.	2008	DBLP DOI BibTeX RDF
6	Rishad A. Shafik, Paul M. Rosinger, Bashir M. Al-Hashimi	MPEG-based Performance Comparison between Network-on-Chip and AMBA MPSoC.	DDECS	2008	DBLP DOI BibTeX RDF
6	Nupur Kothari, Kiran Nagaraja, Vijay Raghunathan, Florin Sultan, Srimat T. Chakradhar	HERMES: A Software Architecture for Visibility and Control in Wireless Sensor Network Deployments.	IPSN	2008	DBLP DOI BibTeX RDF	interposition, sensor networks, control, software reliability, visibility, SOS
6	Fabrizio Mulas, Michele Pittau, Marco Buttu, Salvatore Carta, Andrea Acquaviva, Luca Benini, David Atienza, Giovanni De Micheli	Thermal Balancing Policy for Streaming Computing on Multiprocessor Architectures.	DATE	2008	DBLP DOI BibTeX RDF
6	Sungchan Kim, Chanik Park, Soonhoi Ha	Architecture Exploration of NAND Flash-based Multimedia Card.	DATE	2008	DBLP DOI BibTeX RDF
6	Karin Avnit, Vijay D'Silva, Arcot Sowmya, S. Ramesh, Sri Parameswaran	A Formal Approach To The Protocol Converter Problem.	DATE	2008	DBLP DOI BibTeX RDF
6	Kim Grüttner, Frank Oppenheimer, Wolfgang Nebel, Fabien Colas-Bigey, Anne-Marie Fouilliart	SystemC-based Modelling, Seamless Refinement, and Synthesis of a JPEG 2000 Decoder.	DATE	2008	DBLP DOI BibTeX RDF
6	Abdellah-Medjadji Kouadri-Mostefaoui, Benaoumeur Senouci, Frédéric Pétrot	Large Scale On-Chip Networks : An Accurate Multi-FPGA Emulation Platform.	DSD	2008	DBLP DOI BibTeX RDF
6	Yanqin Yang, Zili Shao, Linfeng Pan, Minyi Guo	ISOS: Space Overlapping Based on Iteration Access Patterns for Dynamic Scratch-pad Memory Management in Embedded Systems.	ICYCS	2008	DBLP DOI BibTeX RDF
6	Jun Ho Bahn, Jungsook Yang, Nader Bagherzadeh	Parallel FFT Algorithms on Network-on-Chips.	ITNG	2008	DBLP DOI BibTeX RDF	Embedded DSP system, Parallel Programming, FFT, Network-on-Chip (NoC)
6	Ying Yu, Raymond R. Hoare, Alex K. Jones	A CAM-based intrusion detection system for single-packet attack detection.	IPDPS	2008	DBLP DOI BibTeX RDF
6	Young-Hwan Park, Sudeep Pasricha, Fadi J. Kurdahi, Nikil D. Dutt	Methodology for multi-granularity embedded processor power model generation for an ESL design flow.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	system-on-chip, embedded processor, power modeling, esl
6	Theo Kluter, Philip Brisk, Paolo Ienne, Edoardo Charbon	Speculative DMA for architecturally visible storage in instruction set extensions.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	architecturally visible storage, speculative direct memory access, instruction set extensions, application-specific processors
6	Daniel D. Gajski, Samar Abdi, Ines Viskic	Model Based Synthesis of Embedded Software.	SEUS	2008	DBLP DOI BibTeX RDF
6	Zhong-Yi Jin, Rajesh Gupta 0001	Improved Distributed Simulation of Sensor Networks Based on Sensor Node Sleep Time.	DCOSS	2008	DBLP DOI BibTeX RDF
6	Anders Sejer Tranberg-Hansen, Jan Madsen, Bjørn Sand Jensen	A service based estimation method for MPSoC performance modelling.	SIES	2008	DBLP DOI BibTeX RDF
6	John D. Davis, Zhangxi Tan, Fang Yu 0002, Lintao Zhang	Designing an Efficient Hardware Implication Accelerator for SAT Solving.	SAT	2008	DBLP DOI BibTeX RDF
6	Brian Keng, Hratch Mangassarian, Andreas G. Veneris	A succinct memory model for automated design debugging.	ICCAD	2008	DBLP DOI BibTeX RDF
6	Oreste Villa, Gianluca Palermo, Cristina Silvano	Efficiency and scalability of barrier synchronization on NoC based many-core architectures.	CASES	2008	DBLP DOI BibTeX RDF	scalability, synchronization, efficiency, Multicore, NoC, barrier, Manycore
6	Major Bhadauria, Sally A. McKee	Optimizing thread throughput for multithreaded workloads on memory constrained CMPs.	Conf. Computing Frontiers	2008	DBLP DOI BibTeX RDF	performance, efficiency, power, memory bandwidth
6	Xingzhi Wen, Uzi Vishkin	Fpga-based prototype of a pram-on-chip processor.	Conf. Computing Frontiers	2008	DBLP DOI BibTeX RDF	ease-of-programming, explicit multi-threading, on-chip parallel processor, pram, parallel algorithms, xmt
6	Wei Han 0001, Ying Yi, Mark Muir, Ioannis Nousias, Tughrul Arslan, Ahmet Teyfik Erdogan	MRPSIM: A TLM based simulation tool for MPSOCS targeting dynamically reconfigurable processors.	SoCC	2008	DBLP DOI BibTeX RDF
6	Enkhbold Ochirsuren, Heiko Hinkelmann, Leandro Soares Indrusiak, Manfred Glesner	TinyOS Extensions for a Wireless Sensor Network Node Based on a Dynamically Reconfigurable Processor.	DIPES	2008	DBLP DOI BibTeX RDF
6	Christophe Clavier, Benedikt Gierlichs, Ingrid Verbauwhede	Fault Analysis Study of IDEA.	CT-RSA	2008	DBLP DOI BibTeX RDF	Collision Fault Analysis, Ineffective Fault Analysis, Random Fault Model, IDEA, Differential Fault Analysis
6	Berkin Özisikyilmaz, Gokhan Memik, Alok N. Choudhary	Machine Learning Models to Predict Performance of Computer System Design Alternatives.	ICPP	2008	DBLP DOI BibTeX RDF
6	Thomas M. DuBois, Bryant C. Lee, Yi Wang, Marc Olano, Uzi Vishkin	XMT-GPU: A PRAM Architecture for Graphics Computation.	ICPP	2008	DBLP DOI BibTeX RDF
6	Liqun Cheng, John B. Carter	Extending CC-NUMA systems to support write update optimizations.	SC	2008	DBLP DOI BibTeX RDF
6	Hao Shen, Frédéric Pétrot	MPSoC Communication Architecture Exploration Using an Abstraction Refinement Method.	VLSI Design	2008	DBLP DOI BibTeX RDF
6	Aydin O. Balkan, Gang Qu 0001, Uzi Vishkin	An area-efficient high-throughput hybrid interconnection network for single-chip parallel processing.	DAC	2008	DBLP DOI BibTeX RDF	hybrid networks, on-chip networks, mesh-of-trees
6	John D. Davis, Zhangxi Tan, Fang Yu 0002, Lintao Zhang	A practical reconfigurable hardware accelerator for Boolean satisfiability solvers.	DAC	2008	DBLP DOI BibTeX RDF	BCP, FPGA, reconfigurable, SAT solver, co-processor
6	Ke Ning, David R. Kaeli	Power Aware External Bus Arbitration for System-on-a-Chip Embedded Systems.	Trans. High Perform. Embed. Archit. Compil.	2007	DBLP DOI BibTeX RDF	embedded systems, power-aware, external memory, media processor, bus arbitration
6	N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk	Run-Time Integration of Reconfigurable Video Processing Systems.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
6	Nevine AbouGhazaleh, Bruce R. Childers, Daniel Mossé, Rami G. Melhem	Near-Memory Caching for Improved Energy Consumption.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	Memory power management, Cached DRAM, Power Management, Energy-aware systems, Memory design
6	Partha Biswas, Nikil D. Dutt, Laura Pozzi, Paolo Ienne	Introduction of Architecturally Visible Storage in Instruction Set Extensions.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
6	Youngjin Cho, Naehyuck Chang	Energy-Aware Clock-Frequency Assignment in Microprocessors and Memory Devices for Dynamic Voltage Scaling.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
6	Salvatore Carta, Andrea Alimonda, Alessandro Pisano, Andrea Acquaviva, Luca Benini	A control theoretic approach to energy-efficient pipelined computation in MPSoCs.	ACM Trans. Embed. Comput. Syst.	2007	DBLP DOI BibTeX RDF	feedback-control techniques, parallel systems, MPSoC, DVFS
6	David Atienza, Pablo García Del Valle, Giacomo Paci, Francesco Poletti, Luca Benini, Giovanni De Micheli, Jose Manuel Mendias, Román Hermida	HW-SW emulation framework for temperature-aware design in MPSoCs.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	Thermal-aware design, FPGA, emulation, MPSoC, temperature
6	Antoine Fraboulet, Guillaume Chelius, Eric Fleury	Worldsens: development and prototyping tools for application specific wireless sensors networks.	IPSN	2007	DBLP DOI BibTeX RDF	simulation, sensor networks, performance, development
6	Mark H. Nodine	Automatic Testbench Generation for Rearchitected Designs.	MTV	2007	DBLP DOI BibTeX RDF
6	Nicolas Fournel, Antoine Fraboulet, Paul Feautrier	Fast and Accurate Embedded Systems Energy Characterization Using Non-intrusive Measurements.	PATMOS	2007	DBLP DOI BibTeX RDF
6	Arno Moonen, Marco Bekooij, René van den Berg, Jef L. van Meerbergen	Practical and Accurate Throughput Analysis with the Cyclo Static Dataflow Model.	MASCOTS	2007	DBLP DOI BibTeX RDF
6	Naser Sedaghati-Mokhtari, Mahdi Nazm Bojnordi, Sied Mehdi Fakhraie	MDST: Multiprocessor DSP Simulation Toolkit for Voice Processing Applications.	MASCOTS	2007	DBLP DOI BibTeX RDF	MDST, Multiprocessor DSP Simulation toolkit, Voice processing applications
6	Liqun Cheng, John B. Carter, Donglai Dai	An Adaptive Cache Coherence Protocol Optimized for Producer-Consumer Sharing.	HPCA	2007	DBLP DOI BibTeX RDF
6	Chung-Fu Kao, Chi-Hung Lin, Ing-Jer Huang	Configurable AMBA On-Chip Real-Time Signal Tracer.	ASP-DAC	2007	DBLP DOI BibTeX RDF
6	Alexey Kupriyanov, Dmitrij Kissler, Frank Hannig, Jürgen Teich	Efficient event-driven simulation of parallel processor architectures.	SCOPES	2007	DBLP DOI BibTeX RDF	embedded tools, simulation, modeling, processor arrays
6	Jiang Lin, Hongzhong Zheng, Zhichun Zhu, Zhao Zhang 0010, Howard David	DRAM-Level Prefetching for Fully-Buffered DIMM: Design, Performance and Power Saving.	ISPASS	2007	DBLP DOI BibTeX RDF	channel bandwidth utilization, DRAM-level prefetching, dynamic random access memory, fully-buffered DIMM, dual in-line memory module, redundant bandwidth, memory block, L2 cache block, DRAM power consumption, SPEC2000 program, software cache prefetching, idle memory latency, power saving, multicore processor, memory controller, interconnect structure, DRAM chip
6	Ying Chen, Simon Y. Chen	Cost-Driven Hybrid Configuration Prefetching for Partial Reconfigurable Coprocessor.	IPDPS	2007	DBLP DOI BibTeX RDF
6	Konrad Malkowski, Greg M. Link, Padma Raghavan, Mary Jane Irwin	Load Miss Prediction - Exploiting Power Performance Trade-offs.	IPDPS	2007	DBLP DOI BibTeX RDF
6	Nicolas Fournel, Antoine Fraboulet, Paul Feautrier	eSimu: a Fast and Accurate Energy Consumption Simulator for Real Embedded System.	WOWMOM	2007	DBLP DOI BibTeX RDF
6	Guan Yu, Gauthier Lafruit, Peter Schelkens	Platform-scalable Task Partition and Multilevel Buffering in Multi-processor Plessey Corner Detector.	ACSD	2007	DBLP DOI BibTeX RDF
6	Reinaldo A. Bergamaschi, Indira Nair, Gero Dittmann, Hiren D. Patel, Geert Janssen, Nagu R. Dhanwada, Alper Buyuktosunoglu, Emrah Acar, Gi-Joon Nam, Dorothy Kucar, Pradip Bose, John A. Darringer, Guoling Han	Performance modeling for early analysis of multi-core systems.	CODES+ISSS	2007	DBLP DOI BibTeX RDF	early analysis, multi-core systems modeling, physical analysis, performance, power analysis, transaction-level modeling
6	Srinivasan Murali, Almir Mutapcic, David Atienza, Rajesh Gupta 0001, Stephen P. Boyd, Giovanni De Micheli	Temperature-aware processor frequency assignment for MPSoCs using convex optimization.	CODES+ISSS	2007	DBLP DOI BibTeX RDF	temperature-aware, MPSoCs, convex optimization, thermal
6	Gilles Sassatelli, Nicolas Saint-Jean, Pascal Benoit, Lionel Torres, Michel Robert, Cristiane R. Woszezenki, Ismael Grehs, Fernando Gehm Moraes	Run-time mapping and communication strategies for Homogeneous NoC-Based MPSoCs.	FCCM	2007	DBLP DOI BibTeX RDF
6	Junqing Sun, Gregory D. Peterson, Olaf O. Storaasli	Sparse Matrix-Vector Multiplication Design on FPGAs.	FCCM	2007	DBLP DOI BibTeX RDF
6	Ali-Reza Adl-Tabatabai, Anwar M. Ghuloum, Shobhit O. Kanaujia	Compression in cache design.	ICS	2007	DBLP DOI BibTeX RDF	cache compression, prefetching, cache design
6	Martin Schoeberl, Jan Vitek	Garbage collection for safety critical Java.	JTRES	2007	DBLP DOI BibTeX RDF	real-time system, garbage collection
6	Mahdiar Hosein Ghadiry, Mahdieh Nadi Senjani, M. T. Manzuri-Shalmani, Dara Rahmati	Effect of number of faults on NoC power and performance.	ICPADS	2007	DBLP DOI BibTeX RDF
6	Dietmar Ebner, Florian Brandner, Andreas Krall	Leveraging Predicated Execution for Multimedia Processing.	ESTIMedia	2007	DBLP DOI BibTeX RDF
6	Massimo Alioto, Massimo Poli, Santina Rocchi, Valerio Vignoli	Mixed Techniques to Protect Precharged Busses against Differential Power Analysis Attacks.	ISCAS	2007	DBLP DOI BibTeX RDF
6	Fengguang Song, Shirley Moore, Jack J. Dongarra	L2 Cache Modeling for Scientific Applications on Chip Multi-Processors.	ICPP	2007	DBLP DOI BibTeX RDF	cache performance modeling, architecture, chip multi-processor, multi-threaded programming
6	Amit Kumar 0002, Li-Shiuan Peh, Partha Kundu, Niraj K. Jha	Express virtual channels: towards the ideal interconnection fabric.	ISCA	2007	DBLP DOI BibTeX RDF	packet-switching, flow-control, router design
6	Jongman Kim, Chrysostomos Nicopoulos, Dongkook Park, Reetuparna Das, Yuan Xie 0001, Narayanan Vijaykrishnan, Mazin S. Yousif, Chita R. Das	A novel dimensionally-decomposed router for on-chip communication in 3D architectures.	ISCA	2007	DBLP DOI BibTeX RDF	3D architecture, 3D integration, network-on-chip (NoC)
6	Thomas F. Wenisch, Anastassia Ailamaki, Babak Falsafi, Andreas Moshovos	Mechanisms for store-wait-free multiprocessors.	ISCA	2007	DBLP DOI BibTeX RDF	store buffer design, memory consistency models
6	Paolo Costa, Luca Mottola, Amy L. Murphy, Gian Pietro Picco	Programming Wireless Sensor Networks with the TeenyLimeMiddleware.	Middleware	2007	DBLP DOI BibTeX RDF	Wireless sensor and actuator networks, middleware, tuple spaces
6	Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. Dutt, Juanjo Noguera	Selective Band width and Resource Management in Scheduling for Dynamically Reconfigurable Architectures.	DAC	2007	DBLP DOI BibTeX RDF
6	Matteo Monchiero, Gianluca Palermo, Cristina Silvano, Oreste Villa	Efficient Synchronization for Embedded On-Chip Multiprocessors.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
6	Divya Arora, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha	Hardware-Assisted Run-Time Monitoring for Secure Program Execution on Embedded Processors.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
6	Stephen A. Edwards, Olivier Tardieu	SHIM: a deterministic model for heterogeneous embedded systems.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
6	Xinping Zhu, Wei Qin, Sharad Malik	Modeling operation and microarchitecture concurrency for communication architectures with application to retargetable simulation.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
6	Ilya Ganusov, Martin Burtscher	Future execution: A prefetching mechanism that uses multiple cores to speed up single threads.	ACM Trans. Archit. Code Optim.	2006	DBLP DOI BibTeX RDF	Future execution, chip multiprocessors, prefetching, memory wall
6	Wei Zhang 0002, Yuh-Fang Tsai, David Duarte, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin	Reducing dynamic and leakage energy in VLIW architectures.	ACM Trans. Embed. Comput. Syst.	2006	DBLP DOI BibTeX RDF	dynamic energy, schedule slacks, compiler, VLIW architecture, leakage energy
6	Jiang Xu 0001, Wayne H. Wolf, Jörg Henkel, Srimat T. Chakradhar	A design methodology for application-specific networks-on-chip.	ACM Trans. Embed. Comput. Syst.	2006	DBLP DOI BibTeX RDF	regular topology, architecture, methodology, networks-on-chip, Application-specific
6	Prabhat Mishra 0001, Aviral Shrivastava, Nikil D. Dutt	Architecture description language (ADL)-driven software toolkit generation for architectural exploration of programmable SOCs.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	programmable architecture, design space exploration, Architecture description language, embedded processor, retargetable compilation
6	Dongkook Park, Chrysostomos Nicopoulos, Jongman Kim, Narayanan Vijaykrishnan, Chita R. Das	Exploring Fault-Tolerant Network-on-Chip Architectures.	DSN	2006	DBLP DOI BibTeX RDF
6	N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk	On-Chip Communication in Run-Time Assembled Reconfigurable Systems.	ICSAMOS	2006	DBLP DOI BibTeX RDF
6	Massimo Alioto, Massimo Poli, Santina Rocchi, Valerio Vignoli	Power Modeling of Precharged Address Bus and Application to Multi-bit DPA Attacks to DES Algorithm.	PATMOS	2006	DBLP DOI BibTeX RDF
6	Massimo Alioto, Massimo Poli, Santina Rocchi, Valerio Vignoli	Techniques to Enhance the Resistance of Precharged Busses to Differential Power Analysis.	PATMOS	2006	DBLP DOI BibTeX RDF
6	Ali Habibi, Haja Moinudeen, Amer Samarah, Sofiène Tahar	Towards a Faster Simulation of SystemC Designs.	ISVLSI	2006	DBLP DOI BibTeX RDF
6	Matteo Monchiero, Gianluca Palermo, Cristina Silvano, Oreste Villa	Power/performance hardware optimization for synchronization intensive applications in MPSoCs.	DATE	2006	DBLP DOI BibTeX RDF
6	Franco Fummi, Davide Quaglia, Fabio Ricciato, Maura Turolla	Modeling and simulation of mobile gateways interacting with wireless sensor networks.	DATE Designers' Forum	2006	DBLP DOI BibTeX RDF
6	Dohyung Kim 0007, Soonhoi Ha, Rajesh Gupta 0001	Parallel co-simulation using virtual synchronization with redundant host execution.	DATE	2006	DBLP DOI BibTeX RDF
6	Florin Dumitrascu, Iuliana Bacivarov, Lorenzo Pieralisi, Marius Bonaciu, Ahmed Amine Jerraya	Flexible MPSoC platform with fast interconnect exploration for optimal system performance for a specific application.	DATE Designers' Forum	2006	DBLP DOI BibTeX RDF
6	Andrea Alimonda, Andrea Acquaviva, Salvatore Carta, Alessandro Pisano	A control theoretic approach to run-time energy optimization of pipelined processing in MPSoCs.	DATE	2006	DBLP DOI BibTeX RDF
6	Martino Ruggiero, Alessio Guerri, Davide Bertozzi, Francesco Poletti, Michela Milano	Communication-aware allocation and scheduling framework for stream-oriented multi-processor systems-on-chip.	DATE	2006	DBLP DOI BibTeX RDF
6	Partha Biswas, Nikil D. Dutt, Paolo Ienne, Laura Pozzi	Automatic identification of application-specific functional units with architecturally visible storage.	DATE	2006	DBLP DOI BibTeX RDF
6	Robert G. Dimond, Oskar Mencer, Wayne Luk	Automating processor customisation: optimised memory access and resource sharing.	DATE	2006	DBLP DOI BibTeX RDF
6	Jared C. Smolens, Brian T. Gold, Babak Falsafi, James C. Hoe	Reunion: Complexity-Effective Multicore Redundancy.	MICRO	2006	DBLP DOI BibTeX RDF
6	Chrysostomos Nicopoulos, Dongkook Park, Jongman Kim, Narayanan Vijaykrishnan, Mazin S. Yousif, Chita R. Das	ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers.	MICRO	2006	DBLP DOI BibTeX RDF
6	Yuan Cai, Marcus T. Schmitz, Alireza Ejlali, Bashir M. Al-Hashimi, Sudhakar M. Reddy	Cache size selection for performance, energy and reliability of time-constrained systems.	ASP-DAC	2006	DBLP DOI BibTeX RDF
6	Ikhwan Lee, Hyunsuk Kim, Peng Yang, Sungjoo Yoo, Eui-Young Chung, Kyu-Myung Choi, Jeong-Taek Kong, Soo-Kwan Eo	PowerViP: Soc power estimation framework at transaction level.	ASP-DAC	2006	DBLP DOI BibTeX RDF
6	Haiyan Li, Chunyuan Zhang, Li Li 0005, Ming Pang	A Streaming Implementation of Transform and Quantization in H.264.	HPCC	2006	DBLP DOI BibTeX RDF
6	Ana Lucia Varbanescu, Henk J. Sips, Arjan J. C. van Gemund	PAM-SoC: A Toolchain for Predicting MPSoC Performance.	Euro-Par	2006	DBLP DOI BibTeX RDF
6	Euripides Sotiriades, Christos Kozanitis, Apostolos Dollas	FPGA based architecture for DNA sequence comparison and database search.	IPDPS	2006	DBLP DOI BibTeX RDF
6	Riad Ben Mouhoub, Omar Hammami	Multiprocessor on chip: beating the simulation wall through multiobjective design space exploration with direct execution.	IPDPS	2006	DBLP DOI BibTeX RDF
6	Konrad Malkowski, Ingyu Lee, Padma Raghavan, Mary Jane Irwin	Conjugate gradient sparse solvers: performance-power characteristics.	IPDPS	2006	DBLP DOI BibTeX RDF
6	Divya Arora, Anand Raghunathan, Srivaths Ravi 0001, Niraj K. Jha	Architectural support for safe software execution on embedded processors.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	type safety, memory safety, extensible processors
6	Noel Eisley, Vassos Soteriou, Li-Shiuan Peh	High-level power analysis for multi-core chips.	CASES	2006	DBLP DOI BibTeX RDF	simulation, chip multiprocessor (CMP), multi-core, power analysis, system-on-a-chip (SoC)
6	Sayaka Akioka, Konrad Malkowski, Padma Raghavan, Mary Jane Irwin, Lois C. McInnes, Boyana Norris	Characterizing the Performance and Energy Attributes of Scientific Simulations.	International Conference on Computational Science (1)	2006	DBLP DOI BibTeX RDF