Search results for "electromigration"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
18	M. H. Lin, K. P. Chang, K. C. Su, Tahui Wang	Effects of width scaling and layout variation on dual damascene copper interconnect electromigration.	Microelectron. Reliab.	2007	DBLP DOI BibTeX RDF
18	Yi-Shao Lai, Kuo-Ming Chen, Chin-Li Kao, Chiu-Wen Lee, Ying-Ta Chiu	Electromigration of Sn-37Pb and Sn-3Ag-1.5Cu/Sn-3Ag-0.5Cu composite flip-chip solder bumps with Ti/Ni(V)/Cu under bump metallurgy.	Microelectron. Reliab.	2007	DBLP DOI BibTeX RDF
18	Wei Li, Cher Ming Tan	Enhanced finite element modelling of Cu electromigration using ANSYS and matlab.	Microelectron. Reliab.	2007	DBLP DOI BibTeX RDF
18	J. R. Lloyd	Black's law revisited - Nucleation and growth in electromigration failure.	Microelectron. Reliab.	2007	DBLP DOI BibTeX RDF
18	Kimihiro Yamanaka, Yutaka Tsukada, Katsuaki Suganuma	Studies on solder bump electromigration in Cu/Sn-3Ag-0.5Cu/Cu system.	Microelectron. Reliab.	2007	DBLP DOI BibTeX RDF
18	Rani S. Ghaida, Payman Zarkesh-Ha	Estimation of Electromigration-Aggravating Narrow Interconnects Using a Layout Sensitivity Model.	DFT	2007	DBLP DOI BibTeX RDF
18	Cher Ming Tan, Wei Li, Kok Tong Tan, Frankie Low	Development of highly accelerated electromigration test.	Microelectron. Reliab.	2006	DBLP DOI BibTeX RDF
18	A. S. Oates, Shou-Chung Lee	Electromigration failure distributions of dual damascene Cu /low - k interconnects.	Microelectron. Reliab.	2006	DBLP DOI BibTeX RDF
18	Arijit Roy 0001, Cher Ming Tan	Experimental investigation on the impact of stress free temperature on the electromigration performance of copper dual damascene submicron interconnect.	Microelectron. Reliab.	2006	DBLP DOI BibTeX RDF
18	Kuo-Ming Chen, J. D. Wu, Kuo-Ning Chiang	Effects of pre-bump probing and bumping processes on eutectic solder bump electromigration.	Microelectron. Reliab.	2006	DBLP DOI BibTeX RDF
18	Toru Miyazaki, Tomoya Omata	Electromigration degradation mechanism for Pb-free flip-chip micro solder bumps.	Microelectron. Reliab.	2006	DBLP DOI BibTeX RDF
18	Hideaki Tsuchiya, Shinji Yokogawa	Electromigration lifetimes and void growth at low cumulative failure probability.	Microelectron. Reliab.	2006	DBLP DOI BibTeX RDF
18	Chao-Kun Hu, Lynne M. Gignac, R. Rosenberg	Electromigration of Cu/low dielectric constant interconnects.	Microelectron. Reliab.	2006	DBLP DOI BibTeX RDF
18	M. Y. Yan, King-Ning Tu, A. V. Vairagar, S. G. Mhaisalkar, Ahila Krishnamoorthy	A direct measurement of electromigration induced drift velocity in Cu dual damascene interconnects.	Microelectron. Reliab.	2006	DBLP DOI BibTeX RDF
18	Karen Chow, David Abercrombie, Mark Basel	Method for Managing Electromigration in SOC'S When Designing for Both Reliability and Manufacturing.	SoCC	2006	DBLP DOI BibTeX RDF
18	Cher Ming Tan, Arijit Roy 0001, Kok Tong Tan, Derek Sim Kwang Ye, Frankie Low	Effect of vacuum break after the barrier layer deposition on the electromigration performance of aluminum based line interconnects.	Microelectron. Reliab.	2005	DBLP DOI BibTeX RDF
18	M. H. Lin, Y. L. Lin, K. P. Chang, K. C. Su, Tahui Wang	Copper interconnect electromigration behaviors in various structures and lifetime improvement by cap/dielectric interface treatment.	Microelectron. Reliab.	2005	DBLP DOI BibTeX RDF
18	Arijit Roy 0001, Cher Ming Tan, Rakesh Kumar, Xian Tong Chen	Effect of test condition and stress free temperature on the electromigration failure of Cu dual damascene submicron interconnect line-via test structures.	Microelectron. Reliab.	2005	DBLP DOI BibTeX RDF
18	John W. Barrett 0001, Robert Nürnberg, Vanessa Styles	Finite Element Approximation of a Phase Field Model for Void Electromigration.	SIAM J. Numer. Anal.	2004	DBLP DOI BibTeX RDF
18	Mario R. Casu, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni	An electromigration and thermal model of power wires for a priori high-level reliability prediction.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
18	A. V. Vairagar, S. G. Mhaisalkar, Ahila Krishnamoorthy	Electromigration behavior of dual-damascene Cu interconnects--Structure, width, and length dependences.	Microelectron. Reliab.	2004	DBLP DOI BibTeX RDF
18	Christine S. Hau-Riege	An introduction to Cu electromigration.	Microelectron. Reliab.	2004	DBLP DOI BibTeX RDF
18	Leen Biesemans, K. Schepers, Kris Vanstreels, Jan D'Haen, Ward De Ceuninck, Marc D'Olieslaeger	MTF test system with AC based dynamic joule correction for electromigration tests on interconnects.	Microelectron. Reliab.	2004	DBLP DOI BibTeX RDF
18	Maurizio Impronta, Sandro Farris, Andrea Scorzoni	An improved isothermal electromigration test for Cu-damascene characterization.	Microelectron. Reliab.	2004	DBLP DOI BibTeX RDF
18	Insu Jeon, Young-Bae Park	Analysis of the reservoir effect on electromigration reliability.	Microelectron. Reliab.	2004	DBLP DOI BibTeX RDF
18	Roman Barsky, Israel A. Wagner	Electromigration-dependent parametric yield estimation.	ICECS	2004	DBLP DOI BibTeX RDF
18	C. Pennetta, Lino Reggiani, E. Alfinito	Monte Carlo simulation of electromigration phenomena in metallic lines.	Math. Comput. Simul.	2003	DBLP DOI BibTeX RDF
18	Sherry Suat Cheng Khoo, Pee Ya Tan, Steven H. Voldman	Microanalysis and electromigration reliability performance of high current transmission line pulse (TLP) stressed copper interconnects.	Microelectron. Reliab.	2003	DBLP DOI BibTeX RDF
18	Masashi Hayashi, Shinji Nakano, Tetsuaki Wada	Dependence of copper interconnect electromigration phenomenon on barrier metal materials.	Microelectron. Reliab.	2003	DBLP DOI BibTeX RDF
18	Glenn A. Rinne	Issues in accelerated electromigration of solder bumps.	Microelectron. Reliab.	2003	DBLP DOI BibTeX RDF
18	Jens Lienig, Göran Jerke	Current-driven wire planning for electromigration avoidance in analog circuits.	ASP-DAC	2003	DBLP DOI BibTeX RDF
18	Ennis T. Ogawa, Ki-Don Lee, Volker A. Blaschke, Paul S. Ho	Electromigration reliability issues in dual-damascene Cu interconnections.	IEEE Trans. Reliab.	2002	DBLP DOI BibTeX RDF
18	Alfred F. K. Zehe	Prediction of electromigration-void formation in copper conductors based on the electron configuration of matrix and solute atoms.	Microelectron. Reliab.	2002	DBLP DOI BibTeX RDF
18	Hajdin Ceric, Siegfried Selberherr	Simulative prediction of the resistance change due to electromigration induced void evolution.	Microelectron. Reliab.	2002	DBLP DOI BibTeX RDF
18	H. V. Nguyen, Cora Salm, R. Wenzel, A. J. Mouthaan, Fred G. Kuper	Simulation and experimental characterization of reservoir and via layout effects on electromigration lifetime.	Microelectron. Reliab.	2002	DBLP DOI BibTeX RDF
18	Graziella Scandurra, Carmine Ciofi, Calogero Pace, F. Speroni, F. Alagi	True constant temperature MTF test system for the characterization of electromigration of thick Cu interconnection lines.	Microelectron. Reliab.	2002	DBLP DOI BibTeX RDF
18	H. V. Nguyen, Cora Salm, J. Vroemen, J. Voets, Benno Krabbenborg, Jaap Bisschop, A. J. Mouthaan, Fred G. Kuper	Fast temperature cycling and electromigration induced thin film cracking in multilevel interconnection: experiments and modeling.	Microelectron. Reliab.	2002	DBLP DOI BibTeX RDF
18	M. R. Carriero, Stefano Di Pascoli, Giuseppe Iannaccone	Simulation of failure time distributions of metal lines under electromigration.	Microelectron. Reliab.	2002	DBLP DOI BibTeX RDF
18	C. Caprile, Ilaria De Munari, Maurizio Impronta, Simona Podda, Andrea Scorzoni, Massimo Vanzi	A specimen-current branching approach for FA of long Electromigration test lines.	Microelectron. Reliab.	2002	DBLP DOI BibTeX RDF
18	J. Joseph Clement	Electromigration Reliability Issues in High-Performance Circuit Design (Tutorial Abstract).	ISQED	2002	DBLP DOI BibTeX RDF
18	Kris Croes, R. Dreesen, Jean Manca, Ward De Ceuninck, Luc De Schepper, Luc Tielemans, P. J. van der Wel	High-resolution in-situ of gold electromigration: test time reduction.	Microelectron. Reliab.	2001	DBLP DOI BibTeX RDF
18	A. H. Fischer, A. Abel, M. Lepper, A. E. Zitzelsberger, A. von Glasow	Modeling bimodal electromigration failure distributions.	Microelectron. Reliab.	2001	DBLP DOI BibTeX RDF
18	Hide Murayama, Makoto Yamazaki, Shigeru Nakajima	Electromigration and electrochemical reaction mixed failure mechanism in gold interconnection system.	Microelectron. Reliab.	2001	DBLP DOI BibTeX RDF
18	Shinji Yokogawa, Norio Okada, Yumi Kakuhara, Hideyuki Takizawa	Electromigration Performance of Multi-level Damascene Copper Interconnects.	Microelectron. Reliab.	2001	DBLP DOI BibTeX RDF
18	M. K. Mazumder, S. Yamamoto, H. Maeda, J. Komori, Y. Mashiko	Mechanism of pre-annealing effect on electromigration immunity of Al-Cu line.	Microelectron. Reliab.	2001	DBLP DOI BibTeX RDF
18	Kaustav Banerjee, Amit Mehrotra	Coupled Analysis of Electromigration Reliability and Performance in ULSI Signal Nets.	ICCAD	2001	DBLP DOI BibTeX RDF
18	Carmine Ciofi, Ivan Ciofi, Stefano C. Di Pascoli, Bruno Neri	Temperature controlled oven for low noise measurement systems [for electromigration characterization].	IEEE Trans. Instrum. Meas.	2000	DBLP DOI BibTeX RDF
18	Irving Ames, Francois Max d'Heurle, Richard E. Horstmann	Reduction of electromigration in aluminium films by copper doping.	IBM J. Res. Dev.	2000	DBLP DOI BibTeX RDF
18	Aurobindo Dasgupta, Ramesh Karri	Electromigration Reliability Enhancement via Bus Activity Distribution.	DAC	1996	DBLP DOI BibTeX RDF
18	Chin-Chi Teng, Yi-Kan Cheng, Elyse Rosenbaum, Sung-Mo Kang	Hierarchical Electromigration Reliability Diagnosis for VLSI Interconnects.	DAC	1996	DBLP DOI BibTeX RDF
18	Chao-Kun Hu, Kenneth P. Rodbell, Timothy D. Sullivan, Kim Y. Lee, Dennis P. Bouldin	Electromigration and stress-induced voiding in fine Al and Al-alloy thin-film lines.	IBM J. Res. Dev.	1995	DBLP DOI BibTeX RDF
18	Kaushik Roy 0001, Sharat Prasad	Logic synthesis for reliability - an early start to controlling electromigration and hot carrier effects.	EURO-DAC	1994	DBLP DOI BibTeX RDF
18	J. Joseph Clement, Eugenia M. Atakov, James R. Lloyd	Electromigration Reliability of VLSI Interconnect.	Digit. Tech. J.	1992	DBLP BibTeX RDF
18	E. Weis, E. Kinsbron, M. Snyder, B. Vogel, N. Croitoru	Electromigration Effects in VLSI Due to Various Current Types.	ITC	1991	DBLP DOI BibTeX RDF
18	Jerry P. Hwang	REX - A VLSI Parasitic Extraction Tool for Electromigration and Signal Analysis.	DAC	1991	DBLP DOI BibTeX RDF
18	Farid N. Najm, Ibrahim N. Hajj, Ping Yang 0001	Electromigration median time-to-failure based on a stochastic current waveform.	ICCD	1989	DBLP DOI BibTeX RDF
14	Pedro Marques Morgado, Paulo F. Flores, L. Miguel Silveira	Generating realistic stimuli for accurate power grid analysis.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	stimuli generation, simulation, verification, Power grid, ground bounce, voltage drop
14	Adam C. Cabe, Zhenyu Qi, Stuart N. Wooters, Travis N. Blalock, Mircea R. Stan	Small embeddable NBTI sensors (SENS) for tracking on-chip performance decay.	ISQED	2009	DBLP DOI BibTeX RDF
14	K. C. Narasimhamurthy, Roy P. Paily	Impact of Bias Voltage on Magnetic Inductance of Carbon Nanotube Interconnects.	VLSI Design	2009	DBLP DOI BibTeX RDF
14	Eric Karl, David T. Blaauw, Dennis Sylvester, Trevor N. Mudge	Multi-Mechanism Reliability Modeling and Management in Dynamic Systems.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
14	Andrew Labun, Karan Jagjitkumar	Rapid Detailed Temperature Estimation for Highly Coupled IC Interconnect.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
14	Pedro Marques Morgado, Paulo F. Flores, José C. Monteiro 0001, Luís Miguel Silveira	Generating Worst-Case Stimuli for Accurate Power Grid Analysis.	PATMOS	2008	DBLP DOI BibTeX RDF
14	Prasanth Mangalagiri, Sungmin Bae, Krishnan Ramakrishnan, Yuan Xie 0001, Vijaykrishnan Narayanan	Thermal-aware reliability analysis for platform FPGAs.	ICCAD	2008	DBLP DOI BibTeX RDF
14	Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir	Thermal Aware Global Routing of VLSI Chips for Enhanced Reliability.	ISQED	2008	DBLP DOI BibTeX RDF	reliability, global routing, thermal
14	Eric Karl, Dennis Sylvester, David T. Blaauw	Analysis of System-Level Reliability Factors and Implications on Real-Time Monitoring Methods for Oxide Breakdown Device Failures.	ISQED	2008	DBLP DOI BibTeX RDF
14	Zhijian Lu, Wei Huang 0004, Mircea R. Stan, Kevin Skadron, John C. Lach	Interconnect Lifetime Prediction for Reliability-Aware Systems.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
14	Pedro Marques Morgado, Paulo F. Flores, L. Miguel Silveira	Generating Realistic Stimuli for Accurate Power Grid Analysis.	ISVLSI	2007	DBLP DOI BibTeX RDF
14	Arthur Nieuwoudt, Mosin Mondal, Yehia Massoud	Predicting the Performance and Reliability of Carbon Nanotube Bundles for On-Chip Interconnect.	ASP-DAC	2007	DBLP DOI BibTeX RDF
14	Aida Todri, Malgorzata Marek-Sadowska, Shih-Chieh Chang	Analysis and optimization of power-gated ICs with multiple power gating configurations.	ICCAD	2007	DBLP DOI BibTeX RDF
14	Kanak Agarwal, Frank Liu 0001	Efficient computation of current flow in signal wires for reliability analysis.	ICCAD	2007	DBLP DOI BibTeX RDF
14	I-Jye Lin, Tsui-Yee Ling, Yao-Wen Chang	Statistical circuit optimization considering device andinterconnect process variations.	SLIP	2007	DBLP DOI BibTeX RDF	gate and wire sizing, statistical optimization
14	Sule Ozev, Daniel J. Sorin, Mahmut Yilmaz	Low-cost run-time diagnosis of hard delay faults in the functional units of a microprocessor.	ICCD	2007	DBLP DOI BibTeX RDF
14	Chang-Tzu Lin, Tai-Wei Kung, De-Sheng Chen, Yiwen Wang 0003, Ching-Hwa Cheng	Noise-Aware Floorplanning for Fast Power Supply Network Design.	ISCAS	2007	DBLP DOI BibTeX RDF
14	Kambiz Rahimi	Minimizing peak power in synchronous logic circuits.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	power optimization, peak power, clock scheduling
14	Yehia Massoud, Arthur Nieuwoudt	Modeling and design challenges and solutions for carbon nanotube-based interconnect in future high performance integrated circuits.	ACM J. Emerg. Technol. Comput. Syst.	2006	DBLP DOI BibTeX RDF	nanotube bundle, interconnect, inductance, Carbon nanotube, resistance
14	Jürgen Rauscher, Hans-Jörg Pfleiderer	Sensitivity of a Power Supply Damping Method to Resistance and Current Waveform Variations.	PATMOS	2006	DBLP DOI BibTeX RDF
14	Shih-Hsu Huang, Chun-Hua Cheng, Chung-Hsin Chiang, Chia-Ming Chang 0002	Peak Power Minimization through Power Management Scheduling.	APCCAS	2006	DBLP DOI BibTeX RDF
14	Jin-Tai Yan, Chia-Wei Wu, Yen-Hsiang Chen	Wiring area optimization in floorplan-aware hierarchical power grids.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
14	Muzhou Shao, Youxin Gao, Li-Pen Yuan, Hung-Ming Chen, Martin D. F. Wong	Current Calculation on VLSI Signal Interconnects.	ISQED	2005	DBLP DOI BibTeX RDF
14	Jinan Lou, Wei Chen	Crosstalk-Aware Placement.	IEEE Des. Test Comput.	2004	DBLP DOI BibTeX RDF
14	Jayanth Srinivasan, Sarita V. Adve, Pradip Bose, Jude A. Rivers	The Impact of Technology Scaling on Lifetime Reliability.	DSN	2004	DBLP DOI BibTeX RDF
14	Robert A. Mullen	RF design methodologies bridging system-IC-module design.	ASP-DAC	2004	DBLP DOI BibTeX RDF
14	Alain Salles, Bruno Estibals, Corinne Alonso	Electro-thermal study of nano-inductors for integrated low power converters.	ISCAS (3)	2004	DBLP DOI BibTeX RDF
14	Syed M. Alam, Chee Lip Gan, Carl V. Thompson, Donald E. Troxel	Circuit Level Reliability Analysis of Cu Interconnects.	ISQED	2004	DBLP DOI BibTeX RDF
14	Brian Marshall	Beyond P-Cell and Gate-Level: Accuracy Requirements for Simulation of Nanometer SoC Designs.	IWSOC	2004	DBLP DOI BibTeX RDF
14	Sheldon X.-D. Tan, C.-J. Richard Shi, Jyh-Chwen Lee	Reliability-constrained area optimization of VLSI power/ground networks via sequence of linear programmings.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
14	Yonghee Im, Kaushik Roy 0001	LALM: A Logic-Aware Layout Methodology to Enhance the Noise Immunity of Domino Circuits.	ISVLSI	2003	DBLP DOI BibTeX RDF
14	Eli Chiprout	Early electrical wire projections and implications.	SLIP	2003	DBLP DOI BibTeX RDF
14	Martijn T. Bennebroek	Validation of wire length distribution models on commercial designs.	SLIP	2003	DBLP DOI BibTeX RDF
14	Yonghee Im, Kaushik Roy 0001	A logic-aware layout methodology to enhance the noise immunity of domino circuits.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
14	Ralph H. J. M. Otten, Raul Camposano, Patrick Groeneveld	Design Automation for Deepsubmicron: Present and Future.	DATE	2002	DBLP DOI BibTeX RDF
14	Sung-Mo Kang	On-chip thermal engineering for peta-scale integration.	ISPD	2002	DBLP DOI BibTeX RDF
14	Shih-Hsu Huang, Chu-Liao Wang	An effective floorplan-based power distribution network design methodology under reliability constraints.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
14	Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni	Hierarchical power supply noise evaluation for early power grid design prediction.	SLIP	2001	DBLP DOI BibTeX RDF
14	Kenneth Rose	A comprehensive look at system level model.	SLIP	2001	DBLP DOI BibTeX RDF
14	Gulsun Yasar, Charles Chiu, Robert A. Proctor, James P. Libous	I/O Cell Placement and Electrical Checking Methodology for ASICs with Peripheral I/Os.	ISQED	2001	DBLP DOI BibTeX RDF
14	Sabyasachi Sengupta, Somavalli Ramanathan, Biswadeep Chatterjee, Dibyendu Goswami	Minimizing Area and Maximizing Porosity for Cell Layouts Using Innovative Routing Strategies.	VLSI Design	2001	DBLP DOI BibTeX RDF
14	Nagaraj Ns, Frank Cano, Sudha Thiruvengadam, Deepak Kapoor	Performance and Reliability Verification of C6201/C6701 Digital Signal Processors.	ICCD	1999	DBLP DOI BibTeX RDF
14	Markus Wolf 0001, Ulrich Kleine	Reliability driven module generation for analog layouts.	ISCAS (6)	1999	DBLP DOI BibTeX RDF
14	Bernard A. McCoy, Gabriel Robins	Non-tree routing [VLSI layout].	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF