Search results for "floorplanning"

Hits ?▲	Authors	Title	Venue	Year	Link
17	Atul Prakash 0002, Rajesh Kumar Lal	Floorplanning for Area Optimization Using Parallel Particle Swarm Optimization and Sequence Pair.	Wirel. Pers. Commun.	2021	DBLP DOI BibTeX RDF
17	B. Srinivasan, R. Venkatesan 0002	Multi-objective optimization for energy and heat-aware VLSI floorplanning using enhanced firefly optimization.	Soft Comput.	2021	DBLP DOI BibTeX RDF
17	Licheng Guo, Yuze Chi, Jie Wang 0022, Jason Lau, Weikang Qiao, Ecenur Ustun, Zhiru Zhang, Jason Cong	AutoBridge: Coupling Coarse-Grained Floorplanning and Pipelining for High-Frequency HLS Design on Multi-Die FPGAs.	FPGA	2021	DBLP DOI BibTeX RDF
17	Ganesh Gore, Xifan Tang, Pierre-Emmanuel Gaillardon	A Scalable and Robust Hierarchical Floorplanning to Enable 24-hour Prototyping for 100k-LUT FPGAs.	ISPD	2021	DBLP DOI BibTeX RDF
17	Mert Vatansever, Faik Baskaya	A modified relay-race algorithm for floorplanning in PCB and IC design.	Turkish J. Electr. Eng. Comput. Sci.	2020	DBLP DOI BibTeX RDF
17	Zhipeng Huang 0009, Zhifeng Lin, Ziran Zhu, Jianli Chen	An Improved Simulated Annealing Algorithm With Excessive Length Penalty for Fixed-Outline Floorplanning.	IEEE Access	2020	DBLP DOI BibTeX RDF
17	Lalin L. Laudis, N. Ramadass	A Lion's Pride Inspired Algorithm for VLSI Floorplanning.	J. Circuits Syst. Comput.	2020	DBLP DOI BibTeX RDF
17	Song Chen 0001, Jinglei Huang, Xiaodong Xu, Bo Ding, Qi Xu	Integrated Optimization of Partitioning, Scheduling, and Floorplanning for Partially Dynamically Reconfigurable Systems.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2020	DBLP DOI BibTeX RDF
17	Pingakshya Goswami, Dinesh Bhatia	Automated Floorplanning for Partially Reconfigurable Designs on Heterogenrous FPGAs.	CoRR	2020	DBLP BibTeX RDF
17	Tai-Chen Chen, Pei-Yu Lee, Tung-Chieh Chen	Automatic Floorplanning for AI SoCs.	VLSI-DAT	2020	DBLP DOI BibTeX RDF
17	Tianming Ni, Hao Chang, Shidong Zhu, Lin Lu, Xueyun Li, Qi Xu, Huaguo Liang, Zhengfeng Huang	Temperature-Aware Floorplanning for Fixed-Outline 3D ICs.	IEEE Access	2019	DBLP DOI BibTeX RDF
17	Junyan Tan, Chunhua Cai	An Efficient Partitioning Algorithm Based on Hypergraph for 3D Network-On-Chip Architecture Floorplanning.	J. Circuits Syst. Comput.	2019	DBLP DOI BibTeX RDF
17	Norbert Deak, Octavian Cret, Horia Hedesiu	Efficient FPGA Floorplanning for Partial Reconfiguration-Based Applications.	CoRR	2019	DBLP BibTeX RDF
17	Norbert Deak, Octavian Cret, Horia Hedesiu	Efficient FPGA Floorplanning for Partial Reconfiguration-Based Applications.	FCCM	2019	DBLP DOI BibTeX RDF
17	S. B. Vinay Kumar, P. V. Rao, Manoj Kumar Singh	Multi-culture diversity based self adaptive particle swarm optimization for optimal floorplanning.	Multiagent Grid Syst.	2018	DBLP DOI BibTeX RDF
17	Johann Knechtel, Jens Lienig, Ibrahim Abe M. Elfadel	Multi-Objective 3D Floorplanning with Integrated Voltage Assignment.	ACM Trans. Design Autom. Electr. Syst.	2018	DBLP DOI BibTeX RDF
17	Song Chen 0001, Jinglei Huang, Xiaodong Xu, Qi Xu	Integrated Optimization of Partitioning, Scheduling and Floorplanning for Partially Dynamically Reconfigurable Systems.	CoRR	2018	DBLP BibTeX RDF
17	Subrata Das, Debesh Kumar Das	Floorplanning in Graphene Nanoribbon (GNR) Based Circuits.	ISVLSI	2018	DBLP DOI BibTeX RDF
17	Sara Vinco, Lorenzo Bottaccioli, Edoardo Patti, Andrea Acquaviva, Enrico Macii, Massimo Poncino	GIS-based optimal photovoltaic panel floorplanning for residential installations.	DATE	2018	DBLP DOI BibTeX RDF
17	Jai-Ming Lin, Chien-Yu Huang	General floorplanning methodology for 3D ICs with an arbitrary bonding style.	DATE	2018	DBLP DOI BibTeX RDF
17	Jai-Ming Lin, Chien-Yu Huang, Jhih-Ying Yang	Co-synthesis of floorplanning and powerplanning in 3D ICs for multiple supply voltage designs.	DATE	2018	DBLP DOI BibTeX RDF
17	François Galea, Sergiu Carpov, Lilia Zaourar	Multi-start simulated annealing for partially-reconfigurable FPGA floorplanning.	IPDPS Workshops	2018	DBLP DOI BibTeX RDF
17	Chao Geng, Shigetoshi Nakatake	Hierarchical Floorplanning Based on Analog Structure Tree.	NGCAS	2018	DBLP DOI BibTeX RDF
17	Jai-Ming Lin, Tai-Ting Chen, Yen-Fu Chang, Wei-Yi Chang, Ya-Ting Shyu, Yeong-Jar Chang, Juin-Ming Lu	A fast thermal-aware fixed-outline floorplanning methodology based on analytical models.	ICCAD	2018	DBLP DOI BibTeX RDF
17	Sara Vinco, Enrico Macii, Massimo Poncino	Optimal Topology-Aware PV Panel Floorplanning with Hybrid Orientation.	ACM Great Lakes Symposium on VLSI	2018	DBLP DOI BibTeX RDF
17	Francisco Eugenio Potestad-Ordóñez, Carlos Jesús Jiménez-Fernández, Carmen Baena Oliva, Pilar Parra Fernández, Manuel Valencia-Barrero	Floorplanning as a practical countermeasure against clock fault attack in Trivium stream cipher.	DCIS	2018	DBLP DOI BibTeX RDF
17	Piotr Zajac, Melvin Galicia, Andrzej Napieralski	Thermal-aware Floorplanning Guidelines for 3D ICs with Integrated Microchannels.	MIXDES	2018	DBLP DOI BibTeX RDF
17	P. Sivaranjani, A. Senthil Kumar	Hybrid Particle Swarm Optimization-Firefly algorithm (HPSOFF) for combinatorial optimization of non-slicing VLSI floorplanning.	J. Intell. Fuzzy Syst.	2017	DBLP DOI BibTeX RDF
17	Bernhard Schmidt, Daniel Ziener, Jürgen Teich, Christian Zöllner 0003	Optimizing scrubbing by netlist analysis for FPGA configuration bit classification and floorplanning.	Integr.	2017	DBLP DOI BibTeX RDF
17	Behnam Khodabandeloo, Ahmad Khonsari, Masoomeh Jasemi, Golnaz Taheri	A fast temperature-aware fixed-outline floorplanning framework using convex optimization.	Integr.	2017	DBLP DOI BibTeX RDF
17	Qi Xu, Song Chen 0001	Fast thermal analysis for fixed-outline 3D floorplanning.	Integr.	2017	DBLP DOI BibTeX RDF
17	Jianli Chen, Yan Liu, Ziran Zhu, Wenxing Zhu	An adaptive hybrid memetic algorithm for thermal-aware non-slicing VLSI floorplanning.	Integr.	2017	DBLP DOI BibTeX RDF
17	Pengli Ji, Kun He 0001, Yan Jin 0005, Hongsheng Lan, Chumin Li	An iterative merging algorithm for soft rectangle packing and its extension for application of fixed-outline floorplanning of soft modules.	Comput. Oper. Res.	2017	DBLP DOI BibTeX RDF
17	Marco Rabozzi, Gianluca Carlo Durelli, Antonio Miele, John Lillis, Marco Domenico Santambrogio	Floorplanning Automation for Partial-Reconfigurable FPGAs via Feasible Placements Generation.	IEEE Trans. Very Large Scale Integr. Syst.	2017	DBLP DOI BibTeX RDF
17	Marta Ortín-Obón, Mahdi Tala, Luca Ramini, Víctor Viñals Yúfera, Davide Bertozzi	Contrasting Laser Power Requirements of Wavelength-Routed Optical NoC Topologies Subject to the Floorplanning, Placement, and Routing Constraints of a 3-D-Stacked System.	IEEE Trans. Very Large Scale Integr. Syst.	2017	DBLP DOI BibTeX RDF
17	Jai-Ming Lin, Jung-An Yang	Routability-Driven TSV-Aware Floorplanning Methodology for Fixed-Outline 3-D ICs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2017	DBLP DOI BibTeX RDF
17	Suchandra Banerjee, Anand Ratna, Suchismita Roy	Satisfiability Modulo Theory based Methodology for Floorplanning in VLSI Circuits.	CoRR	2017	DBLP BibTeX RDF
17	Bernhard Schmidt, Daniel Ziener, Jürgen Teich, Christian Zöllner 0003	Optimizing Scrubbing by Netlist Analysis for FPGA Configuration Bit Classification and Floorplanning.	CoRR	2017	DBLP BibTeX RDF
17	Marco Rabozzi, Giuseppe Natale, Biagio Festa, Antonio Miele, Marco D. Santambrogio	Optimizing streaming stencil time-step designs via FPGA floorplanning.	FPL	2017	DBLP DOI BibTeX RDF
17	Xiaodong Xu, Qi Xu, Jinglei Huang, Song Chen 0001	An Integrated Optimization Framework for Partitioning, Scheduling and Floorplanning on Partially Dynamically Reconfigurable FPGAs.	ACM Great Lakes Symposium on VLSI	2017	DBLP DOI BibTeX RDF
17	Linquan Lyu, Takeshi Yoshimura	A force directed partitioning algorithm for 3D floorplanning.	ASICON	2017	DBLP DOI BibTeX RDF
17	Yanling Zhou, Yunyao Yan, Wei Yan	A method to speed up VLSI hierarchical physical design in floorplanning.	ASICON	2017	DBLP DOI BibTeX RDF
17	Jinyu Wang, Weiguo Wu, Zhaonan Qin, Dongfang Zhao 0005	A Floorplanning Algorithm for Partially Reconfigurable FPGA in Wireless Sensor Network.	SpaCCS Workshops	2017	DBLP DOI BibTeX RDF
17	De-Xuan Zou, Gaige Wang, Gai Pan, Hongwei Qin	A modified simulated annealing algorithm and an excessive area model for floorplanning using fixed-outline constraints.	Frontiers Inf. Technol. Electron. Eng.	2016	DBLP DOI BibTeX RDF
17	Zhufei Chu, Yinshui Xia, Lun-Yao Wang	Multi-supply voltage (MSV) driven SoC floorplanning for fast design convergence.	Integr.	2016	DBLP DOI BibTeX RDF
17	Zhufei Chu, Yinshui Xia, Lun-Yao Wang, Jian Wang	Efficient power pad assignment for multi-voltage SoC and its application in floorplanning.	Int. J. Circuit Theory Appl.	2016	DBLP DOI BibTeX RDF
17	Piotr Zajac, Melvin Galicia, Cezary Maj, Andrzej Napieralski	Impact of floorplanning and thermal vias placement on temperature in 2D and 3D processors.	Microelectron. J.	2016	DBLP DOI BibTeX RDF
17	Jinglei Huang, Song Chen 0001, Wei Zhong, Wenchao Zhang, Shengxi Diao, Fujiang Lin	Floorplanning and Topology Synthesis for Application-Specific Network-on-Chips with RF-Interconnect.	ACM Trans. Design Autom. Electr. Syst.	2016	DBLP DOI BibTeX RDF
17	Qi Xu, Song Chen 0001, Bin Li 0025	Combining the ant system algorithm and simulated annealing for 3D/2D fixed-outline floorplanning.	Appl. Soft Comput.	2016	DBLP DOI BibTeX RDF
17	Hui Zhu, Cong Hao, Takeshi Yoshimura	Thermal-aware floorplanning for NoC-sprinting.	MWSCAS	2016	DBLP DOI BibTeX RDF
17	Pingakshya Goswami, Dinesh Bhatia	Floorplanning of Partially Reconfigurable Design on Heterogeneous FPGA (Abstract Only).	FPGA	2016	DBLP DOI BibTeX RDF
17	Suchandra Banerjee, Anand Ratna, Suchismita Roy	Satisfiability modulo theory based methodology for floorplanning in VLSI circuits.	ISED	2016	DBLP DOI BibTeX RDF
17	Wissem Chouchene, Rabie Ben Atitallah, Jean-Luc Dekeyser	AFFORDe: Automatic Allocation and Floorplanning for SPMD Architecture.	MCSoC	2016	DBLP DOI BibTeX RDF
17	Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal	A Novel EPE Aware Hybrid Global Route Planner after Floorplanning.	VLSID	2016	DBLP DOI BibTeX RDF
17	Artur Quiring	Routing-driven Multiobjective 3D Floorplanning.		2016	RDF
17	Aminollah Mahabadi, Ahmad Khonsari, Behnam Khodabandeloo, Hamid Noori, Alireza Majidi	Critical path-aware voltage island partitioning and floorplanning for hard real-time embedded systems.	Integr.	2015	DBLP DOI BibTeX RDF
17	Xiaodao Chen, Lizhe Wang 0001, Albert Y. Zomaya, Lin Liu 0013, Shiyan Hu	Cloud Computing for VLSI Floorplanning Considering Peak Temperature Reduction.	IEEE Trans. Emerg. Top. Comput.	2015	DBLP DOI BibTeX RDF
17	Dakun Zhang, Guozhi Song, Kunliang Liu, Yong Ma, Chenglong Zhao, Xu An Wang 0001	Comprehensive Improved Simulated Annealing Optimization for Floorplanning of Heterogeneous 3D Networks-on-Chip.	J. Interconnect. Networks	2015	DBLP DOI BibTeX RDF
17	P. Sivaranjani, A. Senthil Kumar	Thermal-Aware Non-slicing VLSI Floorplanning Using a Smart Decision-Making PSO-GA Based Hybrid Algorithm.	Circuits Syst. Signal Process.	2015	DBLP DOI BibTeX RDF
17	Andreas Thor Winther, Wei Liu 0016, Alberto Nannarelli, Sarma B. K. Vrudhula	Thermal aware floorplanning incorporating temperature dependent wire delay estimation.	Microprocess. Microsystems	2015	DBLP DOI BibTeX RDF
17	Alfredo Cuesta-Infante, J. Manuel Colmenar, Zorana Bankovic, José L. Risco-Martín, Marina Zapater, José Ignacio Hidalgo, José Luis Ayala, José Manuel Moya	Comparative study of meta-heuristic 3D floorplanning algorithms.	Neurocomputing	2015	DBLP DOI BibTeX RDF
17	Chyi-Shiang Hoo, Kanesan Jeevan, Harikrishnan Ramiah	Cost reduction in bottom-up hierarchical-based VLSI floorplanning designs.	Int. J. Circuit Theory Appl.	2015	DBLP DOI BibTeX RDF
17	Artur Quiring, Markus Olbrich, Erich Barke	Fast global interconnnect driven 3D floorplanning.	VLSI-SoC	2015	DBLP DOI BibTeX RDF
17	Ying-Jung Chen, Shanq-Jang Ruan	A cluster-based reliability- and thermal-aware 3D floorplanning using redundant STSVs.	VLSI-SoC	2015	DBLP DOI BibTeX RDF
17	Davide Pagano, Mikel Vuka, Marco Rabozzi, Riccardo Cattaneo, Donatella Sciuto, Marco D. Santambrogio	Thermal-aware floorplanning for partially-reconfigurable FPGA-based systems.	DATE	2015	DBLP BibTeX RDF
17	Marco Rabozzi, Riccardo Cattaneo, Tobias Becker, Wayne Luk, Marco D. Santambrogio	Relocation-Aware Floorplanning for Partially-Reconfigurable FPGA-Based Systems.	IPDPS Workshops	2015	DBLP DOI BibTeX RDF
17	Marco Rabozzi, Antonio Miele, Marco D. Santambrogio	Floorplanning for Partially-Reconfigurable FPGAs via Feasible Placements Detection.	FCCM	2015	DBLP DOI BibTeX RDF
17	Kevin E. Murray, Vaughn Betz	HETRIS: Adaptive floorplanning for heterogeneous FPGAs.	FPT	2015	DBLP DOI BibTeX RDF
17	Mohammad A. Ahmed, Sucheta Mohapatra, Malgorzata Chrzanowska-Jeske	Dynamic nets-to-TSVs assignment in 3D floorplanning.	ISCAS	2015	DBLP DOI BibTeX RDF
17	David Guilherme, João Pereira, Nuno Horta, Jorge Guilherme	Thermal-aware floorplanning and layout generation of MOSFET power stages.	ISCAS	2015	DBLP DOI BibTeX RDF
17	Boris Vaisband, Eby G. Friedman	3-D floorplanning algorithm to minimize thermal interactions.	ISCAS	2015	DBLP DOI BibTeX RDF
17	Shengcheng Wang, Farshad Firouzi, Fabian Oboril, Mehdi Baradaran Tahoori	Deadspace-aware Power/Ground TSV planning in 3D floorplanning.	ICICDT	2015	DBLP DOI BibTeX RDF
17	Jai-Ming Lin, Chih-Yao Hu, Kai-Chung Chan	Routability-driven floorplanning algorithm for mixed-size modules with fixed-outline constraint.	VLSI-DAT	2015	DBLP DOI BibTeX RDF
17	Xi Chen, Jiang Hu, Ning Xu 0006	Regularity-constrained floorplanning for multi-core processors.	Integr.	2014	DBLP DOI BibTeX RDF
17	Chyi-Shiang Hoo, Kanesan Jeevan, Harikrishnan Ramiah	Enumeration technique in very large-scale integration fixed-outline floorplanning.	IET Circuits Devices Syst.	2014	DBLP DOI BibTeX RDF
17	Cheoljon Jang, Jaehwan Kim, Jong-Wha Chong	Power-aware floorplanning-based power throughsilicon- via technology and bump minimisation for three-dimensional power delivery network.	IET Comput. Digit. Tech.	2014	DBLP DOI BibTeX RDF
17	Lin Wang	Fast Algorithms for thermal-Aware floorplanning.	J. Circuits Syst. Comput.	2014	DBLP DOI BibTeX RDF
17	Jai-Ming Lin, Ji-Heng Wu	F-FM: Fixed-Outline Floorplanning Methodology for Mixed-Size Modules Considering Voltage-Island Constraint.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2014	DBLP DOI BibTeX RDF
17	Zhufei Chu, Yinshui Xia, Lun-Yao Wang, Jian Wang	Efficient nonrectangular shaped voltage island aware floorplanning with nonrandomized searching engine.	Microelectron. J.	2014	DBLP DOI BibTeX RDF
17	Bei Yu 0001, Sheqin Dong, Song Chen 0001, Satoshi Goto	Floorplanning and Topology Generation for Application-Specific Network-on-Chip.	CoRR	2014	DBLP BibTeX RDF
17	Kun He 0001, Pengli Ji, Chumin Li	An iterative merging placement algorithm for the fixed-outline floorplanning.	CoRR	2014	DBLP BibTeX RDF
17	Bei Yu 0001, Sheqin Dong, Satoshi Goto	Multi-Voltage and Level-Shifter Assignment Driven Floorplanning.	CoRR	2014	DBLP BibTeX RDF
17	Bei Yu 0001, Sheqin Dong, Song Chen 0001, Satoshi Goto	Voltage and Level-Shifter Assignment Driven Floorplanning.	CoRR	2014	DBLP BibTeX RDF
17	Sung Kyu Lim	Research Needs for TSV-Based 3D IC Architectural Floorplanning.	J. Inform. and Commun. Convergence Engineering	2014	DBLP DOI BibTeX RDF
17	Yang Xu 0019, Bo Wang 0010, Jürgen Teich	Parametric yield optimization using leakage-yield-driven floorplanning.	PATMOS	2014	DBLP DOI BibTeX RDF
17	Bernhard Schmidt, Daniel Ziener, Jürgen Teich	An automatic netlist and floorplanning approach to improve the MTTR of scrubbing techniques (abstract only).	FPGA	2014	DBLP DOI BibTeX RDF
17	Indira Rawat, M. K. Gupta, Virendra Singh	Temperature aware test scheduling by modified floorplanning.	EWDTS	2014	DBLP DOI BibTeX RDF
17	Mohammad A. Ahmed, Sucheta Mohapatra, Malgorzata Chrzanowska-Jeske	3D floorplanning with nets-to-TSVs assignment.	ICECS	2014	DBLP DOI BibTeX RDF
17	Bernhard Schmidt, Daniel Ziener, Jürgen Teich	Minimizing Scrubbing Effort through Automatic Netlist Partitioning and Floorplanning.	IPDPS Workshops	2014	DBLP DOI BibTeX RDF
17	Marco Rabozzi, John Lillis, Marco D. Santambrogio	Floorplanning for Partially-Reconfigurable FPGA Systems via Mixed-Integer Linear Programming.	FCCM	2014	DBLP DOI BibTeX RDF
17	Kan Wang, Sheqin Dong	Post-floorplanning power optimization for MSV-driven application specific NoC design.	ISCAS	2014	DBLP DOI BibTeX RDF
17	Puskar Budhathoki, Andreas Henschel, Ibrahim Abe M. Elfadel	Thermal-driven 3D floorplanning using localized TSV placement.	ICICDT	2014	DBLP DOI BibTeX RDF
17	Zhufei Chu, Yinshui Xia, Lun-Yao Wang	Level shifter planning for timing constrained multi-voltage SoC floorplanning.	ACM Great Lakes Symposium on VLSI	2014	DBLP DOI BibTeX RDF
17	Mohammad A. Ahmed, Malgorzata Chrzanowska-Jeske	Delay and power optimization with TSV-aware 3D floorplanning.	ISQED	2014	DBLP DOI BibTeX RDF
17	Wen-Hao Liu, Min-Sheng Chang, Ting-Chi Wang	Floorplanning and Signal Assignment for Silicon Interposer-based 3D ICs.	DAC	2014	DBLP DOI BibTeX RDF
17	Ignacio Arnaldo, Alfredo Cuesta-Infante, J. Manuel Colmenar, José L. Risco-Martín, José L. Ayala	Boosting the 3D thermal-aware floorplanning problem through a master-worker parallel MOEA.	Concurr. Comput. Pract. Exp.	2013	DBLP DOI BibTeX RDF
17	Wenxu Sheng, Sheqin Dong	Multi-bend bus-driven floorplanning considering fixed-outline constraints.	Integr.	2013	DBLP DOI BibTeX RDF
17	Po-Hsun Wu, Tsung-Yi Ho	Bus-driven floorplanning with thermal consideration.	Integr.	2013	DBLP DOI BibTeX RDF
17	Cha-Ru Li, Wai-Kei Mak, Ting-Chi Wang	Fast Fixed-Outline 3-D IC Floorplanning With TSV Co-Placement.	IEEE Trans. Very Large Scale Integr. Syst.	2013	DBLP DOI BibTeX RDF
17	Wei Zhong, Song Chen 0001, Bo Huang, Takeshi Yoshimura, Satoshi Goto	Floorplanning and Topology Synthesis for Application-Specific Network-on-Chips.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2013	DBLP DOI BibTeX RDF