Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
17 | Atul Prakash 0002, Rajesh Kumar Lal |
Floorplanning for Area Optimization Using Parallel Particle Swarm Optimization and Sequence Pair. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Wirel. Pers. Commun. ![In: Wirel. Pers. Commun. 118(1), pp. 323-342, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
17 | B. Srinivasan, R. Venkatesan 0002 |
Multi-objective optimization for energy and heat-aware VLSI floorplanning using enhanced firefly optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Soft Comput. ![In: Soft Comput. 25(5), pp. 4159-4174, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
17 | Licheng Guo, Yuze Chi, Jie Wang 0022, Jason Lau, Weikang Qiao, Ecenur Ustun, Zhiru Zhang, Jason Cong |
AutoBridge: Coupling Coarse-Grained Floorplanning and Pipelining for High-Frequency HLS Design on Multi-Die FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: FPGA '21: The 2021 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Virtual Event, USA, February 28 - March 2, 2021, pp. 81-92, 2021, ACM, 978-1-4503-8218-2. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
17 | Ganesh Gore, Xifan Tang, Pierre-Emmanuel Gaillardon |
A Scalable and Robust Hierarchical Floorplanning to Enable 24-hour Prototyping for 100k-LUT FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: ISPD '21: International Symposium on Physical Design, Virtual Event, USA, March 22-24, 2021, pp. 135-142, 2021, ACM, 978-1-4503-8300-4. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
17 | Mert Vatansever, Faik Baskaya |
A modified relay-race algorithm for floorplanning in PCB and IC design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Turkish J. Electr. Eng. Comput. Sci. ![In: Turkish J. Electr. Eng. Comput. Sci. 28(2), pp. 679-692, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
17 | Zhipeng Huang 0009, Zhifeng Lin, Ziran Zhu, Jianli Chen |
An Improved Simulated Annealing Algorithm With Excessive Length Penalty for Fixed-Outline Floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 8, pp. 50911-50920, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
17 | Lalin L. Laudis, N. Ramadass |
A Lion's Pride Inspired Algorithm for VLSI Floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 29(1), pp. 2050003:1-2050003:12, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
17 | Song Chen 0001, Jinglei Huang, Xiaodong Xu, Bo Ding, Qi Xu |
Integrated Optimization of Partitioning, Scheduling, and Floorplanning for Partially Dynamically Reconfigurable Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(1), pp. 199-212, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
17 | Pingakshya Goswami, Dinesh Bhatia |
Automated Floorplanning for Partially Reconfigurable Designs on Heterogenrous FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2011.11716, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP BibTeX RDF |
|
17 | Tai-Chen Chen, Pei-Yu Lee, Tung-Chieh Chen |
Automatic Floorplanning for AI SoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-DAT ![In: 2020 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2020, Hsinchu, Taiwan, August 10-13, 2020, pp. 1-2, 2020, IEEE, 978-1-7281-6083-2. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
17 | Tianming Ni, Hao Chang, Shidong Zhu, Lin Lu, Xueyun Li, Qi Xu, Huaguo Liang, Zhengfeng Huang |
Temperature-Aware Floorplanning for Fixed-Outline 3D ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 7, pp. 139787-139794, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
17 | Junyan Tan, Chunhua Cai |
An Efficient Partitioning Algorithm Based on Hypergraph for 3D Network-On-Chip Architecture Floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 28(5), pp. 1950075:1-1950075:19, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
17 | Norbert Deak, Octavian Cret, Horia Hedesiu |
Efficient FPGA Floorplanning for Partial Reconfiguration-Based Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1904.10646, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
|
17 | Norbert Deak, Octavian Cret, Horia Hedesiu |
Efficient FPGA Floorplanning for Partial Reconfiguration-Based Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2019, San Diego, CA, USA, April 28 - May 1, 2019, pp. 309, 2019, IEEE, 978-1-7281-1131-5. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
17 | S. B. Vinay Kumar, P. V. Rao, Manoj Kumar Singh |
Multi-culture diversity based self adaptive particle swarm optimization for optimal floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Multiagent Grid Syst. ![In: Multiagent Grid Syst. 14(1), pp. 31-65, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
17 | Johann Knechtel, Jens Lienig, Ibrahim Abe M. Elfadel |
Multi-Objective 3D Floorplanning with Integrated Voltage Assignment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 23(2), pp. 22:1-22:27, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
17 | Song Chen 0001, Jinglei Huang, Xiaodong Xu, Qi Xu |
Integrated Optimization of Partitioning, Scheduling and Floorplanning for Partially Dynamically Reconfigurable Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1803.03748, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP BibTeX RDF |
|
17 | Subrata Das, Debesh Kumar Das |
Floorplanning in Graphene Nanoribbon (GNR) Based Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2018 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2018, Hong Kong, China, July 8-11, 2018, pp. 293-298, 2018, IEEE Computer Society, 978-1-5386-7099-6. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
17 | Sara Vinco, Lorenzo Bottaccioli, Edoardo Patti, Andrea Acquaviva, Enrico Macii, Massimo Poncino |
GIS-based optimal photovoltaic panel floorplanning for residential installations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2018 Design, Automation & Test in Europe Conference & Exhibition, DATE 2018, Dresden, Germany, March 19-23, 2018, pp. 437-442, 2018, IEEE, 978-3-9819263-0-9. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
17 | Jai-Ming Lin, Chien-Yu Huang |
General floorplanning methodology for 3D ICs with an arbitrary bonding style. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2018 Design, Automation & Test in Europe Conference & Exhibition, DATE 2018, Dresden, Germany, March 19-23, 2018, pp. 1199-1202, 2018, IEEE, 978-3-9819263-0-9. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
17 | Jai-Ming Lin, Chien-Yu Huang, Jhih-Ying Yang |
Co-synthesis of floorplanning and powerplanning in 3D ICs for multiple supply voltage designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2018 Design, Automation & Test in Europe Conference & Exhibition, DATE 2018, Dresden, Germany, March 19-23, 2018, pp. 1339-1344, 2018, IEEE, 978-3-9819263-0-9. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
17 | François Galea, Sergiu Carpov, Lilia Zaourar |
Multi-start simulated annealing for partially-reconfigurable FPGA floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS Workshops ![In: 2018 IEEE International Parallel and Distributed Processing Symposium Workshops, IPDPS Workshops 2018, Vancouver, BC, Canada, May 21-25, 2018, pp. 1335-1338, 2018, IEEE Computer Society, 978-1-5386-5555-9. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
17 | Chao Geng, Shigetoshi Nakatake |
Hierarchical Floorplanning Based on Analog Structure Tree. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NGCAS ![In: 2018 New Generation of CAS, NGCAS 2018, Valletta, Malta, November 20-23, 2018, pp. 138-141, 2018, IEEE, 978-1-5386-7681-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
17 | Jai-Ming Lin, Tai-Ting Chen, Yen-Fu Chang, Wei-Yi Chang, Ya-Ting Shyu, Yeong-Jar Chang, Juin-Ming Lu |
A fast thermal-aware fixed-outline floorplanning methodology based on analytical models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the International Conference on Computer-Aided Design, ICCAD 2018, San Diego, CA, USA, November 05-08, 2018, pp. 1:1-1:8, 2018, ACM, 978-1-4503-5950-4. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
17 | Sara Vinco, Enrico Macii, Massimo Poncino |
Optimal Topology-Aware PV Panel Floorplanning with Hybrid Orientation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 2018 on Great Lakes Symposium on VLSI, GLSVLSI 2018, Chicago, IL, USA, May 23-25, 2018, pp. 491-494, 2018, ACM. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
17 | Francisco Eugenio Potestad-Ordóñez, Carlos Jesús Jiménez-Fernández, Carmen Baena Oliva, Pilar Parra Fernández, Manuel Valencia-Barrero |
Floorplanning as a practical countermeasure against clock fault attack in Trivium stream cipher. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DCIS ![In: Conference on Design of Circuits and Integrated Systems, DCIS 2018, Lyon, France, November 14-16, 2018, pp. 1-6, 2018, IEEE, 978-1-7281-0171-2. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
17 | Piotr Zajac, Melvin Galicia, Andrzej Napieralski |
Thermal-aware Floorplanning Guidelines for 3D ICs with Integrated Microchannels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MIXDES ![In: 25th International Conference `Mixed Design of Integrated Circuits and System`, MIXDES 2018, Gdynia, Poland, June 21-23, 2018, pp. 258-261, 2018, IEEE, 978-83-63578-14-5. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
17 | P. Sivaranjani, A. Senthil Kumar |
Hybrid Particle Swarm Optimization-Firefly algorithm (HPSOFF) for combinatorial optimization of non-slicing VLSI floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Intell. Fuzzy Syst. ![In: J. Intell. Fuzzy Syst. 32(1), pp. 661-669, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
17 | Bernhard Schmidt, Daniel Ziener, Jürgen Teich, Christian Zöllner 0003 |
Optimizing scrubbing by netlist analysis for FPGA configuration bit classification and floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 59, pp. 98-108, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
17 | Behnam Khodabandeloo, Ahmad Khonsari, Masoomeh Jasemi, Golnaz Taheri |
A fast temperature-aware fixed-outline floorplanning framework using convex optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 58, pp. 101-110, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
17 | Qi Xu, Song Chen 0001 |
Fast thermal analysis for fixed-outline 3D floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 59, pp. 157-167, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
17 | Jianli Chen, Yan Liu, Ziran Zhu, Wenxing Zhu |
An adaptive hybrid memetic algorithm for thermal-aware non-slicing VLSI floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 58, pp. 245-252, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
17 | Pengli Ji, Kun He 0001, Yan Jin 0005, Hongsheng Lan, Chumin Li |
An iterative merging algorithm for soft rectangle packing and its extension for application of fixed-outline floorplanning of soft modules. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Oper. Res. ![In: Comput. Oper. Res. 86, pp. 110-123, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
17 | Marco Rabozzi, Gianluca Carlo Durelli, Antonio Miele, John Lillis, Marco Domenico Santambrogio |
Floorplanning Automation for Partial-Reconfigurable FPGAs via Feasible Placements Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 25(1), pp. 151-164, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
17 | Marta Ortín-Obón, Mahdi Tala, Luca Ramini, Víctor Viñals Yúfera, Davide Bertozzi |
Contrasting Laser Power Requirements of Wavelength-Routed Optical NoC Topologies Subject to the Floorplanning, Placement, and Routing Constraints of a 3-D-Stacked System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 25(7), pp. 2081-2094, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
17 | Jai-Ming Lin, Jung-An Yang |
Routability-Driven TSV-Aware Floorplanning Methodology for Fixed-Outline 3-D ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(11), pp. 1856-1868, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
17 | Suchandra Banerjee, Anand Ratna, Suchismita Roy |
Satisfiability Modulo Theory based Methodology for Floorplanning in VLSI Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1709.07241, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP BibTeX RDF |
|
17 | Bernhard Schmidt, Daniel Ziener, Jürgen Teich, Christian Zöllner 0003 |
Optimizing Scrubbing by Netlist Analysis for FPGA Configuration Bit Classification and Floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1707.08134, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP BibTeX RDF |
|
17 | Marco Rabozzi, Giuseppe Natale, Biagio Festa, Antonio Miele, Marco D. Santambrogio |
Optimizing streaming stencil time-step designs via FPGA floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 27th International Conference on Field Programmable Logic and Applications, FPL 2017, Ghent, Belgium, September 4-8, 2017, pp. 1-4, 2017, IEEE, 978-9-0903-0428-1. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
17 | Xiaodong Xu, Qi Xu, Jinglei Huang, Song Chen 0001 |
An Integrated Optimization Framework for Partitioning, Scheduling and Floorplanning on Partially Dynamically Reconfigurable FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the on Great Lakes Symposium on VLSI 2017, Banff, AB, Canada, May 10-12, 2017, pp. 403-406, 2017, ACM, 978-1-4503-4972-7. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
17 | Linquan Lyu, Takeshi Yoshimura |
A force directed partitioning algorithm for 3D floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASICON ![In: 12th IEEE International Conference on ASIC, ASICON 2017, Guiyang, China, October 25-28, 2017, pp. 718-721, 2017, IEEE, 978-1-5090-6625-4. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
17 | Yanling Zhou, Yunyao Yan, Wei Yan |
A method to speed up VLSI hierarchical physical design in floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASICON ![In: 12th IEEE International Conference on ASIC, ASICON 2017, Guiyang, China, October 25-28, 2017, pp. 347-350, 2017, IEEE, 978-1-5090-6625-4. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
17 | Jinyu Wang, Weiguo Wu, Zhaonan Qin, Dongfang Zhao 0005 |
A Floorplanning Algorithm for Partially Reconfigurable FPGA in Wireless Sensor Network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SpaCCS Workshops ![In: Security, Privacy, and Anonymity in Computation, Communication, and Storage - SpaCCS 2017 International Workshops, Guangzhou, China, December 12-15, 2017, Proceedings, pp. 667-679, 2017, Springer, 978-3-319-72394-5. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
17 | De-Xuan Zou, Gaige Wang, Gai Pan, Hongwei Qin |
A modified simulated annealing algorithm and an excessive area model for floorplanning using fixed-outline constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Frontiers Inf. Technol. Electron. Eng. ![In: Frontiers Inf. Technol. Electron. Eng. 17(11), pp. 1228-1244, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
17 | Zhufei Chu, Yinshui Xia, Lun-Yao Wang |
Multi-supply voltage (MSV) driven SoC floorplanning for fast design convergence. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 52, pp. 335-346, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
17 | Zhufei Chu, Yinshui Xia, Lun-Yao Wang, Jian Wang |
Efficient power pad assignment for multi-voltage SoC and its application in floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Circuit Theory Appl. ![In: Int. J. Circuit Theory Appl. 44(8), pp. 1533-1550, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
17 | Piotr Zajac, Melvin Galicia, Cezary Maj, Andrzej Napieralski |
Impact of floorplanning and thermal vias placement on temperature in 2D and 3D processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 52, pp. 40-48, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
17 | Jinglei Huang, Song Chen 0001, Wei Zhong, Wenchao Zhang, Shengxi Diao, Fujiang Lin |
Floorplanning and Topology Synthesis for Application-Specific Network-on-Chips with RF-Interconnect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 21(3), pp. 40:1-40:23, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
17 | Qi Xu, Song Chen 0001, Bin Li 0025 |
Combining the ant system algorithm and simulated annealing for 3D/2D fixed-outline floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Appl. Soft Comput. ![In: Appl. Soft Comput. 40, pp. 150-160, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
17 | Hui Zhu, Cong Hao, Takeshi Yoshimura |
Thermal-aware floorplanning for NoC-sprinting. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MWSCAS ![In: IEEE 59th International Midwest Symposium on Circuits and Systems, MWSCAS 2016, Abu Dhabi, United Arab Emirates, October 16-19, 2016, pp. 1-4, 2016, IEEE, 978-1-5090-0916-9. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
17 | Pingakshya Goswami, Dinesh Bhatia |
Floorplanning of Partially Reconfigurable Design on Heterogeneous FPGA (Abstract Only). ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Monterey, CA, USA, February 21-23, 2016, pp. 275, 2016, ACM, 978-1-4503-3856-1. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
17 | Suchandra Banerjee, Anand Ratna, Suchismita Roy |
Satisfiability modulo theory based methodology for floorplanning in VLSI circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISED ![In: Sixth International Symposium on Embedded Computing and System Design, ISED 2016, Patna, India, December 15-17, 2016, pp. 91-95, 2016, IEEE, 978-1-5090-2541-1. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
17 | Wissem Chouchene, Rabie Ben Atitallah, Jean-Luc Dekeyser |
AFFORDe: Automatic Allocation and Floorplanning for SPMD Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MCSoC ![In: 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, MCSOC 2016, Lyon, France, September 21-23, 2016, pp. 1-7, 2016, IEEE Computer Society, 978-1-5090-3531-1. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
17 | Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal |
A Novel EPE Aware Hybrid Global Route Planner after Floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSID ![In: 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, VLSID 2016, Kolkata, India, January 4-8, 2016, pp. 595-596, 2016, IEEE Computer Society, 978-1-4673-8700-2. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
17 | Artur Quiring |
Routing-driven Multiobjective 3D Floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2016 |
RDF |
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17 | Aminollah Mahabadi, Ahmad Khonsari, Behnam Khodabandeloo, Hamid Noori, Alireza Majidi |
Critical path-aware voltage island partitioning and floorplanning for hard real-time embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 48, pp. 21-35, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
17 | Xiaodao Chen, Lizhe Wang 0001, Albert Y. Zomaya, Lin Liu 0013, Shiyan Hu |
Cloud Computing for VLSI Floorplanning Considering Peak Temperature Reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Emerg. Top. Comput. ![In: IEEE Trans. Emerg. Top. Comput. 3(4), pp. 534-543, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
17 | Dakun Zhang, Guozhi Song, Kunliang Liu, Yong Ma, Chenglong Zhao, Xu An Wang 0001 |
Comprehensive Improved Simulated Annealing Optimization for Floorplanning of Heterogeneous 3D Networks-on-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Interconnect. Networks ![In: J. Interconnect. Networks 15(3-4), pp. 1540006:1-1540006:19, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
17 | P. Sivaranjani, A. Senthil Kumar |
Thermal-Aware Non-slicing VLSI Floorplanning Using a Smart Decision-Making PSO-GA Based Hybrid Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits Syst. Signal Process. ![In: Circuits Syst. Signal Process. 34(11), pp. 3521-3542, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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17 | Andreas Thor Winther, Wei Liu 0016, Alberto Nannarelli, Sarma B. K. Vrudhula |
Thermal aware floorplanning incorporating temperature dependent wire delay estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 39(8), pp. 807-815, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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17 | Alfredo Cuesta-Infante, J. Manuel Colmenar, Zorana Bankovic, José L. Risco-Martín, Marina Zapater, José Ignacio Hidalgo, José Luis Ayala, José Manuel Moya |
Comparative study of meta-heuristic 3D floorplanning algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Neurocomputing ![In: Neurocomputing 150, pp. 67-81, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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17 | Chyi-Shiang Hoo, Kanesan Jeevan, Harikrishnan Ramiah |
Cost reduction in bottom-up hierarchical-based VLSI floorplanning designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Circuit Theory Appl. ![In: Int. J. Circuit Theory Appl. 43(3), pp. 286-306, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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17 | Artur Quiring, Markus Olbrich, Erich Barke |
Fast global interconnnect driven 3D floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015, pp. 313-318, 2015, IEEE, 978-1-4673-9140-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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17 | Ying-Jung Chen, Shanq-Jang Ruan |
A cluster-based reliability- and thermal-aware 3D floorplanning using redundant STSVs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015, pp. 349-354, 2015, IEEE, 978-1-4673-9140-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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17 | Davide Pagano, Mikel Vuka, Marco Rabozzi, Riccardo Cattaneo, Donatella Sciuto, Marco D. Santambrogio |
Thermal-aware floorplanning for partially-reconfigurable FPGA-based systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, DATE 2015, Grenoble, France, March 9-13, 2015, pp. 920-923, 2015, ACM, 978-3-9815370-4-8. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP BibTeX RDF |
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17 | Marco Rabozzi, Riccardo Cattaneo, Tobias Becker, Wayne Luk, Marco D. Santambrogio |
Relocation-Aware Floorplanning for Partially-Reconfigurable FPGA-Based Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS Workshops ![In: 2015 IEEE International Parallel and Distributed Processing Symposium Workshop, IPDPS 2015, Hyderabad, India, May 25-29, 2015, pp. 97-104, 2015, IEEE Computer Society, 978-1-4673-7684-6. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
17 | Marco Rabozzi, Antonio Miele, Marco D. Santambrogio |
Floorplanning for Partially-Reconfigurable FPGAs via Feasible Placements Detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2015, Vancouver, BC, Canada, May 2-6, 2015, pp. 252-255, 2015, IEEE Computer Society, 978-1-4799-9969-9. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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17 | Kevin E. Murray, Vaughn Betz |
HETRIS: Adaptive floorplanning for heterogeneous FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPT ![In: 2015 International Conference on Field Programmable Technology, FPT 2015, Queenstown, New Zealand, December 7-9, 2015, pp. 88-95, 2015, IEEE, 978-1-4673-9091-0. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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17 | Mohammad A. Ahmed, Sucheta Mohapatra, Malgorzata Chrzanowska-Jeske |
Dynamic nets-to-TSVs assignment in 3D floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015, Lisbon, Portugal, May 24-27, 2015, pp. 1870-1873, 2015, IEEE, 978-1-4799-8391-9. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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17 | David Guilherme, João Pereira, Nuno Horta, Jorge Guilherme |
Thermal-aware floorplanning and layout generation of MOSFET power stages. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015, Lisbon, Portugal, May 24-27, 2015, pp. 2269-2272, 2015, IEEE, 978-1-4799-8391-9. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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17 | Boris Vaisband, Eby G. Friedman |
3-D floorplanning algorithm to minimize thermal interactions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015, Lisbon, Portugal, May 24-27, 2015, pp. 2133-2136, 2015, IEEE, 978-1-4799-8391-9. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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17 | Shengcheng Wang, Farshad Firouzi, Fabian Oboril, Mehdi Baradaran Tahoori |
Deadspace-aware Power/Ground TSV planning in 3D floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICICDT ![In: 2015 International Conference on IC Design & Technology, ICICDT 2015, Leuven, Belgium, June 1-3, 2015, pp. 1-4, 2015, IEEE, 978-1-4799-7669-0. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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17 | Jai-Ming Lin, Chih-Yao Hu, Kai-Chung Chan |
Routability-driven floorplanning algorithm for mixed-size modules with fixed-outline constraint. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-DAT ![In: VLSI Design, Automation and Test, VLSI-DAT 2015, Hsinchu, Taiwan, April 27-29, 2015, pp. 1-4, 2015, IEEE, 978-1-4799-6275-4. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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17 | Xi Chen, Jiang Hu, Ning Xu 0006 |
Regularity-constrained floorplanning for multi-core processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 47(1), pp. 86-95, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
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17 | Chyi-Shiang Hoo, Kanesan Jeevan, Harikrishnan Ramiah |
Enumeration technique in very large-scale integration fixed-outline floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Circuits Devices Syst. ![In: IET Circuits Devices Syst. 8(1), pp. 47-57, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
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17 | Cheoljon Jang, Jaehwan Kim, Jong-Wha Chong |
Power-aware floorplanning-based power throughsilicon- via technology and bump minimisation for three-dimensional power delivery network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Comput. Digit. Tech. ![In: IET Comput. Digit. Tech. 8(5), pp. 210-218, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
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17 | Lin Wang |
Fast Algorithms for thermal-Aware floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 23(7), 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
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17 | Jai-Ming Lin, Ji-Heng Wu |
F-FM: Fixed-Outline Floorplanning Methodology for Mixed-Size Modules Considering Voltage-Island Constraint. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(11), pp. 1681-1692, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
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17 | Zhufei Chu, Yinshui Xia, Lun-Yao Wang, Jian Wang |
Efficient nonrectangular shaped voltage island aware floorplanning with nonrandomized searching engine. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 45(4), pp. 382-393, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
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17 | Bei Yu 0001, Sheqin Dong, Song Chen 0001, Satoshi Goto |
Floorplanning and Topology Generation for Application-Specific Network-on-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1402.2462, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP BibTeX RDF |
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17 | Kun He 0001, Pengli Ji, Chumin Li |
An iterative merging placement algorithm for the fixed-outline floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1401.3172, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP BibTeX RDF |
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17 | Bei Yu 0001, Sheqin Dong, Satoshi Goto |
Multi-Voltage and Level-Shifter Assignment Driven Floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1402.2894, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP BibTeX RDF |
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17 | Bei Yu 0001, Sheqin Dong, Song Chen 0001, Satoshi Goto |
Voltage and Level-Shifter Assignment Driven Floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1402.3149, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP BibTeX RDF |
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17 | Sung Kyu Lim |
Research Needs for TSV-Based 3D IC Architectural Floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Inform. and Commun. Convergence Engineering ![In: J. Inform. and Commun. Convergence Engineering 12(1), pp. 46-52, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
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17 | Yang Xu 0019, Bo Wang 0010, Jürgen Teich |
Parametric yield optimization using leakage-yield-driven floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: 24th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS), Palma de Mallorca, Spain, September 29 - Oct. 1, 2014, pp. 1-6, 2014, IEEE. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
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17 | Bernhard Schmidt, Daniel Ziener, Jürgen Teich |
An automatic netlist and floorplanning approach to improve the MTTR of scrubbing techniques (abstract only). ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: The 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA '14, Monterey, CA, USA - February 26 - 28, 2014, pp. 257, 2014, ACM, 978-1-4503-2671-1. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
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17 | Indira Rawat, M. K. Gupta, Virendra Singh |
Temperature aware test scheduling by modified floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EWDTS ![In: 2014 East-West Design & Test Symposium, EWDTS 2014, Kiev, Ukraine, September 26-29, 2014, pp. 1-4, 2014, IEEE Computer Society, 978-1-4799-7630-0. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
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17 | Mohammad A. Ahmed, Sucheta Mohapatra, Malgorzata Chrzanowska-Jeske |
3D floorplanning with nets-to-TSVs assignment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 21st IEEE International Conference on Electronics, Circuits and Systems, ICECS 2014, Marseille, France, December 7-10, 2014, pp. 578-581, 2014, IEEE, 978-1-4799-4242-8. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
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17 | Bernhard Schmidt, Daniel Ziener, Jürgen Teich |
Minimizing Scrubbing Effort through Automatic Netlist Partitioning and Floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS Workshops ![In: 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, Phoenix, AZ, USA, May 19-23, 2014, pp. 299-304, 2014, IEEE Computer Society, 978-0-7695-5208-8. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
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17 | Marco Rabozzi, John Lillis, Marco D. Santambrogio |
Floorplanning for Partially-Reconfigurable FPGA Systems via Mixed-Integer Linear Programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2014, Boston, MA, USA, May 11-13, 2014, pp. 186-193, 2014, IEEE Computer Society, 978-1-4799-5110-9. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
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17 | Kan Wang, Sheqin Dong |
Post-floorplanning power optimization for MSV-driven application specific NoC design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systemss, ISCAS 2014, Melbourne, Victoria, Australia, June 1-5, 2014, pp. 994-997, 2014, IEEE, 978-1-4799-3431-7. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
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17 | Puskar Budhathoki, Andreas Henschel, Ibrahim Abe M. Elfadel |
Thermal-driven 3D floorplanning using localized TSV placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICICDT ![In: 2014 IEEE International Conference on IC Design & Technology, ICICDT 2014, Austin, TX, USA, May 28-30, 2014, pp. 1-4, 2014, IEEE, 978-1-4799-2153-9. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
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17 | Zhufei Chu, Yinshui Xia, Lun-Yao Wang |
Level shifter planning for timing constrained multi-voltage SoC floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21 - 23, 2014, pp. 329-334, 2014, ACM, 978-1-4503-2816-6. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
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17 | Mohammad A. Ahmed, Malgorzata Chrzanowska-Jeske |
Delay and power optimization with TSV-aware 3D floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: Fifteenth International Symposium on Quality Electronic Design, ISQED 2014, Santa Clara, CA, USA, March 3-5, 2014, pp. 189-196, 2014, IEEE, 978-1-4799-3945-9. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
17 | Wen-Hao Liu, Min-Sheng Chang, Ting-Chi Wang |
Floorplanning and Signal Assignment for Silicon Interposer-based 3D ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: The 51st Annual Design Automation Conference 2014, DAC '14, San Francisco, CA, USA, June 1-5, 2014, pp. 5:1-5:6, 2014, ACM, 978-1-4503-2730-5. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
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17 | Ignacio Arnaldo, Alfredo Cuesta-Infante, J. Manuel Colmenar, José L. Risco-Martín, José L. Ayala |
Boosting the 3D thermal-aware floorplanning problem through a master-worker parallel MOEA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Concurr. Comput. Pract. Exp. ![In: Concurr. Comput. Pract. Exp. 25(8), pp. 1089-1103, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
17 | Wenxu Sheng, Sheqin Dong |
Multi-bend bus-driven floorplanning considering fixed-outline constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 46(2), pp. 142-152, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
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17 | Po-Hsun Wu, Tsung-Yi Ho |
Bus-driven floorplanning with thermal consideration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 46(4), pp. 369-381, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
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17 | Cha-Ru Li, Wai-Kei Mak, Ting-Chi Wang |
Fast Fixed-Outline 3-D IC Floorplanning With TSV Co-Placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 21(3), pp. 523-532, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
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17 | Wei Zhong, Song Chen 0001, Bo Huang, Takeshi Yoshimura, Satoshi Goto |
Floorplanning and Topology Synthesis for Application-Specific Network-on-Chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(6), pp. 1174-1184, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|