Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
20 | Takuya Kaizawa, Mingyu Jo, Masashi Arita, Akira Fujiwara, Kenji Yamazaki, Yukinori Ono, Hiroshi Inokawa, Yasuo Takahashi |
Full Adder Operation Based on Si Nanodot Array Device with Multiple Inputs and Outputs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Nanotechnol. Mol. Comput. ![In: Int. J. Nanotechnol. Mol. Comput. 1(2), pp. 58-69, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
20 | Keivan Navi, Amir Momeni, Fazel Sharifi, Peiman Keshavarzian |
Two novel ultra high speed carbon nanotube Full-Adder cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 6(19), pp. 1395-1401, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
20 | Mehrdad Maeen, Vahid Foroutan, Keivan Navi |
On the design of low power 1-bit full adder cell. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 6(16), pp. 1148-1154, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
20 | Keivan Navi, Mehrdad Maeen, Omid Hashemipour |
An energy efficient full adder cell for low voltage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 6(9), pp. 553-559, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
20 | Anindya Ghosh, Debapriyo Ghosh |
Optimization of Static Power, Leakage Power and Delay of Full Adder Circuit Using Dual Threshold MOSFET Based Design and T-Spice Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARTCom ![In: ARTCom 2009, International Conference on Advances in Recent Technologies in Communication and Computing, Kottayam, Kerala, India, 27-28 October 2009, pp. 903-905, 2009, IEEE Computer Society, 978-0-7695-3845-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
20 | Farshad Moradi, Dag T. Wisland, Hamid Mahmoodi, Snorre Aunet, Tuan Vu Cao, Ali Peiravi |
Ultra Low Power Full Adder Topologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2009), 24-17 May 2009, Taipei, Taiwan, pp. 3158-3161, 2009, IEEE, 978-1-4244-3827-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
20 | Katsumi Wasaki |
Stability of n-Bit Generalized Full Adder Circuits (GFAs). Part II. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Formaliz. Math. ![In: Formaliz. Math. 16(1-4), pp. 73-80, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
20 | Minas Dasygenis, K. Mitroglou, Dimitrios Soudris, Adonios Thanailakis |
A Full-Adder-Based Methodology for the Design of Scaling Operation in Residue Number System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(2), pp. 546-558, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
20 | Keivan Navi, Omid Kavehei, Mahnoush Rouholamini, Amir Sahafi, Shima Mehrabi, Nooshin Dadkhahi |
Low-Power and High-Performance 1-Bit CMOS Full-Adder Cell. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comput. ![In: J. Comput. 3(2), pp. 48-54, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP BibTeX RDF |
|
20 | Omid Kavehei, Mostafa Rahimi Azghadi, Keivan Navi, Amir-Pasha Mirbaha |
Design of Robust and High-Performance 1-Bit CMOS Full Adder for Nanometer Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2008, 7-9 April 2008, Montpellier, France, pp. 10-15, 2008, IEEE Computer Society, 978-0-7695-3170-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
20 | Gian Carlo Cardarilli, Luca Di Nunzio, Marco Re |
A full-adder based reconfigurable architecture for fine grain applications: ADAPTO. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008, St. Julien's, Malta, August 31 2008-September 3, 2008, pp. 1304-1307, 2008, IEEE, 978-1-4244-2181-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
20 | Deepchand Patel, Pravinkumar G. Parate, Prafulla S. Patil, S. Subbaraman |
ASIC Implimentation of 1 Bit Full Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICETET ![In: First International Conference on Emerging Trends in Engineering and Technology, ICETET '08, Nagpur, Maharashtra, India, July 16-18, 2008, pp. 463-467, 2008, IEEE Computer Society, 978-0-7695-3267-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
20 | Gian Carlo Cardarilli, Luca Di Nunzio, Marco Re, Alberto Nannarelli |
ADAPTO: full-adder based reconfigurable architecture for bit level operations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 3434-3437, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
20 | Takao Waho, Hiroki Okuyama, Tomohiko Ebata, Ryousuke Kato |
An ultrahigh-speed full adder using resonant-tunneling logic gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2008, Macao, China, November 30 2008 - December 3, 2008, pp. 1724-1727, 2008, IEEE, 978-1-4244-2342-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
20 | Pradeep S. Nair, Savithra Eratne, Eugene John |
Topology-related effects of Gated-Vdd and Gated-Vss techniques on full-adder leakage and delay at 65nm and 45 nm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2008, Macao, China, November 30 2008 - December 3, 2008, pp. 972-975, 2008, IEEE, 978-1-4244-2342-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
20 | Massimo Alioto, Giuseppe Di Cataldo, Gaetano Palumbo |
Mixed Full Adder topologies for high-performance low-power arithmetic circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 38(1), pp. 130-139, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
20 | Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu, Cheng-Che Ho |
A Novel High-Speed and Energy Efficient 10-Transistor Full Adder Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 54-I(5), pp. 1050-1059, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
20 | Chiou-Kou Tung, Yu-Cherng Hung, Shao-Hui Shieh, Guo-Shing Huang |
A Low-Power High-Speed Hybrid CMOS Full Adder for Embedded System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), Kraków, Poland, April 11-13, 2007, pp. 199-202, 2007, IEEE Computer Society, 1-4244-1161-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
20 | Keivan Navi, Omid Kavehei, Mahnoush Rouholamini, Amir Sahafi, Shima Mehrabi |
A Novel CMOS Full Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India, pp. 303-307, 2007, IEEE Computer Society, 0-7695-2762-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
20 | Kristian Granhaug, Snorre Aunet |
Six Subthreshold Full Adder Cells Characterized in 90 nm CMOS Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), Prague, Czech Republic, April 18-21, 2006, pp. 27-32, 2006, IEEE Computer Society, 1-4244-0185-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
20 | Yvan Van Rentergem, Alexis De Vos |
Optimal Design of a Reversible Full Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Unconv. Comput. ![In: Int. J. Unconv. Comput. 1(4), pp. 339-355, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP BibTeX RDF |
|
20 | Konstantinos Anagnostopoulos, George Economakos |
Lowpower design of multipliers using a full-adder isolation technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 12th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2005, Gammarth, Tunisia, December 11-14, 2005, pp. 1-4, 2005, IEEE, 978-9972-61-100-1. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
20 | Yingtao Jiang, Abdulkarim Al-Sheraidah, Yuke Wang, Edwin Hsing-Mean Sha, Jin-Gyun Chung |
A novel multiplexer-based low-power full adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 51-II(7), pp. 345-348, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
20 | Elizabeth J. Brauer, Yusuf Leblebici |
Sub-70 PS full adder IN 0.18 µm CMOS current-mode logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits, Signals, and Systems ![In: Proceedings of the Second IASTED International Conference on Circuits, Signals, and Systems, Clearwater Beach, FL, USA, November 28, 2004 - December 1, 2004, pp. 483-487, 2004, IASTED/ACTA Press. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP BibTeX RDF |
|
20 | Adrian Burian, Jarmo Takala |
VLSI-efficient implementation of full adder-based median filter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: Proceedings of the 2004 International Symposium on Circuits and Systems, ISCAS 2004, Vancouver, BC, Canada, May 23-26, 2004, pp. 817-820, 2004, IEEE, 0-7803-8251-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP BibTeX RDF |
|
20 | Ahmed Sayed, Hussain Al-Asaad |
Survey and Evaluation of Low-Power Full-Adder Cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESA/VLSI ![In: Proceedings of the International Conference on Embedded Systems and Applications, ESA '04 & Proceedings of the International Conference on VLSI, VLSI '04, June 21-24, 2004, Las Vegas, Nevada, USA, pp. 332-338, 2004, CSREA Press, 1-932415-41-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP BibTeX RDF |
|
20 | Massimo Alioto, Gaetano Palumbo |
Analysis and comparison on full adder block in submicron technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 10(6), pp. 806-823, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
20 | Casper Lageweg, Sorin Cotofana, Stamatis Vassiliadis |
A full adder implementation using SET based linear threshold gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: Proceedings of the 2002 9th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2002, Dubrovnik, Croatia, September 15-18, 2002, pp. 665-668, 2002, IEEE, 0-7803-7596-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
20 | Dimitrios Soudris, Minas Dasygenis, K. Mitroglou, Konstantinos Tatas, Adonios Thanailakis |
A full adder based methodology for scaling operation in residue number system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: Proceedings of the 2002 9th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2002, Dubrovnik, Croatia, September 15-18, 2002, pp. 891-894, 2002, IEEE, 0-7803-7596-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
20 | Yngvar Berg, Snorre Aunet, Øivind Næss, O. Hagen, Mats Høvin |
A novel floating-gate multiple-valued CMOS full-adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 877-880, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
20 | Alejandro F. González, Mayukh Bhattacharya, Shriram Kulkarni, Pinaki Mazumder |
CMOS implementation of a multiple-valued logic signed-digit full adder based on negative-differentiaI-resistance devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 36(6), pp. 924-932, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
20 | Abdulkarim Al-Sheraidah, Bassem Alhalabi, Hung Tien Bui |
Five new high-performance multiplexer-based 1-bit full adder cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: Proceedings of the 2001 8th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2001, Malta, September 2-5, 2001, pp. 807-810, 2001, IEEE, 0-7803-7057-0. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
20 | José M. Quintana, Maria J. Avedillo, Raúl Jiménez, Esther Rodríguez-Villegas |
Low-power logic styles for full-adder circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: Proceedings of the 2001 8th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2001, Malta, September 2-5, 2001, pp. 1417-1420, 2001, IEEE, 0-7803-7057-0. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
20 | Bassem Alhalabi, Abdulkarim Al-Sheraidah |
A novel low power multiplexer-based full adder cell. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: Proceedings of the 2001 8th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2001, Malta, September 2-5, 2001, pp. 1433-1436, 2001, IEEE, 0-7803-7057-0. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
20 | D. J. Soudris, Minas Dasygenis, Adonios Thanailakis |
Designing RNS and QRNS full adder based converters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2000, Emerging Technologies for the 21st Century, Geneva, Switzerland, 28-31 May 2000, Proceedings, pp. 20-23, 2000, IEEE. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
20 | Ahmed M. Shams, Magdy A. Bayoumi |
A New Full Adder Cell for Low-Power Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 19-21 February 1998, Lafayette, LA, USA, pp. 45-, 1998, IEEE Computer Society, 0-8186-8409-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
20 | Shyh-Jye Jou, Chang-Yu Chen, En-Chung Yang, Chau-Chin Su |
A pipelined multiplier-accumulator using a high-speed, low-power static and dynamic full adder design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 32(1), pp. 114-118, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
20 | A. Srivastava, K. Venkatapathy |
Design and Implementation of a Low Power Ternary Full Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 4(1), pp. 75-81, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
20 | Dimitrios Soudris, Vassilis Paliouras, Thanos Stouraitis, Alexander Skavantzos, Constantinos E. Goutis |
Systematic design of full adder-based architectures for convolution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICASSP (1) ![In: IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP '93, Minneapolis, Minnesota, USA, April 27-30, 1993, pp. 389-392, 1993, IEEE Computer Society, 0-7803-7402-9. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
20 | Seon Wook Kim, Thanos Stouraitis, Alexander Skavantzos |
Full Adder-based Inner Product Step Processors for Residue and Quadratic Residue Number Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 1993 IEEE International Symposium on Circuits and Systems, ISCAS 1993, Chicago, Illinois, USA, May 3-6, 1993, pp. 1821-1824, 1993, IEEE, 0-7803-1281-3. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP BibTeX RDF |
|
20 | K. Wayne Current |
A CMOS Quaternary Threshold Logic Full Adder Circuit with Transparent Latch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: Proceedings of the 20th International Symposium on Multiple-Valued Logic, ISMVL 1990, Charlotte, NC, USA, May 23-25, 1990, pp. 168-173, 1990, IEEE Computer Society, 0-8186-2046-3. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
20 | Kazuo Iwano, Kenneth Steiglitz |
Time-power-area tradeoffs for the nMOS VLSI full-adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICASSP ![In: IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP '85, Tampa, Florida, USA, March 26-29, 1985, pp. 1453-1456, 1985, IEEE. The full citation details ...](Pics/full.jpeg) |
1985 |
DBLP DOI BibTeX RDF |
|
20 | K. Wayne Current, Douglas A. Mow |
Four-valued threshold logic full adder circuit implementations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MVL ![In: Proceedings of the eighth international symposium on Multiple-valued logic, MVL 1978, Rosemont, Illinois, USA, 1978, pp. 95-100, 1978, IEEE Computer Society Press. The full citation details ...](Pics/full.jpeg) |
1978 |
DBLP BibTeX RDF |
|
20 | Donald W. Davies |
An 11-Cryotron Full Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Electron. Comput. ![In: IEEE Trans. Electron. Comput. 12(3), pp. 319, 1963. The full citation details ...](Pics/full.jpeg) |
1963 |
DBLP DOI BibTeX RDF |
|
20 | Jon S. Squire |
An 11-Cryotron Full Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IRE Trans. Electron. Comput. ![In: IRE Trans. Electron. Comput. 11(5), pp. 710-711, 1962. The full citation details ...](Pics/full.jpeg) |
1962 |
DBLP DOI BibTeX RDF |
|
19 | Sundeepkumar Agarwal, Pavankumar V. K., Yokesh R. |
Energy-Efficient, High Performance Circuits for Arithmetic Units. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 21st International Conference on VLSI Design (VLSI Design 2008), 4-8 January 2008, Hyderabad, India, pp. 371-376, 2008, IEEE Computer Society, 0-7695-3083-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
19 | William N. N. Hung, Xiaoyu Song, Guowu Yang, Jin Yang 0006, Marek A. Perkowski |
Optimal synthesis of multiple output Boolean functions using a set of quantum gates by symbolic reachability analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(9), pp. 1652-1663, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Petros Oikonomakos, Paul Fox |
Error Correction in Arithmetic Operations by I/O Inversion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 10-12 July 2006, Como, Italy, pp. 287-292, 2006, IEEE Computer Society, 0-7695-2620-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | A. Prasad Vinod 0001, Edmund Ming-Kit Lai |
Optimizing vertical common subexpression elimination using coefficient partitioning for designing low complexity software radio channelizers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (6) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 5429-5432, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | E. Islas Pérez, Carlos A. Coello Coello, Arturo Hernández Aguirre, Alejandro Villavicencio Ramírez |
Genetic Algorithms and Case-Based Reasoning as a Discovery and Learning Machine in the Optimization of Combinational Logic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICAI ![In: MICAI 2002: Advances in Artificial Intelligence, Second Mexican International Conference on Artificial Intelligence, Merida, Yucatan, Mexico, April 22-26, 2002, Proceedings, pp. 128-137, 2002, Springer, 3-540-43475-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
19 | Hong-Yi Huang, Teng-Neng Wang |
High-speed CMOS logic circuits in capacitor coupling technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 634-637, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
19 | Christian Pacha, Peter Glösekötter, Karl Goser, Uwe Auer, Werner Prost, Franz-Josef Tegude |
Resonant Tunneling Transistors for Threshold Logic Circuit Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 4-6 March 1999, Ann Arbor, MI, USA, pp. 344-345, 1999, IEEE Computer Society, 0-7695-0104-4. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
16 | Hirokatsu Shirahama, Takahiro Hanyu |
Design of High-Performance Quaternary Adders Based on Output-Generator Sharing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 22-23 May 2008, Dallas, Texas, USA, pp. 8-13, 2008, IEEE Computer Society, 978-0-7695-3155-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Carry pre-addition, Differential-pair circuitry, Voltage-mode circuit, Transfer-gate circuitry, Current-mode circuit |
16 | Zine Abid, Wei Wang 0003 |
New designs of Redundant-Binary full Adders and its applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 3366-3369, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
13 | Cecília Reis, José António Tenreiro Machado, José Boaventura Cunha, Eduardo José Solteiro Pires |
Evolutionary computation in the design of logic circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SMC ![In: Proceedings of the IEEE International Conference on Systems, Man and Cybernetics, Montréal, Canada, 7-10 October 2007, pp. 1664-1669, 2007, IEEE, 978-1-4244-0990-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
13 | Massimo Alioto, Gaetano Palumbo |
Delay Variability Due to Supply Variations in Transmission-Gate Full Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 3732-3735, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
13 | A. Prasad Vinod 0001, Ankita Singla, Chip-Hong Chang |
Improved differential coefficients-based low power FIR filters. Part I. Fundamentals. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
13 | A. Prasad Vinod 0001, Chip-Hong Chang, Pramod Kumar Meher, Ankita Singla |
Low Power FIR Filter Realization using Minimal Difference Coefficients: Part I - Complexity Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 1547-1550, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
13 | Xingjun Wu, Hongyi Chen, Yihe Sun, Weixin Gai |
A Fully-Pipeline Linear Systolic Architecture for Modular Multiplier in Public-Key Crypto-Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 33(1-2), pp. 191-197, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
public-key crypto-system, systolic array, modular-multiplication, pipeline architecture, modular-exponentiation |
13 | Miguel Garvie, Adrian Thompson |
Evolution of Combinatonial and Sequential On-Line Self-Diagnosing Hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Evolvable Hardware ![In: 5th NASA / DoD Workshop on Evolvable Hardware (EH 2003), 9-11 July 2002, Chicago, IL, USA, pp. 177-183, 2003, IEEE Computer Society, 0-7695-1977-6. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
13 | Kiamal Z. Pekmestzi, Nikos K. Moshopoulos |
A Systolic, High Speed Architecture for an RSA Cryptosystem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 32(3), pp. 223-235, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Montgomery algorithm, modular squaring, RSA, public key cryptography, modular multiplication |
13 | Christian Lütkemeyer |
An Optimized Coefficient Update Processor for High-Throughput Adaptive Equalizers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 1997 International Conference on Application-Specific Systems, Architectures, and Processors (ASAP '97), 14-16 July 1997, Zurich, Switzerland, pp. 519-528, 1997, IEEE Computer Society, 0-8186-7958-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
11 | Flavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner |
Transmission Gates Combined With Level-Restoring CMOS Gates Reduce Glitches in Low-Power Low-Frequency Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(7), pp. 830-836, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
11 | Alex Piñeiro, Javier D. Bruguera, Fabrizio Lamberti, Paolo Montuschi |
A Radix-2 Digit-by-Digit Architecture for Cube Root. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 57(4), pp. 562-566, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Cost/performance, High-Speed Arithmetic |
11 | Håvard Pedersen Alstad, Snorre Aunet |
Improving Circuit Security against Power Analysis Attacks with Subthreshold Operation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), Bratislava, Slovakia, April 16-18, 2008, pp. 12-13, 2008, IEEE Computer Society, 978-1-4244-2276-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
11 | Manoj Singh Gaur, Raghavendra Narasimhan, Vijay Laxmi, Ujjwal Kumar |
Structural Fault Modelling in Nano Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NanoNet ![In: Nano-Net - Third International ICST Conference, NanoNet 2008, Boston, MA, USA, September 14-16, 2008, Revised Selected Papers, pp. 6-10, 2008, Springer, 978-3-642-02426-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Structural fault, stuck-at-0, stuck-at-1, MRF, bridge, TMR |
11 | Nobuaki Okada, Michitaka Kameyama |
Fine-Grain Multiple-Valued Reconfigurable VLSI Using Universal-Literal-Based Cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 22-23 May 2008, Dallas, Texas, USA, pp. 180-185, 2008, IEEE Computer Society, 978-0-7695-3155-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Field-programmable VLSI, Multiple-valued source-coupled logic, Differential-Pair circuit, Bit-serial architecture |
11 | Snorre Aunet, Hans Kristian Otnes Berge |
Statistical Simulations for Exploring Defect Tolerance and Power Consumption for 4 Subthreshold 1-Bit Addition Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWANN ![In: Computational and Ambient Intelligence, 9th International Work-Conference on Artificial Neural Networks, IWANN 2007, San Sebastián, Spain, June 20-22, 2007, Proceedings, pp. 455-462, 2007, Springer, 978-3-540-73006-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
11 | Junchen Liu, Ian O'Connor, David Navarro, Frédéric Gaffiot |
Design of a Novel CNTFET-based Reconfigurable Logic Gate. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), May 9-11, 2007, Porto Alegre, Brazil, pp. 285-290, 2007, IEEE Computer Society, 0-7695-2896-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
11 | Elhadj Benkhelifa, Anthony G. Pipe, Gabriel Dragffy, Mokhtar Nibouche |
Towards evolving fault tolerant biologically inspired hardware using evolutionary algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Congress on Evolutionary Computation ![In: Proceedings of the IEEE Congress on Evolutionary Computation, CEC 2007, 25-28 September 2007, Singapore, pp. 1548-1554, 2007, IEEE, 978-1-4244-1339-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
11 | Junchen Liu, Ian O'Connor, David Navarro, Frédéric Gaffiot |
Novel CNTFET-based Reconfigurable Logic Gate Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007, pp. 276-277, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
11 | Koichi Itoh, Masashi Yamazaki, Shinji Nakamura, Yasuo Nagazumi |
An Attempt Towards Charge-Domain Logic (CDL). ![Search on Bibsonomy](Pics/bibsonomy.png) |
CISS ![In: Proceedings of the 41st Annual Conference on Information Sciences and Systems, CISS 2007, 14-16 March 2007, Johns Hopkins University, Department of Electrical Engineering, Baltimore, MD, USA, pp. 732-736, 2007, IEEE, 1-4244-1037-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
11 | Ricardo C. Goncalves da Silva, Henri Boudinov, Luigi Carro |
A cell library for low power high performance CMOS voltage-mode quaternary logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2006, Ouro Preto, MG, Brazil, August 28 - September 1, 2006, pp. 167-172, 2006, ACM. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
quaternary logic design, voltage-mode, multi-valued logic |
11 | Akira Mochizuki, Takahiro Hanyu |
Highly reliable Multiple-Valued Circuit Based on Dual-Rail Differential Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 36th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2006), 17-20 May 2006, Singapore, pp. 5, 2006, IEEE Computer Society, 0-7695-2532-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
11 | Omer Can Akgun, Yusuf Leblebici |
Weak inversion performance of CMOS and DCVSPG logic families in sub-300 mV range. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
11 | Rui Liu, Sanyou Zeng, Lixin Ding, Lishan Kang, Hui Li, Yuping Chen, Yong Liu 0012, Yueping Han |
An Efficient Multi-Objective Evolutionary Algorithm for Combinational Circuit Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AHS ![In: First NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2006), 15-18 June 2006, Istanbul, Turkey, pp. 215-221, 2006, IEEE Computer Society, 0-7695-2614-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Gartesian Genetic Programming, Multiobjective Evolutionary Algorithm, Combinational logic Circuit |
11 | Robert Ross, Richard Hall |
A FPGA Simulation Using Asexual Genetic Algorithms for Integrated Self-Repair. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AHS ![In: First NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2006), 15-18 June 2006, Istanbul, Turkey, pp. 301-304, 2006, IEEE Computer Society, 0-7695-2614-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
11 | Sandeep B. Singh, Jayanta Biswas, S. K. Nandy 0001 |
A Cost Effective Pipelined Divider for Double Precision Floating Point Number. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 2006 IEEE International Conference on Application-Specific Systems, Architecture and Processors (ASAP 2006), 11-13 September 2006, Steamboat Springs, Colorado, USA, pp. 132-137, 2006, IEEE Computer Society, 0-7695-2682-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
11 | Yanjie Mao, Chunhong Chen |
Performance Evaluation and Optimization of Full Adders with Single-Electron Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCECE ![In: Proceedings of the Canadian Conference on Electrical and Computer Engineering, CCECE 2006, May 7-10, 2006, Ottawa Congress Centre, Ottawa, Canada, pp. 2136-2139, 2006, IEEE, 1-4244-0038-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
11 | Yi Wang 0016, Douglas L. Maskell, Jussipekka Leiwo, Thambipillai Srikanthan |
Unified Signed-Digit Number Adder for RSA and ECC Public-key Cryptosystems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 1655-1658, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
11 | A. Prasad Vinod 0001, Chip-Hong Chang, Pramod Kumar Meher, Ankita Singla |
Low Power FIR Filter Realization Using Minimal Difference Coefficients: Part II - Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 1551-1554, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
11 | Samir Roy, Biswajit Saha |
Minority Gate Oriented Logic Design with Quantum-Dot Cellular Automata. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACRI ![In: Cellular Automata, 7th International Conference on Cellular Automata, for Research and Industry, ACRI 2006, Perpignan, France, September 20-23, 2006, Proceedings, pp. 646-656, 2006, Springer, 3-540-40929-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Nano-computing, Minority Gate, Quantum-dot Cellular Automata |
11 | N. Huot, H. Dubreuil, Laurent Fesquet, Marc Renaudin |
FPGA Architecture for Multi-Style Asynchronous Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany, pp. 32-33, 2005, IEEE Computer Society, 0-7695-2288-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
11 | Jae-Jin Lee, Gi-Yong Song |
Design of an application-specific PLD architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 1244-1247, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
11 | Guoqiang Hang |
Adiabatic CMOS gate and adiabatic circuit design for low-power applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 803-808, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
11 | Ulya R. Karpuzcu |
Automatic verilog code generation through grammatical evolution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GECCO Workshops ![In: Genetic and Evolutionary Computation Conference, GECCO 2005, Workshop Proceedings, Washington DC, USA, June 25-26, 2005, pp. 394-397, 2005, ACM. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
automatic code generation, grammatical evolution, verilog |
11 | Hideki Fukuda |
Signed-digit CMOS (SD-CMOS) Logic Circuits with Dynamic Operation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 35th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2005), 18-21 May 2005, Calgary, Canada, pp. 144-151, 2005, IEEE Computer Society, 0-7695-2336-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
11 | Rui Tang, Fengming Zhang, Yong-Bin Kim |
QCA-based nano circuits design [adder design example]. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 2527-2530, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
11 | Julio Villalba, Javier Hormigo, Jose M. Prades, Emilio L. Zapata |
On-line Multioperand Addition Based on On-line Full Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 16th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2005), 23-25 July 2005, Samos, Greece, pp. 322-327, 2005, IEEE Computer Society, 0-7695-2407-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
11 | Rui Tang, Fengming Zhang, Yong-Bin Kim |
Quantum-dot cellular automata SPICE macro model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005, pp. 108-111, 2005, ACM, 1-59593-057-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
QCA macro modeling |
11 | Nasser Masoumi, Mahmoud Ahmadian, Farshid Raissi, Massoud Masoumi, Jahan B. Ghasemi |
Enhancing Performance and Saving Energy in CMOS DCVSL Gates by Using a New Transistor Sizing Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWSOC ![In: Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 20-24 July 2004, Banff, Alberta, Canada, pp. 283-288, 2005, IEEE Computer Society, 0-7695-2403-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
11 | Kenneth A. Townsend, James W. Haslett, Krzysztof Iniewski |
Design and Optimization of Low-Voltage Low-Power Quasi-Floating Gate Digital Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWSOC ![In: Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 20-24 July 2004, Banff, Alberta, Canada, pp. 132-136, 2005, IEEE Computer Society, 0-7695-2403-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
11 | Haque Mohammad Munirul, Michitaka Kameyama |
Multiple-Valued Source-Coupled Logic VLSI Based on Adaptive Threshold Control and Its Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 34th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2004), 19-22 May 2004, Toronto, Canada, pp. 328-333, 2004, IEEE Computer Society, 0-7695-2130-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
11 | Jin-Hua Hong, Cheng-Wen Wu |
Cellular-array modular multiplier for fast RSA public-key cryptosystem based on modified Booth's algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 11(3), pp. 474-484, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
11 | Jürgen Fischer, Ettore Amirante, Francesco Randazzo, Giuseppe Iannaccone, Doris Schmitt-Landsiedel |
Reduction of the Energy Consumption in Adiabatic Gates by Optimal Transistor Sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation, 13th International Workshop, PATMOS 2003, Torino, Italy, September 10-12, 2003, Proceedings, pp. 309-318, 2003, Springer, 3-540-20074-6. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
11 | Sumeer Goel, Tarek Darwish, Magdy A. Bayoumi |
A Novel Technique for Noise-Tolerance in Dynamic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), New Trends and Technologies for VLSI Systems Design, 20-21 February 2003, Tampa, FL, USA, pp. 203-206, 2003, IEEE Computer Society, 0-7695-1904-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
11 | Chandramouli Gopalakrishnan, Srinivas Katkoori |
An Architectural Leakage Power Simulator for VHDL Structural Datapaths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), New Trends and Technologies for VLSI Systems Design, 20-21 February 2003, Tampa, FL, USA, pp. 211-212, 2003, IEEE Computer Society, 0-7695-1904-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
11 | Rong Lin |
A Reconfigurable Low-Power High-Performance Matrix Multiplier Architecture with Borrow Parallel Counters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 22-26 April 2003, Nice, France, CD-ROM/Abstracts Proceedings, pp. 182, 2003, IEEE Computer Society, 0-7695-1926-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
11 | Peter Celinski, Derek Abbott, Sorin Dan Cotofana |
Area efficient, high speed parallel counter circuits using charge recycling threshold logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 233-236, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
11 | Matthew M. Ziegler, Mircea R. Stan |
The CMOS/nano interface from a circuits perspective. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 904-907, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|