Search results for "full-adder"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
20	Takuya Kaizawa, Mingyu Jo, Masashi Arita, Akira Fujiwara, Kenji Yamazaki, Yukinori Ono, Hiroshi Inokawa, Yasuo Takahashi	Full Adder Operation Based on Si Nanodot Array Device with Multiple Inputs and Outputs.	Int. J. Nanotechnol. Mol. Comput.	2009	DBLP DOI BibTeX RDF
20	Keivan Navi, Amir Momeni, Fazel Sharifi, Peiman Keshavarzian	Two novel ultra high speed carbon nanotube Full-Adder cells.	IEICE Electron. Express	2009	DBLP DOI BibTeX RDF
20	Mehrdad Maeen, Vahid Foroutan, Keivan Navi	On the design of low power 1-bit full adder cell.	IEICE Electron. Express	2009	DBLP DOI BibTeX RDF
20	Keivan Navi, Mehrdad Maeen, Omid Hashemipour	An energy efficient full adder cell for low voltage.	IEICE Electron. Express	2009	DBLP DOI BibTeX RDF
20	Anindya Ghosh, Debapriyo Ghosh	Optimization of Static Power, Leakage Power and Delay of Full Adder Circuit Using Dual Threshold MOSFET Based Design and T-Spice Simulation.	ARTCom	2009	DBLP DOI BibTeX RDF
20	Farshad Moradi, Dag T. Wisland, Hamid Mahmoodi, Snorre Aunet, Tuan Vu Cao, Ali Peiravi	Ultra Low Power Full Adder Topologies.	ISCAS	2009	DBLP DOI BibTeX RDF
20	Katsumi Wasaki	Stability of n-Bit Generalized Full Adder Circuits (GFAs). Part II.	Formaliz. Math.	2008	DBLP DOI BibTeX RDF
20	Minas Dasygenis, K. Mitroglou, Dimitrios Soudris, Adonios Thanailakis	A Full-Adder-Based Methodology for the Design of Scaling Operation in Residue Number System.	IEEE Trans. Circuits Syst. I Regul. Pap.	2008	DBLP DOI BibTeX RDF
20	Keivan Navi, Omid Kavehei, Mahnoush Rouholamini, Amir Sahafi, Shima Mehrabi, Nooshin Dadkhahi	Low-Power and High-Performance 1-Bit CMOS Full-Adder Cell.	J. Comput.	2008	DBLP BibTeX RDF
20	Omid Kavehei, Mostafa Rahimi Azghadi, Keivan Navi, Amir-Pasha Mirbaha	Design of Robust and High-Performance 1-Bit CMOS Full Adder for Nanometer Design.	ISVLSI	2008	DBLP DOI BibTeX RDF
20	Gian Carlo Cardarilli, Luca Di Nunzio, Marco Re	A full-adder based reconfigurable architecture for fine grain applications: ADAPTO.	ICECS	2008	DBLP DOI BibTeX RDF
20	Deepchand Patel, Pravinkumar G. Parate, Prafulla S. Patil, S. Subbaraman	ASIC Implimentation of 1 Bit Full Adder.	ICETET	2008	DBLP DOI BibTeX RDF
20	Gian Carlo Cardarilli, Luca Di Nunzio, Marco Re, Alberto Nannarelli	ADAPTO: full-adder based reconfigurable architecture for bit level operations.	ISCAS	2008	DBLP DOI BibTeX RDF
20	Takao Waho, Hiroki Okuyama, Tomohiko Ebata, Ryousuke Kato	An ultrahigh-speed full adder using resonant-tunneling logic gates.	APCCAS	2008	DBLP DOI BibTeX RDF
20	Pradeep S. Nair, Savithra Eratne, Eugene John	Topology-related effects of Gated-Vdd and Gated-Vss techniques on full-adder leakage and delay at 65nm and 45 nm.	APCCAS	2008	DBLP DOI BibTeX RDF
20	Massimo Alioto, Giuseppe Di Cataldo, Gaetano Palumbo	Mixed Full Adder topologies for high-performance low-power arithmetic circuits.	Microelectron. J.	2007	DBLP DOI BibTeX RDF
20	Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu, Cheng-Che Ho	A Novel High-Speed and Energy Efficient 10-Transistor Full Adder Design.	IEEE Trans. Circuits Syst. I Regul. Pap.	2007	DBLP DOI BibTeX RDF
20	Chiou-Kou Tung, Yu-Cherng Hung, Shao-Hui Shieh, Guo-Shing Huang	A Low-Power High-Speed Hybrid CMOS Full Adder for Embedded System.	DDECS	2007	DBLP DOI BibTeX RDF
20	Keivan Navi, Omid Kavehei, Mahnoush Rouholamini, Amir Sahafi, Shima Mehrabi	A Novel CMOS Full Adder.	VLSI Design	2007	DBLP DOI BibTeX RDF
20	Kristian Granhaug, Snorre Aunet	Six Subthreshold Full Adder Cells Characterized in 90 nm CMOS Technology.	DDECS	2006	DBLP DOI BibTeX RDF
20	Yvan Van Rentergem, Alexis De Vos	Optimal Design of a Reversible Full Adder.	Int. J. Unconv. Comput.	2005	DBLP BibTeX RDF
20	Konstantinos Anagnostopoulos, George Economakos	Lowpower design of multipliers using a full-adder isolation technique.	ICECS	2005	DBLP DOI BibTeX RDF
20	Yingtao Jiang, Abdulkarim Al-Sheraidah, Yuke Wang, Edwin Hsing-Mean Sha, Jin-Gyun Chung	A novel multiplexer-based low-power full adder.	IEEE Trans. Circuits Syst. II Express Briefs	2004	DBLP DOI BibTeX RDF
20	Elizabeth J. Brauer, Yusuf Leblebici	Sub-70 PS full adder IN 0.18 µm CMOS current-mode logic.	Circuits, Signals, and Systems	2004	DBLP BibTeX RDF
20	Adrian Burian, Jarmo Takala	VLSI-efficient implementation of full adder-based median filter.	ISCAS (2)	2004	DBLP BibTeX RDF
20	Ahmed Sayed, Hussain Al-Asaad	Survey and Evaluation of Low-Power Full-Adder Cells.	ESA/VLSI	2004	DBLP BibTeX RDF
20	Massimo Alioto, Gaetano Palumbo	Analysis and comparison on full adder block in submicron technology.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
20	Casper Lageweg, Sorin Cotofana, Stamatis Vassiliadis	A full adder implementation using SET based linear threshold gates.	ICECS	2002	DBLP DOI BibTeX RDF
20	Dimitrios Soudris, Minas Dasygenis, K. Mitroglou, Konstantinos Tatas, Adonios Thanailakis	A full adder based methodology for scaling operation in residue number system.	ICECS	2002	DBLP DOI BibTeX RDF
20	Yngvar Berg, Snorre Aunet, Øivind Næss, O. Hagen, Mats Høvin	A novel floating-gate multiple-valued CMOS full-adder.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
20	Alejandro F. González, Mayukh Bhattacharya, Shriram Kulkarni, Pinaki Mazumder	CMOS implementation of a multiple-valued logic signed-digit full adder based on negative-differentiaI-resistance devices.	IEEE J. Solid State Circuits	2001	DBLP DOI BibTeX RDF
20	Abdulkarim Al-Sheraidah, Bassem Alhalabi, Hung Tien Bui	Five new high-performance multiplexer-based 1-bit full adder cells.	ICECS	2001	DBLP DOI BibTeX RDF
20	José M. Quintana, Maria J. Avedillo, Raúl Jiménez, Esther Rodríguez-Villegas	Low-power logic styles for full-adder circuits.	ICECS	2001	DBLP DOI BibTeX RDF
20	Bassem Alhalabi, Abdulkarim Al-Sheraidah	A novel low power multiplexer-based full adder cell.	ICECS	2001	DBLP DOI BibTeX RDF
20	D. J. Soudris, Minas Dasygenis, Adonios Thanailakis	Designing RNS and QRNS full adder based converters.	ISCAS	2000	DBLP DOI BibTeX RDF
20	Ahmed M. Shams, Magdy A. Bayoumi	A New Full Adder Cell for Low-Power Applications.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF
20	Shyh-Jye Jou, Chang-Yu Chen, En-Chung Yang, Chau-Chin Su	A pipelined multiplier-accumulator using a high-speed, low-power static and dynamic full adder design.	IEEE J. Solid State Circuits	1997	DBLP DOI BibTeX RDF
20	A. Srivastava, K. Venkatapathy	Design and Implementation of a Low Power Ternary Full Adder.	VLSI Design	1996	DBLP DOI BibTeX RDF
20	Dimitrios Soudris, Vassilis Paliouras, Thanos Stouraitis, Alexander Skavantzos, Constantinos E. Goutis	Systematic design of full adder-based architectures for convolution.	ICASSP (1)	1993	DBLP DOI BibTeX RDF
20	Seon Wook Kim, Thanos Stouraitis, Alexander Skavantzos	Full Adder-based Inner Product Step Processors for Residue and Quadratic Residue Number Systems.	ISCAS	1993	DBLP BibTeX RDF
20	K. Wayne Current	A CMOS Quaternary Threshold Logic Full Adder Circuit with Transparent Latch.	ISMVL	1990	DBLP DOI BibTeX RDF
20	Kazuo Iwano, Kenneth Steiglitz	Time-power-area tradeoffs for the nMOS VLSI full-adder.	ICASSP	1985	DBLP DOI BibTeX RDF
20	K. Wayne Current, Douglas A. Mow	Four-valued threshold logic full adder circuit implementations.	MVL	1978	DBLP BibTeX RDF
20	Donald W. Davies	An 11-Cryotron Full Adder.	IEEE Trans. Electron. Comput.	1963	DBLP DOI BibTeX RDF
20	Jon S. Squire	An 11-Cryotron Full Adder.	IRE Trans. Electron. Comput.	1962	DBLP DOI BibTeX RDF
19	Sundeepkumar Agarwal, Pavankumar V. K., Yokesh R.	Energy-Efficient, High Performance Circuits for Arithmetic Units.	VLSI Design	2008	DBLP DOI BibTeX RDF
19	William N. N. Hung, Xiaoyu Song, Guowu Yang, Jin Yang 0006, Marek A. Perkowski	Optimal synthesis of multiple output Boolean functions using a set of quantum gates by symbolic reachability analysis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
19	Petros Oikonomakos, Paul Fox	Error Correction in Arithmetic Operations by I/O Inversion.	IOLTS	2006	DBLP DOI BibTeX RDF
19	A. Prasad Vinod 0001, Edmund Ming-Kit Lai	Optimizing vertical common subexpression elimination using coefficient partitioning for designing low complexity software radio channelizers.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
19	E. Islas Pérez, Carlos A. Coello Coello, Arturo Hernández Aguirre, Alejandro Villavicencio Ramírez	Genetic Algorithms and Case-Based Reasoning as a Discovery and Learning Machine in the Optimization of Combinational Logic Circuits.	MICAI	2002	DBLP DOI BibTeX RDF
19	Hong-Yi Huang, Teng-Neng Wang	High-speed CMOS logic circuits in capacitor coupling technique.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
19	Christian Pacha, Peter Glösekötter, Karl Goser, Uwe Auer, Werner Prost, Franz-Josef Tegude	Resonant Tunneling Transistors for Threshold Logic Circuit Applications.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
16	Hirokatsu Shirahama, Takahiro Hanyu	Design of High-Performance Quaternary Adders Based on Output-Generator Sharing.	ISMVL	2008	DBLP DOI BibTeX RDF	Carry pre-addition, Differential-pair circuitry, Voltage-mode circuit, Transfer-gate circuitry, Current-mode circuit
16	Zine Abid, Wei Wang 0003	New designs of Redundant-Binary full Adders and its applications.	ISCAS	2008	DBLP DOI BibTeX RDF
13	Cecília Reis, José António Tenreiro Machado, José Boaventura Cunha, Eduardo José Solteiro Pires	Evolutionary computation in the design of logic circuits.	SMC	2007	DBLP DOI BibTeX RDF
13	Massimo Alioto, Gaetano Palumbo	Delay Variability Due to Supply Variations in Transmission-Gate Full Adders.	ISCAS	2007	DBLP DOI BibTeX RDF
13	A. Prasad Vinod 0001, Ankita Singla, Chip-Hong Chang	Improved differential coefficients-based low power FIR filters. Part I. Fundamentals.	ISCAS	2006	DBLP DOI BibTeX RDF
13	A. Prasad Vinod 0001, Chip-Hong Chang, Pramod Kumar Meher, Ankita Singla	Low Power FIR Filter Realization using Minimal Difference Coefficients: Part I - Complexity Analysis.	APCCAS	2006	DBLP DOI BibTeX RDF
13	Xingjun Wu, Hongyi Chen, Yihe Sun, Weixin Gai	A Fully-Pipeline Linear Systolic Architecture for Modular Multiplier in Public-Key Crypto-Systems.	J. VLSI Signal Process.	2003	DBLP DOI BibTeX RDF	public-key crypto-system, systolic array, modular-multiplication, pipeline architecture, modular-exponentiation
13	Miguel Garvie, Adrian Thompson	Evolution of Combinatonial and Sequential On-Line Self-Diagnosing Hardware.	Evolvable Hardware	2003	DBLP DOI BibTeX RDF
13	Kiamal Z. Pekmestzi, Nikos K. Moshopoulos	A Systolic, High Speed Architecture for an RSA Cryptosystem.	J. VLSI Signal Process.	2002	DBLP DOI BibTeX RDF	Montgomery algorithm, modular squaring, RSA, public key cryptography, modular multiplication
13	Christian Lütkemeyer	An Optimized Coefficient Update Processor for High-Throughput Adaptive Equalizers.	ASAP	1997	DBLP DOI BibTeX RDF
11	Flavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner	Transmission Gates Combined With Level-Restoring CMOS Gates Reduce Glitches in Low-Power Low-Frequency Multipliers.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
11	Alex Piñeiro, Javier D. Bruguera, Fabrizio Lamberti, Paolo Montuschi	A Radix-2 Digit-by-Digit Architecture for Cube Root.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	Cost/performance, High-Speed Arithmetic
11	Håvard Pedersen Alstad, Snorre Aunet	Improving Circuit Security against Power Analysis Attacks with Subthreshold Operation.	DDECS	2008	DBLP DOI BibTeX RDF
11	Manoj Singh Gaur, Raghavendra Narasimhan, Vijay Laxmi, Ujjwal Kumar	Structural Fault Modelling in Nano Devices.	NanoNet	2008	DBLP DOI BibTeX RDF	Structural fault, stuck-at-0, stuck-at-1, MRF, bridge, TMR
11	Nobuaki Okada, Michitaka Kameyama	Fine-Grain Multiple-Valued Reconfigurable VLSI Using Universal-Literal-Based Cells.	ISMVL	2008	DBLP DOI BibTeX RDF	Field-programmable VLSI, Multiple-valued source-coupled logic, Differential-Pair circuit, Bit-serial architecture
11	Snorre Aunet, Hans Kristian Otnes Berge	Statistical Simulations for Exploring Defect Tolerance and Power Consumption for 4 Subthreshold 1-Bit Addition Circuits.	IWANN	2007	DBLP DOI BibTeX RDF
11	Junchen Liu, Ian O'Connor, David Navarro, Frédéric Gaffiot	Design of a Novel CNTFET-based Reconfigurable Logic Gate.	ISVLSI	2007	DBLP DOI BibTeX RDF
11	Elhadj Benkhelifa, Anthony G. Pipe, Gabriel Dragffy, Mokhtar Nibouche	Towards evolving fault tolerant biologically inspired hardware using evolutionary algorithms.	IEEE Congress on Evolutionary Computation	2007	DBLP DOI BibTeX RDF
11	Junchen Liu, Ian O'Connor, David Navarro, Frédéric Gaffiot	Novel CNTFET-based Reconfigurable Logic Gate Design.	DAC	2007	DBLP DOI BibTeX RDF
11	Koichi Itoh, Masashi Yamazaki, Shinji Nakamura, Yasuo Nagazumi	An Attempt Towards Charge-Domain Logic (CDL).	CISS	2007	DBLP DOI BibTeX RDF
11	Ricardo C. Goncalves da Silva, Henri Boudinov, Luigi Carro	A cell library for low power high performance CMOS voltage-mode quaternary logic.	SBCCI	2006	DBLP DOI BibTeX RDF	quaternary logic design, voltage-mode, multi-valued logic
11	Akira Mochizuki, Takahiro Hanyu	Highly reliable Multiple-Valued Circuit Based on Dual-Rail Differential Logic.	ISMVL	2006	DBLP DOI BibTeX RDF
11	Omer Can Akgun, Yusuf Leblebici	Weak inversion performance of CMOS and DCVSPG logic families in sub-300 mV range.	ISCAS	2006	DBLP DOI BibTeX RDF
11	Rui Liu, Sanyou Zeng, Lixin Ding, Lishan Kang, Hui Li, Yuping Chen, Yong Liu 0012, Yueping Han	An Efficient Multi-Objective Evolutionary Algorithm for Combinational Circuit Design.	AHS	2006	DBLP DOI BibTeX RDF	Gartesian Genetic Programming, Multiobjective Evolutionary Algorithm, Combinational logic Circuit
11	Robert Ross, Richard Hall	A FPGA Simulation Using Asexual Genetic Algorithms for Integrated Self-Repair.	AHS	2006	DBLP DOI BibTeX RDF
11	Sandeep B. Singh, Jayanta Biswas, S. K. Nandy 0001	A Cost Effective Pipelined Divider for Double Precision Floating Point Number.	ASAP	2006	DBLP DOI BibTeX RDF
11	Yanjie Mao, Chunhong Chen	Performance Evaluation and Optimization of Full Adders with Single-Electron Technology.	CCECE	2006	DBLP DOI BibTeX RDF
11	Yi Wang 0016, Douglas L. Maskell, Jussipekka Leiwo, Thambipillai Srikanthan	Unified Signed-Digit Number Adder for RSA and ECC Public-key Cryptosystems.	APCCAS	2006	DBLP DOI BibTeX RDF
11	A. Prasad Vinod 0001, Chip-Hong Chang, Pramod Kumar Meher, Ankita Singla	Low Power FIR Filter Realization Using Minimal Difference Coefficients: Part II - Algorithm.	APCCAS	2006	DBLP DOI BibTeX RDF
11	Samir Roy, Biswajit Saha	Minority Gate Oriented Logic Design with Quantum-Dot Cellular Automata.	ACRI	2006	DBLP DOI BibTeX RDF	Nano-computing, Minority Gate, Quantum-dot Cellular Automata
11	N. Huot, H. Dubreuil, Laurent Fesquet, Marc Renaudin	FPGA Architecture for Multi-Style Asynchronous Logic.	DATE	2005	DBLP DOI BibTeX RDF
11	Jae-Jin Lee, Gi-Yong Song	Design of an application-specific PLD architecture.	ASP-DAC	2005	DBLP DOI BibTeX RDF
11	Guoqiang Hang	Adiabatic CMOS gate and adiabatic circuit design for low-power applications.	ASP-DAC	2005	DBLP DOI BibTeX RDF
11	Ulya R. Karpuzcu	Automatic verilog code generation through grammatical evolution.	GECCO Workshops	2005	DBLP DOI BibTeX RDF	automatic code generation, grammatical evolution, verilog
11	Hideki Fukuda	Signed-digit CMOS (SD-CMOS) Logic Circuits with Dynamic Operation.	ISMVL	2005	DBLP DOI BibTeX RDF
11	Rui Tang, Fengming Zhang, Yong-Bin Kim	QCA-based nano circuits design [adder design example].	ISCAS (3)	2005	DBLP DOI BibTeX RDF
11	Julio Villalba, Javier Hormigo, Jose M. Prades, Emilio L. Zapata	On-line Multioperand Addition Based on On-line Full Adders.	ASAP	2005	DBLP DOI BibTeX RDF
11	Rui Tang, Fengming Zhang, Yong-Bin Kim	Quantum-dot cellular automata SPICE macro model.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	QCA macro modeling
11	Nasser Masoumi, Mahmoud Ahmadian, Farshid Raissi, Massoud Masoumi, Jahan B. Ghasemi	Enhancing Performance and Saving Energy in CMOS DCVSL Gates by Using a New Transistor Sizing Algorithm.	IWSOC	2005	DBLP DOI BibTeX RDF
11	Kenneth A. Townsend, James W. Haslett, Krzysztof Iniewski	Design and Optimization of Low-Voltage Low-Power Quasi-Floating Gate Digital Circuits.	IWSOC	2005	DBLP DOI BibTeX RDF
11	Haque Mohammad Munirul, Michitaka Kameyama	Multiple-Valued Source-Coupled Logic VLSI Based on Adaptive Threshold Control and Its Applications.	ISMVL	2004	DBLP DOI BibTeX RDF
11	Jin-Hua Hong, Cheng-Wen Wu	Cellular-array modular multiplier for fast RSA public-key cryptosystem based on modified Booth's algorithm.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
11	Jürgen Fischer, Ettore Amirante, Francesco Randazzo, Giuseppe Iannaccone, Doris Schmitt-Landsiedel	Reduction of the Energy Consumption in Adiabatic Gates by Optimal Transistor Sizing.	PATMOS	2003	DBLP DOI BibTeX RDF
11	Sumeer Goel, Tarek Darwish, Magdy A. Bayoumi	A Novel Technique for Noise-Tolerance in Dynamic Circuits.	ISVLSI	2003	DBLP DOI BibTeX RDF
11	Chandramouli Gopalakrishnan, Srinivas Katkoori	An Architectural Leakage Power Simulator for VHDL Structural Datapaths.	ISVLSI	2003	DBLP DOI BibTeX RDF
11	Rong Lin	A Reconfigurable Low-Power High-Performance Matrix Multiplier Architecture with Borrow Parallel Counters.	IPDPS	2003	DBLP DOI BibTeX RDF
11	Peter Celinski, Derek Abbott, Sorin Dan Cotofana	Area efficient, high speed parallel counter circuits using charge recycling threshold logic.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
11	Matthew M. Ziegler, Mircea R. Stan	The CMOS/nano interface from a circuits perspective.	ISCAS (4)	2003	DBLP DOI BibTeX RDF