Search results for "hSpice"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
10	Kuo-Hsing Cheng, Yu-Lung Lo, Wen Fang Yu, Shu-Yin Hung	A Mixed-Mode Delay-Locked Loop for Wide-Range Operation and Multiphase Clock Generation.	IWSOC	2003	DBLP DOI BibTeX RDF
10	Yuh-Fang Tsai, David Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin	Implications of technology scaling on leakage reduction techniques.	DAC	2003	DBLP DOI BibTeX RDF	low power, technology scaling, leakage reduction
10	Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang	Noise constrained transistor sizing and power optimization for dual Vst domino logic.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
10	Philippe Maurine, Mustapha Rezzoug, Nadine Azémard, Daniel Auvergne	Transition time modeling in deep submicron CMOS.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
10	José Luis Rosselló, Jaume Segura 0001	Charge-based analytical model for the evaluation of powerconsumption in submicron CMOS buffers.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
10	Yungseon Eo, Jongin Shim, William R. Eisenstadt	A traveling-wave-based waveform approximation technique for thetiming verification of single transmission lines.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
10	Taku Uchino, Jason Cong	An interconnect energy model considering coupling effects.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
10	José Luis Rosselló, Jaume Segura 0001	A Compact Charge-Based Propagation Delay Model for Submicronic CMOS Buffers.	PATMOS	2002	DBLP DOI BibTeX RDF
10	Carmen Baena Oliva, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Carlos Jesús Jiménez-Fernández, Manuel Valencia 0001	Measurement of the Switching Activity of CMOS Digital Circuits at the Gate Level.	PATMOS	2002	DBLP DOI BibTeX RDF
10	Philippe Maurine, Nadine Azémard, Daniel Auvergne	Structure Independent Representation of Output Transition Time for CMOS Library.	PATMOS	2002	DBLP DOI BibTeX RDF
10	Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel J. Bellido, Alejandro Millán 0001, David Guerrero Martos	Efficient and Fast Current Curve Estimation of CMOS Digital Circuits at the Logic Level.	PATMOS	2002	DBLP DOI BibTeX RDF
10	Fabrice Picot, Philippe Coll, Daniel Auvergne	Crosstalk Measurement Technique for CMOS ICs.	PATMOS	2002	DBLP DOI BibTeX RDF
10	Gregorio Cappuccino, Giuseppe Cocorullo	Operating Region Modelling and Timing Analysis of CMOS Gates Driving Transmission Lines.	PATMOS	2002	DBLP DOI BibTeX RDF
10	Mohamed A. Elgamel, Tarek Darwish, Magdy A. Bayoumi	Noise Tolerant Low Power Dynamic TSPCL D Flip-Flops.	ISVLSI	2002	DBLP DOI BibTeX RDF	noise, power, flip-flop, deep submicron
10	Tom J. Kazmierski, Neil Clayton	A Two-Tier Distributed Electronic Design Framework.	DATE	2002	DBLP DOI BibTeX RDF
10	Paul I. Pénzes, Alain J. Martin	An Energy Estimation Method for Asynchronous Circuits with Application to an Asynchronous Microprocessor.	DATE	2002	DBLP DOI BibTeX RDF
10	Recep O. Ozdag, Peter A. Beerel	High-Speed QDI Asynchronous Pipelines.	ASYNC	2002	DBLP DOI BibTeX RDF	conditional split, conditional join, QDI, pipelines, asynchronous, dynamic logic, joins, non-linear, fine-grain, micropipelines, forks
10	Harshit K. Shah, Pun H. Shiu, Brian Bell, Mamie Aldredge, Namarata Sopory, Jeff Davis	Repeater insertion and wire sizing optimization for throughput-centric VLSI global interconnects.	ICCAD	2002	DBLP DOI BibTeX RDF
10	Motoi Inaba, Koichi Tanno, Okihiko Ishizuka	Multi-Valued Flip-Flop with Neuron-CMOS NMIN Circuits.	ISMVL	2002	DBLP DOI BibTeX RDF	Multi-valued flip-flop, Down literal circuit, Analog inverter, Voltage comparator, NMIN circuit
10	Yongjian Brandon Guo, K. Wayne Current	Voltage Comparator Circuits for Multiple-Valued CMOS Logic.	ISMVL	2002	DBLP DOI BibTeX RDF	voltage comparator, MVL, low-power, CMOS
10	Joohee Kim, Conrad H. Ziesler, Marios C. Papaefthymiou	Energy recovering static memory.	ISLPED	2002	DBLP DOI BibTeX RDF	adiabatic circuitry, charge recovery, cache memories, on-chip memories, low-power computing, low-energy design
10	Arif Ishaq Abou-Seido, Brian Nowak, Chris C. N. Chu	Fitted Elmore Delay: A Simple and Accurate Interconnect Delay Model.	ICCD	2002	DBLP DOI BibTeX RDF
10	Yen-Jen Chang, Feipei Lai, Shanq-Jang Ruan	Cache Design for Eliminating the Address Translation Bottleneck and Reducing the Tag Area Cost.	ICCD	2002	DBLP DOI BibTeX RDF
10	João Silva, Nuno Cavaco Gomes Horta	GENOM: circuit-level optimizer based on a modified genetic algorithm kernel.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
10	J. A. López, Ginés Doménech, R. Ruiz, Tom J. Kazmierski	Automated high level synthesis of hardware building blocks present in ART-based neural networks, from VHDL-AMS descriptions.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
10	Ayman A. Fayed, Magdy A. Bayoumi	Noise-tolerant design and analysis for a low-voltage dynamic full adder cell.	ISCAS (3)	2002	DBLP DOI BibTeX RDF
10	Sangwook Kim, E. Greeneich	Body effect compensated switch for low voltage switched-capacitor circuits.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
10	Fazrena A. Hamid, Tom J. Kazmierski	Synthesis and optimization of analog VLSI filters from VHDL-AMS parse trees.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
10	K. Moolpho, Jitkasem Ngarmnil, K. Nandhasri	A low-voltage wide-swing FGMOS current amplifier.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
10	Takahide Sato, Shigetaka Takagi, Nobuo Fujii	Rail-to-rail OTA using a pair of single channel type MOSFETs.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
10	Takao Oura, Teru Yoneyama, Shashidhar Tantry, Hideki Asai	A threshold voltage independent floating resistor circuit exhibiting both positive and negative resistance values.	ISCAS (3)	2002	DBLP DOI BibTeX RDF
10	G. R. Chaji, Seid Mehdi Fakhraie, Kenneth Carless Smith	Pseudo dynamic logic (SDL): a high-speed and low-power dynamic logic family.	ISCAS (3)	2002	DBLP DOI BibTeX RDF
10	Li Ding 0002, Pinaki Mazumder, David T. Blaauw	Crosstalk noise estimation using effective coupling capacitance.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
10	G. A. Al-Rawi	A new offset measurement and cancellation technique for dynamic latches.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
10	Bill Pontikakis, Mohamed Nekili	A novel double edge-triggered pulse-clocked TSPC D flip-flop for high-performance and low-power VLSI design applications.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
10	Ramin Rafati, A. Z. Charaki, G. R. Chaji, Seid Mehdi Fakhraie, Kenneth Carless Smith	Comparison of a 17 b multiplier in Dual-rail domino and in Dual-rail D3L (D4L) logic styles.	ISCAS (3)	2002	DBLP DOI BibTeX RDF
10	Lyes Bouzerara, Mohand-Tahar Belaroussi	Low-voltage, low-power and high gain CMOS operational transconductance amplifier.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
10	Toshihiko Yamasaki, Teruyasu Taguchi, Tadashi Shibata	Low-power CDMA analog matched filters based on floating-gate technology.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
10	Falah R. Awwad, Mohamed Nekili	Variable-segment & variable-driver parallel regeneration techniques for RLC VLSI interconnects.	ACM Great Lakes Symposium on VLSI	2002	DBLP DOI BibTeX RDF	parallel regeneration, VLSI, repeater, RLC interconnect
10	Bipul Chandra Paul, Kaushik Roy 0001	Testing CrossTalk Induced Delay Faults in Static CMOS Circuits Through Dynamic Timing Analysis.	ITC	2002	DBLP DOI BibTeX RDF
10	Yen-Jen Chang, Feipei Lai	Paged cache: an efficient partition architecture for reducing power, area and access time.	APCCAS (2)	2002	DBLP DOI BibTeX RDF
10	S. Swaminathan, Shankar M. Krishnan, Khiang Wee Lim, Zubir Ahamed, Gilbert Chiang	Microsensor characterization in an integrated blood gas measurement system.	APCCAS (1)	2002	DBLP DOI BibTeX RDF
10	Apinunt Thanachayanont	2-V 3.36-mW 2.5-GHz fourth-order inductorless CMOS RF bandpass filter.	APCCAS (1)	2002	DBLP DOI BibTeX RDF
10	Shashidhar Tantry, Takao Oura, Teru Yoneyama, Hideki Asai	A low voltage floating resistor having positive and negative resistance values.	APCCAS (1)	2002	DBLP DOI BibTeX RDF
10	Y. C. Hung, B. D. Liu	An analog CMOS rank-order extractor with O(N) complexity using maximum/winner-take-all circuit.	APCCAS (2)	2002	DBLP DOI BibTeX RDF
10	Chung-Yun Chou, Chung-Yu Wu	The design of a new wideband and low-power CMOS active polyphase filter for low-IF receiver applications.	APCCAS (1)	2002	DBLP DOI BibTeX RDF
10	Raguraman Venkatesan, Jeffrey A. Davis, James D. Meindl	A physical model for the transient response of capacitively loaded distributed rlc interconnects.	DAC	2002	DBLP DOI BibTeX RDF	distributed rlc lines, overshoot, interconnects, crosstalk, time delay, repeaters, transient response
10	Srinivas Bodapati, Farid N. Najm	High-level current macro-model for power-grid analysis.	DAC	2002	DBLP DOI BibTeX RDF	current macro-model, DCT, power grid
10	Ashok K. Murugavel, N. Ranganathan	Petri net modeling of gate and interconnect delays for power estimation.	DAC	2002	DBLP DOI BibTeX RDF
10	Hiroaki Yamaoka, Makoto Ikeda, Kunihiro Asada	A high-speed PLA using array logic circuits with latch sense amplifiers and a charge sharing scheme.	ASP-DAC	2001	DBLP DOI BibTeX RDF
10	Jason Cong, David Zhigang Pan, Prasanna V. Srinivas	Improved crosstalk modeling for noise constrained interconnect optimization.	ASP-DAC	2001	DBLP DOI BibTeX RDF
10	Amorn Jiraseree-amornkun, Boonruk Chipipop, Wanlop Surakampontorn	Novel translinear-based multi-output FTFN.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
10	Yonghui Tang, Randall L. Geiger	A 2.5 Gbit/s CMOS PLL for data/clock recovery without frequency divider.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
10	Manuel J. Bellido, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, Antonio J. Acosta 0001, Manuel Valencia-Barrero	Gate-level simulation of CMOS circuits using the IDDM model.	ISCAS (5)	2001	DBLP DOI BibTeX RDF
10	Eduard Alarcón, Alberto Poveda, Eva Vidal, Herminio Martínez	Analog current-mode implementation of a one-cycle integrated controller for switching power converters.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
10	Emmanuel M. Drakakis, Alison J. Payne, Christofer Toumazou, Andrew E. J. Ng, John I. Sewell	High-order lowpass and bandpass elliptic log-domain ladder filters.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
10	Chun Lu, Bingxue Shi, Lu Chen	A programmable on-chip BP learning neural network with enhanced neuron characteristics.	ISCAS (3)	2001	DBLP DOI BibTeX RDF
10	Jin-Ku Kang, Dong-Hee Kim	A CMOS clock and data recovery with two-XOR phase-frequency detector circuit.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
10	Teemu Suutari, Jouni Isoaho, Hannu Tenhunen	High-speed serial communication with error correction using 0.25 um CMOS technology.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
10	Ayman A. Fayed, Magdy A. Bayoumi	A low power 10-transistor full adder cell for embedded architectures.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
10	Philippe Maurine, Mustapha Rezzoug, Daniel Auvergne	Output transition time modeling of CMOS structures.	ISCAS (5)	2001	DBLP DOI BibTeX RDF
10	Imed Ben Dhaou, Hannu Tenhunen, Vijay Sundararajan, Keshab K. Parhi	Energy efficient signaling in DSM CMOS technology.	ISCAS (5)	2001	DBLP DOI BibTeX RDF
10	Jin-Jer Jong, Chen-Yi Lee	A novel structure for portable digitally controlled oscillator.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
10	Apinunt Thanachayanont	A 1.5-V CMOS fully differential inductorless RF bandpass amplifier.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
10	Geng Bai, Sudhakar Bobba, Ibrahim N. Hajj	RC Power Bus Maximum Voltage Drop in Digital VLSI Circuits.	ISQED	2001	DBLP DOI BibTeX RDF
10	Xiaoliang Bai, Sujit Dey	High-level Crosstalk Defect Simulation for System-on-Chip Interconnects.	VTS	2001	DBLP DOI BibTeX RDF	System-on-Chip, Crosstalk, Interconnect test, Defect simulation, High level
10	Yue-Tsang Chen, Chauchin Su	Test Waveform Shaping in Mixed Signal Test Bus by Pre-Equalization.	VTS	2001	DBLP DOI BibTeX RDF
10	Allen E. Sjogren, Chris J. Myers	Interfacing synchronous and asynchronous modules within a high-speed pipeline.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
10	Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Antonio J. Acosta 0001, Manuel Valencia-Barrero	Degradation Delay Model Extension to CMOS Gates.	PATMOS	2000	DBLP DOI BibTeX RDF
10	Mustapha Rezzoug, Philippe Maurine, Daniel Auvergne	Second Generation Delay Model for Submicron CMOS Process.	PATMOS	2000	DBLP DOI BibTeX RDF
10	Fabrizio Viglione, Guido Masera, Gianluca Piccinini, Massimo Ruo Roch, Maurizio Zamboni	A 50 Mbit/s Iterative Turbo-Decoder.	DATE	2000	DBLP DOI BibTeX RDF
10	Luca Benini, Giuliano Castelli, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi	A Discrete-Time Battery Model for High-Level Power Estimation.	DATE	2000	DBLP DOI BibTeX RDF
10	Montek Singh, Steven M. Nowick	High-Throughput Asynchronous Pipelines for Fine-Grain Dynamic Datapaths.	ASYNC	2000	DBLP DOI BibTeX RDF	fine-grain pipelining, VLSI, pipelines, asynchronous, dynamic logic, FIFO, high-throughput, digital design
10	Makoto Syuto, Jing Shen, Koichi Tanno, Okihiko Ishizuka	Multi-Input Variable-Threshold Circuits for Multi-Valued Logic Functions.	ISMVL	2000	DBLP DOI BibTeX RDF
10	Takahiro Hanyu, Hiromitsu Kimura, Michitaka Kameyama	DRAM-Cell-Based Multiple-Valued Logic-in-Memory VLSI with Charge Addition and Charge Storage.	ISMVL	2000	DBLP DOI BibTeX RDF	logic-in-memory, communication bottleneck, threshold operation, functional pass gate, DRAM, multiple-valued logic
10	Kyeounsoo Kim, Peter A. Beerel, Youpyo Hong	An asynchronous matrix-vector multiplier for discrete cosine transform.	ISLPED	2000	DBLP DOI BibTeX RDF	asynchronous matrix-vector multiplier, discrete cosine transform
10	Hak-soo Yu, Songjun Lee, Jacob A. Abraham	An Adder Using Charge Sharing and its Application in DRAMs.	ICCD	2000	DBLP DOI BibTeX RDF
10	Bibhudatta Sahoo 0002, Martin Kuhlmann, Keshab K. Parhi	A low-power correlator.	ACM Great Lakes Symposium on VLSI	2000	DBLP DOI BibTeX RDF
10	Geng Bai, Sudhakar Bobba, Ibrahim N. Hajj	Power Bus Maximum Voltage Drop in Digital VLSI Circuits.	ISQED	2000	DBLP DOI BibTeX RDF
10	Chun Lu, Bingxue Shi	Circuit Realization of a Programmable Neuron Transfer Function and Its Derivative.	IJCNN (4)	2000	DBLP DOI BibTeX RDF	Artificial Neural Networks (ANN), CMOS analogue integrated circuits
10	Liqiong Wei, Zhanping Chen, Kaushik Roy 0001, Mark C. Johnson, Yibin Ye, Vivek De	Design and optimization of dual-threshold circuits for low-voltage low-power applications.	IEEE Trans. Very Large Scale Integr. Syst.	1999	DBLP DOI BibTeX RDF
10	Teresa Serrano-Gotarredona, Ángel Rodríguez-Vázquez	On the Design of Second Order Dynamics Reaction-Diffusion CNNs.	J. VLSI Signal Process.	1999	DBLP DOI BibTeX RDF
10	Jung Hyun Choi, Sergio Bampi	OTA Amplifiers Design on Digital Sea-of-Transistors Array.	DATE	1999	DBLP DOI BibTeX RDF
10	Per Arne Karlsen, Per Torstein Røine	A Timing Verifier and Timing Profiler for Asynchronous Circuits.	ASYNC	1999	DBLP DOI BibTeX RDF
10	Rung-Bin Lin, Jinq-Chang Chen	Low Power CMOS Off-Chip Drivers with Slew-rate Difference.	ASP-DAC	1999	DBLP DOI BibTeX RDF
10	Jack L. Chan, Steve S. Chung	Universal Switched-Current Integrator Blocks for SI Filter Design.	ASP-DAC	1999	DBLP DOI BibTeX RDF
10	Jason Cong, David Zhigang Pan	Interconnect Delay Estimation Models for Synthesis and Design Planning.	ASP-DAC	1999	DBLP DOI BibTeX RDF
10	Jing Shen, Koichi Tanno, Okihiko Ishizuka	Down Literal Circuit with Neuron-MOS Transistors and Its Applications.	ISMVL	1999	DBLP DOI BibTeX RDF
10	Maitham Shams, Mohamed I. Elmasry	Delay Optimization of CMOS Logic Circuits Using Closed-Form Expressions.	ICCD	1999	DBLP DOI BibTeX RDF
10	Qi Wang, Sarma B. K. Vrudhula	An Investigation of Power Delay Tradeoffs for Dual Vt CMOS Circuits.	ICCD	1999	DBLP DOI BibTeX RDF	low power, CMOS circuits, dual Vt
10	Yi-Chang, Edwin W. Greeneich	A current-controlled oscillator coarse-steering acquisition-aid for high frequency SOI CMOS PLL circuits.	ISCAS (2)	1999	DBLP DOI BibTeX RDF
10	Kaushik Roy 0001, Liqiong Wei, Zhanping Chen	Multiple-Vdd multiple-Vth CMOS (MVCMOS) for low power applications.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
10	Adnan Kabbani, A. J. Al-Khalili	Estimation of ground bounce effects on CMOS circuits.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
10	Jesper Steensgaard	Bootstrapped low-voltage analog switches.	ISCAS (2)	1999	DBLP DOI BibTeX RDF
10	Kei-Yong Khoo, Zhan Yu, Alan N. Willson Jr.	Improved-Booth encoding for low-power multipliers.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
10	Adnan Kabbani, A. J. Al-Khalili	Dynamic CMOS noise immunity estimation in submicron regime.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
10	Julius Georgiou, Emmanuel M. Drakakis, Christofer Toumazou, P. Premanoj	An analogue micropower log-domain silicon circuit for the Hodgkin and Huxley nerve axon.	ISCAS (2)	1999	DBLP DOI BibTeX RDF
10	Andrew B. Kahng, Sudhakar Muddu	Improved Effective Capacitance Computations for Use in Logic and Layout Optimization.	VLSI Design	1999	DBLP DOI BibTeX RDF
10	S. Turgis, Daniel Auvergne	A novel macromodel for power estimation in CMOS structures.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
10	Payam Heydari, Massoud Pedram	Calculation of ramp response of lossy transmission lines using two-port network functions.	ISPD	1998	DBLP DOI BibTeX RDF