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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 4224 occurrences of 1958 keywords
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Results
Found 5158 publication records. Showing 5158 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
19 | Hans Vandierendonck, Philippe Manet, Thibault Delavallee, Igor Loiselle, Jean-Didier Legat |
By-passing the out-of-order execution pipeline to increase energy-efficiency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the 4th Conference on Computing Frontiers, 2007, Ischia, Italy, May 7-9, 2007, pp. 97-104, 2007, ACM, 978-1-59593-683-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
instruction wake-up, energy-efficiency, instruction scheduling, out-of-order execution |
19 | Gongqiong Li, Zhaolin Li |
Optimized design of a double-precision floating-point multiply-add-dused unit for data dependence. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 25th International Conference on Computer Design, ICCD 2007, 7-10 October 2007, Lake Tahoe, CA, USA, Proceedings, pp. 311-316, 2007, IEEE, 1-4244-1258-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Andhi Janapsatya, Aleksandar Ignjatovic, Sri Parameswaran |
Exploiting statistical information for implementation of instruction scratchpad memory in embedded system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 14(8), pp. 816-829, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Xianfeng Li, Abhik Roychoudhury, Tulika Mitra |
Modeling out-of-order processors for WCET analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Real Time Syst. ![In: Real Time Syst. 34(3), pp. 195-227, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Worst-case execution time (WCET) analysis, Out-of-order superscalar processor, Branch prediction, Instruction cache |
19 | Asadollah Shahbahrami, Ben H. H. Juurlink, Demid Borodin, Stamatis Vassiliadis |
Avoiding Conversion and Rearrangement Overhead in SIMD Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Parallel Program. ![In: Int. J. Parallel Program. 34(3), pp. 237-260, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Embedded media processors, multimedia kernels, register file, subword parallelism |
19 | Juan L. Aragón, José M. González, Antonio González 0001 |
Control Speculation for Energy-Efficient Next-Generation Superscalar Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 55(3), pp. 281-291, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
low-power design, processor architecture, energy-aware systems, Control speculation |
19 | Jin Lin, Wei-Chung Hsu, Pen-Chung Yew, Roy Dz-Ching Ju, Tin-Fook Ngai |
Recovery code generation for general speculative optimizations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 3(1), pp. 67-89, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Recovery code, multi-level data speculation, speculative SSA form |
19 | Olivier Rochecouste, Gilles Pokam, André Seznec |
A case for a complexity-effective, width-partitioned microarchitecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 3(3), pp. 295-326, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Power analysis |
19 | Xiaotong Zhuang, Santosh Pande |
Parallelizing load/stores on dual-bank memory embedded processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 5(3), pp. 613-657, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
memory bank allocation, parallel load/stores, profile driven optimization, DSP architectures |
19 | Wu-An Kuo, TingTing Hwang, Allen C.-H. Wu |
Decomposition of instruction decoders for low-power designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 11(4), pp. 880-889, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
instruction decoder, Low power |
19 | Chengmo Yang, Alex Orailoglu |
Power-efficient instruction delivery through trace reuse. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACT ![In: 15th International Conference on Parallel Architectures and Compilation Techniques (PACT 2006), Seattle, Washington, USA, September 16-20, 2006, pp. 192-201, 2006, ACM, 1-59593-264-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
adaptive processor, low-power design, instruction delivery |
19 | Robert G. Dimond, Oskar Mencer, Wayne Luk |
Automating processor customisation: optimised memory access and resource sharing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 206-211, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Hyesoon Kim, José A. Joao, Onur Mutlu, Yale N. Patt |
Diverge-Merge Processor (DMP): Dynamic Predicated Execution of Complex Control-Flow Graphs Based on Frequently Executed Paths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-39 2006), 9-13 December 2006, Orlando, Florida, USA, pp. 53-64, 2006, IEEE Computer Society, 0-7695-2732-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Christopher Lupo, Kent D. Wilken |
Post Register Allocation Spill Code Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CGO ![In: Fourth IEEE/ACM International Symposium on Code Generation and Optimization (CGO 2006), 26-29 March 2006, New York, New York, USA, pp. 245-255, 2006, IEEE Computer Society, 0-7695-2499-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Sumeet Kumar, Aneesh Aggarwal |
Reducing resource redundancy for concurrent error detection techniques in high performance microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 12th International Symposium on High-Performance Computer Architecture, HPCA-12 2006, Austin, Texas, USA, February 11-15, 2006, pp. 212-221, 2006, IEEE Computer Society, 0-7803-9368-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Gang Ren 0002, Peng Wu 0001, David A. Padua |
Optimizing data permutations for SIMD devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the ACM SIGPLAN 2006 Conference on Programming Language Design and Implementation, Ottawa, Ontario, Canada, June 11-14, 2006, pp. 118-131, 2006, ACM, 1-59593-320-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
SIMD compilation, data permutation, optimization |
19 | Hui Wu 0001, Joxan Jaffar, Jingling Xue |
Instruction Scheduling with Release Times and Deadlines on ILP Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTCSA ![In: 12th IEEE Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2006), 16-18 August 2006, Sydney, Australia, pp. 51-60, 2006, IEEE Computer Society, 0-7695-2676-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Jack Whitham, Neil C. Audsley |
MCGREP - A Predictable Architecture for Embedded Real-Time Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTSS ![In: Proceedings of the 27th IEEE Real-Time Systems Symposium (RTSS 2006), 5-8 December 2006, Rio de Janeiro, Brazil, pp. 13-24, 2006, IEEE Computer Society, 0-7695-2761-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Tanausú Ramírez, Alex Pajuelo, Oliverio J. Santana, Mateo Valero |
Kilo-instruction processors, runahead and prefetching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the Third Conference on Computing Frontiers, 2006, Ischia, Italy, May 3-5, 2006, pp. 269-278, 2006, ACM, 1-59593-302-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
runahead, prefetching, speculative execution, memory wall, Kilo-instruction processors |
19 | H. C. Wang, C. K. Yuen |
A general framework to build new CPUs by mapping abstract machine code to instruction level parallel execution hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGARCH Comput. Archit. News ![In: SIGARCH Comput. Archit. News 33(4), pp. 113-120, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Nicholas Andrew Bradley, Mark D. Dunlop |
An Experimental Investigation into Wayfinding Directions for Visually Impaired People. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Pers. Ubiquitous Comput. ![In: Pers. Ubiquitous Comput. 9(6), pp. 395-403, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Resit Sendag, Ying Chen, David J. Lilja |
The Impact of Incorrectly Speculated Memory Operations in a Multithreaded Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 16(3), pp. 271-285, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
mispredicted loads, wrong execution, wrong execution cache, prefetching, Speculation, multithreaded architecture |
19 | Changpeng Fang, Steve Carr 0001, Soner Önder, Zhenlin Wang |
Instruction Based Memory Distance Analysis and its Application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: 14th International Conference on Parallel Architectures and Compilation Techniques (PACT 2005), 17-21 September 2005, St. Louis, MO, USA, pp. 27-37, 2005, IEEE Computer Society, 0-7695-2429-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Dinesh C. Suresh, Walid A. Najjar, Jun Yang 0002 |
Power Efficient Instruction Caches for Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Embedded Computer Systems: Architectures, Modeling, and Simulation 5th International Workshop, SAMOS 2005, Samos, Greece, July 18-20, 2005, Proceedings, pp. 182-191, 2005, Springer, 3-540-26969-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Newton Cheung, Sri Parameswaran, Jörg Henkel |
Battery-aware instruction generation for embedded processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 553-556, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Alex Pajuelo, Antonio González 0001, Mateo Valero |
Control-Flow Independence Reuse via Dynamic Vectorization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), CD-ROM / Abstracts Proceedings, 4-8 April 2005, Denver, CO, USA, 2005, IEEE Computer Society, 0-7695-2312-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Madhavi Gopal Valluri, Lizy Kurian John, Kathryn S. McKinley |
Low-power, low-complexity instruction issue using compiler assistance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 19th Annual International Conference on Supercomputing, ICS 2005, Cambridge, Massachusetts, USA, June 20-22, 2005, pp. 209-218, 2005, ACM, 1-59593-167-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Peng Zhou, Soner Önder, Steve Carr 0001 |
Fast branch misprediction recovery in out-of-order superscalar processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 19th Annual International Conference on Supercomputing, ICS 2005, Cambridge, Massachusetts, USA, June 20-22, 2005, pp. 41-50, 2005, ACM, 1-59593-167-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
processor state, checkpoint, recovery, branch misprediction |
19 | Fei Sun, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha |
Synthesis of Application-Specific Heterogeneous Multiprocessor Architectures Using Extensible Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 18th International Conference on VLSI Design (VLSI Design 2005), with the 4th International Conference on Embedded Systems Design, 3-7 January 2005, Kolkata, India, pp. 551-556, 2005, IEEE Computer Society, 0-7695-2264-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Adrián Cristal, Oliverio J. Santana, Mateo Valero, José F. Martínez |
Toward kilo-instruction processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 1(4), pp. 389-417, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
multicheckpointing, instruction-level parallelism, Memory wall, kilo-instruction processors |
19 | Jin Lin, Wei-Chung Hsu, Pen-Chung Yew, Roy Dz-Ching Ju, Tin-Fook Ngai |
A Compiler Framework for Recovery Code Generation in General Speculative Optimizations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: 13th International Conference on Parallel Architectures and Compilation Techniques (PACT 2004), 29 September - 3 October 2004, Antibes Juan-les-Pins, France, pp. 17-28, 2004, IEEE Computer Society, 0-7695-2229-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
19 | Vlad-Mihai Panait, Amit Sasturkar, Weng-Fai Wong |
Static Identification of Delinquent Loads. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CGO ![In: 2nd IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2004), 20-24 March 2004, San Jose, CA, USA, pp. 303-314, 2004, IEEE Computer Society, 0-7695-2102-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
19 | Saeed Shamshiri, Hadi Esmaeilzadeh, Zainalabedin Navabi |
Test Instruction Set (TIS) for High Level Self-Testing of CPU Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 13th Asian Test Symposium (ATS 2004), 15-17 November 2004, Kenting, Taiwan, pp. 158-163, 2004, IEEE Computer Society, 0-7695-2235-1. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
19 | Alain Colmerauer |
On the Complexity of Universal Programs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MCU ![In: Machines, Computations, and Universality, 4th International Conference, MCU 2004, Saint Petersburg, Russia, September 21-24, 2004, Revised Selected Papers, pp. 18-35, 2004, Springer, 3-540-25261-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
19 | Gordon B. Bell, Mikko H. Lipasti |
Deconstructing commit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPASS ![In: 2004 IEEE International Symposium on Performance Analysis of Systems and Software, March 10-12, 2004, Austin, Texas, USA, Proceedings, pp. 68-77, 2004, IEEE Computer Society, 0-7803-8385-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
19 | Julie Heiser, Barbara Tversky |
Characterizing Diagrams Produced by Individuals and Dyads. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Spatial Cognition ![In: Spatial Cognition IV: Reasoning, Action, Interaction, International Conference Spatial Cognition 2004, Frauenchiemsee, Germany, October 11-13, 2004, RevisedSelected Papers, pp. 214-226, 2004, Springer, 3-540-25048-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
19 | Nikil Mehta, Brian Singer, R. Iris Bahar, Michael Leuchtenburg, Richard S. Weiss |
Fetch Halting on Critical Load Misses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 11-13 October 2004, San Jose, CA, USA, Proceedings, pp. 244-249, 2004, IEEE Computer Society, 0-7695-2231-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
19 | Yunheung Paek, Junsik Choi, Jinoo Joung, Junseo Lee, Seonwook Kim |
Exploiting Parallelism in Memory Operations for Code Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCPC ![In: Languages and Compilers for High Performance Computing, 17th International Workshop, LCPC 2004, West Lafayette, IN, USA, September 22-24, 2004, Revised Selected Papers, pp. 132-148, 2004, Springer, 3-540-28009-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
19 | Johann Großschädl, Erkay Savas |
Instruction Set Extensions for Fast Arithmetic in Finite Fields GF( p) and GF(2m). ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2004: 6th International Workshop Cambridge, MA, USA, August 11-13, 2004. Proceedings, pp. 133-147, 2004, Springer, 3-540-22666-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
19 | Steven Swanson, Luke K. McDowell, Michael M. Swift, Susan J. Eggers, Henry M. Levy |
An evaluation of speculative instruction execution on simultaneous multithreaded processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Comput. Syst. ![In: ACM Trans. Comput. Syst. 21(3), pp. 314-340, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
multiprocessors, multithreading, Instruction-level parallelism, speculation, thread-level parallelism, simultaneous multithreading |
19 | Norman Ramsey, Cristina Cifuentes |
A transformational approach to binary translation of delayed branches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Program. Lang. Syst. ![In: ACM Trans. Program. Lang. Syst. 25(2), pp. 210-224, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
program transformation, program analysis, Binary translation |
19 | Newton Cheung, Jörg Henkel, Sri Parameswaran |
Rapid Configuration and Instruction Selection for an ASIP: A Case Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany, pp. 10802-10809, 2003, IEEE Computer Society, 0-7695-1870-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
19 | Daniel Citron, Dror G. Feitelson |
"Look It Up" or "Do the Math": An Energy, Area, and Timing Analysis of Instruction Reuse and Memoization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACS ![In: Power-Aware Computer Systems, Third International Workshop, PACS 2003, SanDiego, CA, USA, December 1, 2003, Revised Papers, pp. 101-116, 2003, Springer, 3-540-24031-4. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
19 | Ying Chen, Resit Sendag, David J. Lilja |
Using Incorrect Speculation to Prefetch Data in a Concurrent Multithreaded Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 22-26 April 2003, Nice, France, CD-ROM/Abstracts Proceedings, pp. 76, 2003, IEEE Computer Society, 0-7695-1926-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
superthreaded architecture, wrong-thread executioin, wrong-path execution, wrong execution cache (WEC), data prefetch, multithreaded processor |
19 | Bengu Li, Rajiv Gupta 0001 |
Simple offset assignment in presence of subword data. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2003, San Jose, California, USA, October 30 - November 1, 2003, pp. 12-23, 2003, ACM, 1-58113-676-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
SWOA, subword data, SOA, storage assignment |
19 | Prasad Jayanti, Srdjan Petrovic |
Efficient and practical constructions of LL/SC variables. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PODC ![In: Proceedings of the Twenty-Second ACM Symposium on Principles of Distributed Computing, PODC 2003, Boston, Massachusetts, USA, July 13-16, 2003, pp. 285-294, 2003, ACM, 1-58113-708-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
19 | Zhijie Shi, Xiao Yang 0001, Ruby B. Lee |
Arbitrary Bit Permutations in One or Two Cycles. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 14th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2003), 24-26 June 2003, The Hague, The Netherlands, pp. 237-, 2003, IEEE Computer Society, 0-7695-1992-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
19 | Martin Burtscher, Benjamin G. Zorn |
Hybrid Load-Value Predictors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 51(7), pp. 759-774, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
load-value predictor, performance metrics, Value prediction, value locality, hybrid predictor |
19 | Xiaotong Zhuang, Santosh Pande, John S. Greenland Jr. |
A Framework for Parallelizing Load/Stores on Embedded Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: 2002 International Conference on Parallel Architectures and Compilation Techniques (PACT 2002), 22-25 September 2002, Charlottesville, VA, USA, pp. 68-79, 2002, IEEE Computer Society, 0-7695-1620-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
19 | Eric Tune, Dean M. Tullsen, Brad Calder |
Quantifying Instruction Criticality. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: 2002 International Conference on Parallel Architectures and Compilation Techniques (PACT 2002), 22-25 September 2002, Charlottesville, VA, USA, pp. 104-113, 2002, IEEE Computer Society, 0-7695-1620-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
19 | Mohamed M. Zahran, Manoj Franklin |
Return-Address Prediction in Speculative Multithreaded Environments. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPC ![In: High Performance Computing - HiPC 2002, 9th International Conference, Bangalore, India, December 18-21, 2002, Proceedings, pp. 609-619, 2002, Springer, 3-540-00303-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
19 | Dmitry Cheresiz, Ben H. H. Juurlink, Stamatis Vassiliadis, Harry A. G. Wijshoff |
Performance Scalability of Multimedia Instruction Set Extensions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par 2002, Parallel Processing, 8th International Euro-Par Conference Paderborn, Germany, August 27-30, 2002, Proceedings, pp. 849-860, 2002, Springer, 3-540-44049-6. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
19 | Joshua J. Yi, Resit Sendag, David J. Lilja |
Increasing Instruction-Level Parallelism with Instruction Precomputation (Research Note). ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par 2002, Parallel Processing, 8th International Euro-Par Conference Paderborn, Germany, August 27-30, 2002, Proceedings, pp. 481-485, 2002, Springer, 3-540-44049-6. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
19 | Youfeng Wu |
Efficient Discovery of Regular Stride Patterns in Irregular Programs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the 2002 ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), Berlin, Germany, June 17-19, 2002, pp. 210-221, 2002, ACM, 1-58113-463-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
integrated stride and frequency profiling, phased multi-strided loads, strongly single-strided loads, performance evaluation, data prefetching |
19 | Juan L. Aragón, José González 0002, Antonio González 0001, James E. Smith 0001 |
Dual path instruction processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 16th international conference on Supercomputing, ICS 2002, New York City, NY, USA, June 22-26, 2002, pp. 220-229, 2002, ACM, 1-58113-483-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
branch misprediction penalty, dual path processing, pre-scheduling, confidence estimation |
19 | Aart J. C. Bik, Milind Girkar, Paul M. Grey, Xinmin Tian |
Automatic Detection of Saturation and Clipping Idioms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCPC ![In: Languages and Compilers for Parallel Computing, 15th Workshop, LCPC 2002, College Park, MD, USA, July 25-27, 2002, Revised Papers, pp. 61-74, 2002, Springer, 3-540-30781-8. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
19 | Dan Ernst, Todd M. Austin |
Efficient Dynamic Scheduling Through Tag Elimination. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 29th International Symposium on Computer Architecture (ISCA 2002), 25-29 May 2002, Anchorage, AK, USA, pp. 37-46, 2002, IEEE Computer Society, 0-7695-1605-X. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
complexity-effective architecture, last-tag prediction, dynamic scheduling, low-power architecture |
19 | Alvin R. Lebeck, Tong Li 0003, Eric Rotenberg, Jinson Koppanalil, Jaidev P. Patwardhan |
A Large, Fast Instruction Window for Tolerating Cache Misses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 29th International Symposium on Computer Architecture (ISCA 2002), 25-29 May 2002, Anchorage, AK, USA, pp. 59-70, 2002, IEEE Computer Society, 0-7695-1605-X. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Cache Memory, Memory Latency, Latency Tolerance, Instruction Window |
19 | Nestor Rychtyckyj |
An Assessment of Machine Translation for Vehicle Assembly Process Planning at Ford Motor Company. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AMTA ![In: Machine Translation: From Research to Real Users, 5th Conference of the Association for Machine Translation in the Americas, AMTA 2002 Tiburon, CA, USA, October 6-12, 2002, Proceedings, pp. 207-215, 2002, Springer, 3-540-44282-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
19 | Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi |
Reducing the complexity of the register file in dynamic superscalar processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 34th Annual International Symposium on Microarchitecture, Austin, Texas, USA, December 1-5, 2001, pp. 237-248, 2001, ACM/IEEE Computer Society, 0-7695-1369-7. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
19 | Soner Önder, Rajiv Gupta 0001 |
Instruction Wake-Up in Wide Issue Superscalars. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par 2001: Parallel Processing, 7th International Euro-Par Conference Manchester, UK August 28-31, 2001, Proceedings, pp. 418-427, 2001, Springer, 3-540-42495-4. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
19 | Uma Mahadevan, Kevin Nomura, Roy Dz-Ching Ju, Rick Hank |
Applying Data Speculation in Modulo Scheduled Loops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: Proceedings of the 2000 International Conference on Parallel Architectures and Compilation Techniques (PACT'00), Philadelphia, Pennsylvania, USA, October 15-19, 2000, pp. 169-178, 2000, IEEE Computer Society, 0-7695-0622-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
19 | Junichi Hirase, Shinichi Yoshimura |
Faster processing for microprocessor functional ATPG. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 191-197, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
microprocessor functional ATPG, fault coverage improvement, short test pattern, processing speed increase, logic testing, integrated circuit testing, automatic test pattern generation, identification, test pattern generation, functional testing, microprocessor chips, instruction sets, instruction sets, microprocessor tests |
19 | Michaël F. Steehouder, Joyce Karreman, Nicole Ummelen |
Making sense of step-by-step procedures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGDOC ![In: Proceedings of IEEE Professional Communication Society International Professional Communication Conference and Proceedings of the 18th Annual ACM International Conference on Computer Documentation: Technology & Teamwork, Cambridge, Massachusetts, USA, September 24-27, 2000, pp. 463-475, 2000, IEEE, 0-7803-6431-7. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP BibTeX RDF |
|
19 | Jun Yang 0002, Rajiv Gupta 0001 |
Load Redundancy Removal through Instruction Reuse. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP ![In: Proceedings of the 2000 International Conference on Parallel Processing, ICPP 2000, Toronto, Canada, August 21-24, 2000, pp. 61-68, 2000, IEEE Computer Society, 0-7695-0768-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
19 | Soner Önder, Jun Xu, Rajiv Gupta 0001 |
Caching and Predicting Branch Sequences for Improved Fetch Effectiveness. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: Proceedings of the 1999 International Conference on Parallel Architectures and Compilation Techniques, Newport Beach, California, USA, October 12-16, 1999, pp. 294-302, 1999, IEEE Computer Society, 0-7695-0425-6. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
branch sequence prediction, sequence table, fetch bandwidth, speculative execution |
19 | Lea Hwang Lee, Jeff Scott, Bill Moyer, John Arends |
Low-Cost Branch Folding for Embedded Applications with Small Tight Loops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 32nd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 32, Haifa, Israel, November 16-18, 1999, pp. 103-111, 1999, ACM/IEEE Computer Society, 0-7695-0437-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
19 | Li-San Li, Huang-Zhen Chun |
Lookahead Cache with Instruction Processing Unit for Filling Memory Gap. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 25th EUROMICRO '99 Conference, Informatics: Theory and Practice for the New Millenium, 8-10 September 1999, Milan, Italy, pp. 1228-1231, 1999, IEEE Computer Society, 0-7695-0321-7. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Memory Gap, Lookahead Cache, Instruction Processing Unit |
19 | Brad Calder, Glenn Reinman, Dean M. Tullsen |
Selective Value Prediction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: Proceedings of the 26th Annual International Symposium on Computer Architecture, ISCA 1999, Atlanta, Georgia, USA, May 2-4, 1999, pp. 64-74, 1999, IEEE Computer Society, 0-7695-0170-2. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
19 | S. Subramanya Sastry, Subbarao Palacharla, James E. Smith 0001 |
Exploiting Idle Floating-Point Resources for Integer Execution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the ACM SIGPLAN '98 Conference on Programming Language Design and Implementation (PLDI), Montreal, Canada, June 17-19, 1998, pp. 118-129, 1998, ACM, 0-89791-987-4. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
19 | Sanjay J. Patel, Marius Evers, Yale N. Patt |
Improving Trace Cache Effectiveness with Branch Promotion and Trace Packing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: Proceedings of the 25th Annual International Symposium on Computer Architecture, ISCA 1998, Barcelona, Spain, June 27 - July 1, 1998, pp. 262-271, 1998, IEEE Computer Society, 0-8186-8491-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
19 | Keith D. Cooper, Timothy J. Harvey |
Compiler-Controlled Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: ASPLOS-VIII Proceedings of the 8th International Conference on Architectural Support for Programming Languages and Operating Systems, San Jose, California, USA, October 3-7, 1998., pp. 2-11, 1998, ACM Press, 1-58113-107-0. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
19 | Chao-ying Fu, Matthew D. Jennings, Sergei Y. Larin, Thomas M. Conte |
Value Speculation Scheduling for High Performance Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: ASPLOS-VIII Proceedings of the 8th International Conference on Architectural Support for Programming Languages and Operating Systems, San Jose, California, USA, October 3-7, 1998., pp. 262-271, 1998, ACM Press, 1-58113-107-0. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
VLIW instruction schedulings, instruction level parallelism, value prediction, value speculation |
19 | Corinna G. Lee, Derek J. DeVries |
Initial Results on the Performance and Cost of Vector Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the Thirtieth Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 30, Research Triangle Park, North Carolina, USA, December 1-3, 1997, pp. 171-182, 1997, ACM/IEEE Computer Society, 0-8186-7977-8. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
19 | Steven Wallace, Nader Bagherzadeh |
Multiple Branch and Block Prediction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: Proceedings of the 3rd IEEE Symposium on High-Performance Computer Architecture (HPCA '97), San Antonio, Texas, USA, February 1-5, 1997, pp. 94-103, 1997, IEEE Computer Society, 0-8186-7764-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
19 | Subbarao Palacharla, Norman P. Jouppi, James E. Smith 0001 |
Complexity-Effective Superscalar Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: Proceedings of the 24th International Symposium on Computer Architecture, Denver, Colorado, USA, June 2-4, 1997, pp. 206-218, 1997, ACM, 0-89791-901-7. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
19 | Scott A. Mahlke, Balas K. Natarajan |
Compiler Synthesized Dynamic Branch Prediction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 29, Paris, France, December 2-4, 1996, pp. 153-164, 1996, ACM/IEEE Computer Society, 0-8186-7641-8. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
profile information, pipelined processor, compiler analysis, dynamic branch prediction, branch instruction |
19 | Yiannakis Sazeides, Stamatis Vassiliadis, James E. Smith 0001 |
The Performance Potential of Data Dependence Speculation & Collapsing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 29, Paris, France, December 2-4, 1996, pp. 238-247, 1996, ACM/IEEE Computer Society, 0-8186-7641-8. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
address generation-load dependences, address prediction rate, base instruction level parallel machine, dependence collapsing, performance potential, true data dependences, parallel programming, trace-driven simulation, data dependence speculation, address prediction |
19 | Ulrich Sigmund, Theo Ungerer |
Identifying Bottlenecks in a Multithreaded Superscalar Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par, Vol. II ![In: Euro-Par '96 Parallel Processing, Second International Euro-Par Conference, Lyon, France, August 26-29, 1996, Proceedings, Volume II, pp. 797-800, 1996, Springer, 3-540-61627-6. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
19 | Bonnie L. Webber |
Instructing Animated Agents: Viewing Language in Behavioral Terms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Multimodal Human-Computer Communication ![In: Multimodal Human-Computer Communication, Systems, Techniques, and Experiments, pp. 89-100, 1995, Springer, 3-540-64380-X. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
19 | Hideki Ando, Chikako Nakanishi, Tetsuya Hara, Masao Nakaya |
Unconstrained Speculative Execution with Predicated State Buffering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: Proceedings of the 22nd Annual International Symposium on Computer Architecture, ISCA '95, Santa Margherita Ligure, Italy, June 22-24, 1995, pp. 126-137, 1995, ACM, 0-89791-698-0. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
MIPS R3000 |
19 | Gary S. Tyson |
The effects of predicated execution on branch prediction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 27th Annual International Symposium on Microarchitecture, San Jose, California, USA, November 30 - December 2, 1994, pp. 196-206, 1994, ACM / IEEE Computer Society, 0-89791-707-3. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
HP-RISC, Pentium, high-performance, ATOM, branch prediction, predication, PowerPC, Alpha |
19 | Mauricio J. Serrano, Wayne Yamamoto, Roger C. Wood, Mario Nemirovsky |
A Model for Performance Estimation in a Multistreamed Superscalar Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Computer Performance Evaluation ![In: Computer Performance Evaluation, Modeling Techniques and Tools, 7th International Conference, Vienna, Austria, May 3-6, 1994, Proceedings, pp. 213-230, 1994, Springer, 3-540-58021-2. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
19 | Andreas Krall, Thomas Berger |
Fast Prolog with VAM1p based Prolog Compiler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLILP ![In: Programming Language Implementation and Logic Programming, 4th International Symposium, PLILP'92, Leuven, Belgium, August 26-28, 1992, Proceedings, pp. 245-259, 1992, Springer, 3-540-55844-6. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
19 | M. Chastain, G. Gostin, James E. Mankovich, Steven J. Wallach |
The convex C240 architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SC ![In: Proceedings Supercomputing '88, Orlando, FL, USA, November 12-17, 1988, pp. 321-329, 1988, IEEE Computer Society, 0-8186-0882-X. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
19 | Jim Gray 0001 |
A View of Database System Performance Measures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMETRICS ![In: Proceedings of the 1987 ACM SIGMETRICS conference on Measurement and modeling of computer systems, Banff, Alberta, Canada, May 11-14, 1987, pp. 3-4, 1987, ACM, 0-89791-225-X. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
19 | Vishv M. Malhotra, Sanjeev Kumar |
Automatic Retargetable Code Generation: A New Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FSTTCS ![In: Foundations of Software Technology and Theoretical Computer Science, Sixth Conference, New Delhi, India, December 18-20, 1986, Proceedings, pp. 57-80, 1986, Springer, 3-540-17179-7. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
|
19 | Robert R. Kessler |
Peep: an architectural description driven peephole optimizer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGPLAN Symposium on Compiler Construction ![In: Proceedings of the 1984 SIGPLAN Symposium on Compiler Construction, Montreal, Canada, June 17-22, 1984, pp. 106-110, 1984, ACM, 0-89791-139-3. The full citation details ...](Pics/full.jpeg) |
1984 |
DBLP DOI BibTeX RDF |
|
19 | Jack W. Davidson, Christopher W. Fraser |
The Design and Application of a Retargetable Peephole Optimizer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Program. Lang. Syst. ![In: ACM Trans. Program. Lang. Syst. 2(2), pp. 191-202, 1980. The full citation details ...](Pics/full.jpeg) |
1980 |
DBLP DOI BibTeX RDF |
|
18 | Zhanpeng Jin, Richard Neil Pittman, Alessandro Forin |
Reconfigurable custom floating-point instructions (abstract only). ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, FPGA 2010, Monterey, California, USA, February 21-23, 2010, pp. 287, 2010, ACM, 978-1-60558-911-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
emips, reconfigurable, extension, floating-point, partial reconfiguration |
18 | Garo Bournoutian, Alex Orailoglu |
Reducing impact of cache miss stalls in embedded systems by extracting guaranteed independent instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2009 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2009, Grenoble, France, October 11-16, 2009, pp. 117-126, 2009, ACM. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
compiler assisted hardware, pipeline stalls, embedded processors, data cache |
18 | Kevin J. M. Martin, Christophe Wolinski, Krzysztof Kuchcinski, Antoine Floch, François Charot |
Constraint-Driven Instructions Selection and Application Scheduling in the DURASE system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 20th IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2009, July 7-9, 2009, Boston, MA, USA, pp. 145-152, 2009, IEEE Computer Society, 978-0-7695-3732-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
18 | Yohei Kurata, Hui Shi 0001 |
Interpreting Motion Expressions in Route Instructions Using Two Projection-Based Spatial Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
KI ![In: KI 2008: Advances in Artificial Intelligence, 31st Annual German Conference on AI, KI 2008, Kaiserslautern, Germany, September 23-26, 2008. Proceedings, pp. 258-266, 2008, Springer, 978-3-540-85844-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Lars Bauer, Muhammad Shafique 0001, Jörg Henkel |
A computation- and communication- infrastructure for modular special instructions in a dynamically reconfigurable processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2008, International Conference on Field Programmable Logic and Applications, Heidelberg, Germany, 8-10 September 2008, pp. 203-208, 2008, IEEE, 978-1-4244-1961-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Paolo Bonzini, Giovanni Ansaloni, Laura Pozzi |
Compiling custom instructions onto expression-grained reconfigurable architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2008 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2008, Atlanta, GA, USA, October 19-24, 2008, pp. 51-60, 2008, ACM. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
horizontal microprogramming, compilers, instruction set extensions, coarse-grained reconfigurable architectures, data-flow architectures |
18 | Shijian Zhang, Weiwu Hu |
Fetching Primary and Redundant Instructions in Turn for a Fault-Tolerant Embedded Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PRDC ![In: 14th IEEE Pacific Rim International Symposium on Dependable Computing, PRDC 2008, 15-17 December 2008, Taipei, Taiwan, pp. 1-8, 2008, IEEE Computer Society, 978-0-7695-3448-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Todd T. Hahn, Eric Stotzer, Dineel Sule, Mike Asal |
Compilation Strategies for Reducing Code Size on a VLIW Processor with Variable Length Instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPEAC ![In: High Performance Embedded Architectures and Compilers, Third International Conference, HiPEAC 2008, Göteborg, Sweden, January 27-29, 2008, Proceedings, pp. 147-160, 2008, Springer, 978-3-540-77559-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Xiaoyong Chen, Douglas L. Maskell, Yang Sun |
Fast Identification of Custom Instructions for Extensible Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(2), pp. 359-368, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
18 | Hamid Noori, Farhad Mehdipour, Kazuaki J. Murakami, Koji Inoue, Maziar Goudarzi |
Interactive presentation: Generating and executing multi-exit custom instructions for an adaptive extensible processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 325-330, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
18 | Anne Dickinson |
Is the shortcut the quickest way to go?: translating instructions for keyboard navigation and other stories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITiCSE ![In: Proceedings of the 12th Annual SIGCSE Conference on Innovation and Technology in Computer Science Education, ITiCSE 2007, Dundee, Scotland, UK, June 25-27, 2007, pp. 358, 2007, ACM, 978-1-59593-610-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
keyboard shortcuts, university student, e-learning, information technology, disabilities, online learning, stories, braille |
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