Search results for "instructions"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
19	Hans Vandierendonck, Philippe Manet, Thibault Delavallee, Igor Loiselle, Jean-Didier Legat	By-passing the out-of-order execution pipeline to increase energy-efficiency.	Conf. Computing Frontiers	2007	DBLP DOI BibTeX RDF	instruction wake-up, energy-efficiency, instruction scheduling, out-of-order execution
19	Gongqiong Li, Zhaolin Li	Optimized design of a double-precision floating-point multiply-add-dused unit for data dependence.	ICCD	2007	DBLP DOI BibTeX RDF
19	Andhi Janapsatya, Aleksandar Ignjatovic, Sri Parameswaran	Exploiting statistical information for implementation of instruction scratchpad memory in embedded system.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
19	Xianfeng Li, Abhik Roychoudhury, Tulika Mitra	Modeling out-of-order processors for WCET analysis.	Real Time Syst.	2006	DBLP DOI BibTeX RDF	Worst-case execution time (WCET) analysis, Out-of-order superscalar processor, Branch prediction, Instruction cache
19	Asadollah Shahbahrami, Ben H. H. Juurlink, Demid Borodin, Stamatis Vassiliadis	Avoiding Conversion and Rearrangement Overhead in SIMD Architectures.	Int. J. Parallel Program.	2006	DBLP DOI BibTeX RDF	Embedded media processors, multimedia kernels, register file, subword parallelism
19	Juan L. Aragón, José M. González, Antonio González 0001	Control Speculation for Energy-Efficient Next-Generation Superscalar Processors.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	low-power design, processor architecture, energy-aware systems, Control speculation
19	Jin Lin, Wei-Chung Hsu, Pen-Chung Yew, Roy Dz-Ching Ju, Tin-Fook Ngai	Recovery code generation for general speculative optimizations.	ACM Trans. Archit. Code Optim.	2006	DBLP DOI BibTeX RDF	Recovery code, multi-level data speculation, speculative SSA form
19	Olivier Rochecouste, Gilles Pokam, André Seznec	A case for a complexity-effective, width-partitioned microarchitecture.	ACM Trans. Archit. Code Optim.	2006	DBLP DOI BibTeX RDF	Power analysis
19	Xiaotong Zhuang, Santosh Pande	Parallelizing load/stores on dual-bank memory embedded processors.	ACM Trans. Embed. Comput. Syst.	2006	DBLP DOI BibTeX RDF	memory bank allocation, parallel load/stores, profile driven optimization, DSP architectures
19	Wu-An Kuo, TingTing Hwang, Allen C.-H. Wu	Decomposition of instruction decoders for low-power designs.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	instruction decoder, Low power
19	Chengmo Yang, Alex Orailoglu	Power-efficient instruction delivery through trace reuse.	PACT	2006	DBLP DOI BibTeX RDF	adaptive processor, low-power design, instruction delivery
19	Robert G. Dimond, Oskar Mencer, Wayne Luk	Automating processor customisation: optimised memory access and resource sharing.	DATE	2006	DBLP DOI BibTeX RDF
19	Hyesoon Kim, José A. Joao, Onur Mutlu, Yale N. Patt	Diverge-Merge Processor (DMP): Dynamic Predicated Execution of Complex Control-Flow Graphs Based on Frequently Executed Paths.	MICRO	2006	DBLP DOI BibTeX RDF
19	Christopher Lupo, Kent D. Wilken	Post Register Allocation Spill Code Optimization.	CGO	2006	DBLP DOI BibTeX RDF
19	Sumeet Kumar, Aneesh Aggarwal	Reducing resource redundancy for concurrent error detection techniques in high performance microprocessors.	HPCA	2006	DBLP DOI BibTeX RDF
19	Gang Ren 0002, Peng Wu 0001, David A. Padua	Optimizing data permutations for SIMD devices.	PLDI	2006	DBLP DOI BibTeX RDF	SIMD compilation, data permutation, optimization
19	Hui Wu 0001, Joxan Jaffar, Jingling Xue	Instruction Scheduling with Release Times and Deadlines on ILP Processors.	RTCSA	2006	DBLP DOI BibTeX RDF
19	Jack Whitham, Neil C. Audsley	MCGREP - A Predictable Architecture for Embedded Real-Time Systems.	RTSS	2006	DBLP DOI BibTeX RDF
19	Tanausú Ramírez, Alex Pajuelo, Oliverio J. Santana, Mateo Valero	Kilo-instruction processors, runahead and prefetching.	Conf. Computing Frontiers	2006	DBLP DOI BibTeX RDF	runahead, prefetching, speculative execution, memory wall, Kilo-instruction processors
19	H. C. Wang, C. K. Yuen	A general framework to build new CPUs by mapping abstract machine code to instruction level parallel execution hardware.	SIGARCH Comput. Archit. News	2005	DBLP DOI BibTeX RDF
19	Nicholas Andrew Bradley, Mark D. Dunlop	An Experimental Investigation into Wayfinding Directions for Visually Impaired People.	Pers. Ubiquitous Comput.	2005	DBLP DOI BibTeX RDF
19	Resit Sendag, Ying Chen, David J. Lilja	The Impact of Incorrectly Speculated Memory Operations in a Multithreaded Architecture.	IEEE Trans. Parallel Distributed Syst.	2005	DBLP DOI BibTeX RDF	mispredicted loads, wrong execution, wrong execution cache, prefetching, Speculation, multithreaded architecture
19	Changpeng Fang, Steve Carr 0001, Soner Önder, Zhenlin Wang	Instruction Based Memory Distance Analysis and its Application.	IEEE PACT	2005	DBLP DOI BibTeX RDF
19	Dinesh C. Suresh, Walid A. Najjar, Jun Yang 0002	Power Efficient Instruction Caches for Embedded Systems.	SAMOS	2005	DBLP DOI BibTeX RDF
19	Newton Cheung, Sri Parameswaran, Jörg Henkel	Battery-aware instruction generation for embedded processors.	ASP-DAC	2005	DBLP DOI BibTeX RDF
19	Alex Pajuelo, Antonio González 0001, Mateo Valero	Control-Flow Independence Reuse via Dynamic Vectorization.	IPDPS	2005	DBLP DOI BibTeX RDF
19	Madhavi Gopal Valluri, Lizy Kurian John, Kathryn S. McKinley	Low-power, low-complexity instruction issue using compiler assistance.	ICS	2005	DBLP DOI BibTeX RDF
19	Peng Zhou, Soner Önder, Steve Carr 0001	Fast branch misprediction recovery in out-of-order superscalar processors.	ICS	2005	DBLP DOI BibTeX RDF	processor state, checkpoint, recovery, branch misprediction
19	Fei Sun, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha	Synthesis of Application-Specific Heterogeneous Multiprocessor Architectures Using Extensible Processors.	VLSI Design	2005	DBLP DOI BibTeX RDF
19	Adrián Cristal, Oliverio J. Santana, Mateo Valero, José F. Martínez	Toward kilo-instruction processors.	ACM Trans. Archit. Code Optim.	2004	DBLP DOI BibTeX RDF	multicheckpointing, instruction-level parallelism, Memory wall, kilo-instruction processors
19	Jin Lin, Wei-Chung Hsu, Pen-Chung Yew, Roy Dz-Ching Ju, Tin-Fook Ngai	A Compiler Framework for Recovery Code Generation in General Speculative Optimizations.	IEEE PACT	2004	DBLP DOI BibTeX RDF
19	Vlad-Mihai Panait, Amit Sasturkar, Weng-Fai Wong	Static Identification of Delinquent Loads.	CGO	2004	DBLP DOI BibTeX RDF
19	Saeed Shamshiri, Hadi Esmaeilzadeh, Zainalabedin Navabi	Test Instruction Set (TIS) for High Level Self-Testing of CPU Cores.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
19	Alain Colmerauer	On the Complexity of Universal Programs.	MCU	2004	DBLP DOI BibTeX RDF
19	Gordon B. Bell, Mikko H. Lipasti	Deconstructing commit.	ISPASS	2004	DBLP DOI BibTeX RDF
19	Julie Heiser, Barbara Tversky	Characterizing Diagrams Produced by Individuals and Dyads.	Spatial Cognition	2004	DBLP DOI BibTeX RDF
19	Nikil Mehta, Brian Singer, R. Iris Bahar, Michael Leuchtenburg, Richard S. Weiss	Fetch Halting on Critical Load Misses.	ICCD	2004	DBLP DOI BibTeX RDF
19	Yunheung Paek, Junsik Choi, Jinoo Joung, Junseo Lee, Seonwook Kim	Exploiting Parallelism in Memory Operations for Code Optimization.	LCPC	2004	DBLP DOI BibTeX RDF
19	Johann Großschädl, Erkay Savas	Instruction Set Extensions for Fast Arithmetic in Finite Fields GF( p) and GF(2m).	CHES	2004	DBLP DOI BibTeX RDF
19	Steven Swanson, Luke K. McDowell, Michael M. Swift, Susan J. Eggers, Henry M. Levy	An evaluation of speculative instruction execution on simultaneous multithreaded processors.	ACM Trans. Comput. Syst.	2003	DBLP DOI BibTeX RDF	multiprocessors, multithreading, Instruction-level parallelism, speculation, thread-level parallelism, simultaneous multithreading
19	Norman Ramsey, Cristina Cifuentes	A transformational approach to binary translation of delayed branches.	ACM Trans. Program. Lang. Syst.	2003	DBLP DOI BibTeX RDF	program transformation, program analysis, Binary translation
19	Newton Cheung, Jörg Henkel, Sri Parameswaran	Rapid Configuration and Instruction Selection for an ASIP: A Case Study.	DATE	2003	DBLP DOI BibTeX RDF
19	Daniel Citron, Dror G. Feitelson	"Look It Up" or "Do the Math": An Energy, Area, and Timing Analysis of Instruction Reuse and Memoization.	PACS	2003	DBLP DOI BibTeX RDF
19	Ying Chen, Resit Sendag, David J. Lilja	Using Incorrect Speculation to Prefetch Data in a Concurrent Multithreaded Processor.	IPDPS	2003	DBLP DOI BibTeX RDF	superthreaded architecture, wrong-thread executioin, wrong-path execution, wrong execution cache (WEC), data prefetch, multithreaded processor
19	Bengu Li, Rajiv Gupta 0001	Simple offset assignment in presence of subword data.	CASES	2003	DBLP DOI BibTeX RDF	SWOA, subword data, SOA, storage assignment
19	Prasad Jayanti, Srdjan Petrovic	Efficient and practical constructions of LL/SC variables.	PODC	2003	DBLP DOI BibTeX RDF
19	Zhijie Shi, Xiao Yang 0001, Ruby B. Lee	Arbitrary Bit Permutations in One or Two Cycles.	ASAP	2003	DBLP DOI BibTeX RDF
19	Martin Burtscher, Benjamin G. Zorn	Hybrid Load-Value Predictors.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	load-value predictor, performance metrics, Value prediction, value locality, hybrid predictor
19	Xiaotong Zhuang, Santosh Pande, John S. Greenland Jr.	A Framework for Parallelizing Load/Stores on Embedded Processors.	IEEE PACT	2002	DBLP DOI BibTeX RDF
19	Eric Tune, Dean M. Tullsen, Brad Calder	Quantifying Instruction Criticality.	IEEE PACT	2002	DBLP DOI BibTeX RDF
19	Mohamed M. Zahran, Manoj Franklin	Return-Address Prediction in Speculative Multithreaded Environments.	HiPC	2002	DBLP DOI BibTeX RDF
19	Dmitry Cheresiz, Ben H. H. Juurlink, Stamatis Vassiliadis, Harry A. G. Wijshoff	Performance Scalability of Multimedia Instruction Set Extensions.	Euro-Par	2002	DBLP DOI BibTeX RDF
19	Joshua J. Yi, Resit Sendag, David J. Lilja	Increasing Instruction-Level Parallelism with Instruction Precomputation (Research Note).	Euro-Par	2002	DBLP DOI BibTeX RDF
19	Youfeng Wu	Efficient Discovery of Regular Stride Patterns in Irregular Programs.	PLDI	2002	DBLP DOI BibTeX RDF	integrated stride and frequency profiling, phased multi-strided loads, strongly single-strided loads, performance evaluation, data prefetching
19	Juan L. Aragón, José González 0002, Antonio González 0001, James E. Smith 0001	Dual path instruction processing.	ICS	2002	DBLP DOI BibTeX RDF	branch misprediction penalty, dual path processing, pre-scheduling, confidence estimation
19	Aart J. C. Bik, Milind Girkar, Paul M. Grey, Xinmin Tian	Automatic Detection of Saturation and Clipping Idioms.	LCPC	2002	DBLP DOI BibTeX RDF
19	Dan Ernst, Todd M. Austin	Efficient Dynamic Scheduling Through Tag Elimination.	ISCA	2002	DBLP DOI BibTeX RDF	complexity-effective architecture, last-tag prediction, dynamic scheduling, low-power architecture
19	Alvin R. Lebeck, Tong Li 0003, Eric Rotenberg, Jinson Koppanalil, Jaidev P. Patwardhan	A Large, Fast Instruction Window for Tolerating Cache Misses.	ISCA	2002	DBLP DOI BibTeX RDF	Cache Memory, Memory Latency, Latency Tolerance, Instruction Window
19	Nestor Rychtyckyj	An Assessment of Machine Translation for Vehicle Assembly Process Planning at Ford Motor Company.	AMTA	2002	DBLP DOI BibTeX RDF
19	Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi	Reducing the complexity of the register file in dynamic superscalar processors.	MICRO	2001	DBLP DOI BibTeX RDF
19	Soner Önder, Rajiv Gupta 0001	Instruction Wake-Up in Wide Issue Superscalars.	Euro-Par	2001	DBLP DOI BibTeX RDF
19	Uma Mahadevan, Kevin Nomura, Roy Dz-Ching Ju, Rick Hank	Applying Data Speculation in Modulo Scheduled Loops.	IEEE PACT	2000	DBLP DOI BibTeX RDF
19	Junichi Hirase, Shinichi Yoshimura	Faster processing for microprocessor functional ATPG.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	microprocessor functional ATPG, fault coverage improvement, short test pattern, processing speed increase, logic testing, integrated circuit testing, automatic test pattern generation, identification, test pattern generation, functional testing, microprocessor chips, instruction sets, instruction sets, microprocessor tests
19	Michaël F. Steehouder, Joyce Karreman, Nicole Ummelen	Making sense of step-by-step procedures.	SIGDOC	2000	DBLP BibTeX RDF
19	Jun Yang 0002, Rajiv Gupta 0001	Load Redundancy Removal through Instruction Reuse.	ICPP	2000	DBLP DOI BibTeX RDF
19	Soner Önder, Jun Xu, Rajiv Gupta 0001	Caching and Predicting Branch Sequences for Improved Fetch Effectiveness.	IEEE PACT	1999	DBLP DOI BibTeX RDF	branch sequence prediction, sequence table, fetch bandwidth, speculative execution
19	Lea Hwang Lee, Jeff Scott, Bill Moyer, John Arends	Low-Cost Branch Folding for Embedded Applications with Small Tight Loops.	MICRO	1999	DBLP DOI BibTeX RDF
19	Li-San Li, Huang-Zhen Chun	Lookahead Cache with Instruction Processing Unit for Filling Memory Gap.	EUROMICRO	1999	DBLP DOI BibTeX RDF	Memory Gap, Lookahead Cache, Instruction Processing Unit
19	Brad Calder, Glenn Reinman, Dean M. Tullsen	Selective Value Prediction.	ISCA	1999	DBLP DOI BibTeX RDF
19	S. Subramanya Sastry, Subbarao Palacharla, James E. Smith 0001	Exploiting Idle Floating-Point Resources for Integer Execution.	PLDI	1998	DBLP DOI BibTeX RDF
19	Sanjay J. Patel, Marius Evers, Yale N. Patt	Improving Trace Cache Effectiveness with Branch Promotion and Trace Packing.	ISCA	1998	DBLP DOI BibTeX RDF
19	Keith D. Cooper, Timothy J. Harvey	Compiler-Controlled Memory.	ASPLOS	1998	DBLP DOI BibTeX RDF
19	Chao-ying Fu, Matthew D. Jennings, Sergei Y. Larin, Thomas M. Conte	Value Speculation Scheduling for High Performance Processors.	ASPLOS	1998	DBLP DOI BibTeX RDF	VLIW instruction schedulings, instruction level parallelism, value prediction, value speculation
19	Corinna G. Lee, Derek J. DeVries	Initial Results on the Performance and Cost of Vector Microprocessors.	MICRO	1997	DBLP DOI BibTeX RDF
19	Steven Wallace, Nader Bagherzadeh	Multiple Branch and Block Prediction.	HPCA	1997	DBLP DOI BibTeX RDF
19	Subbarao Palacharla, Norman P. Jouppi, James E. Smith 0001	Complexity-Effective Superscalar Processors.	ISCA	1997	DBLP DOI BibTeX RDF
19	Scott A. Mahlke, Balas K. Natarajan	Compiler Synthesized Dynamic Branch Prediction.	MICRO	1996	DBLP DOI BibTeX RDF	profile information, pipelined processor, compiler analysis, dynamic branch prediction, branch instruction
19	Yiannakis Sazeides, Stamatis Vassiliadis, James E. Smith 0001	The Performance Potential of Data Dependence Speculation & Collapsing.	MICRO	1996	DBLP DOI BibTeX RDF	address generation-load dependences, address prediction rate, base instruction level parallel machine, dependence collapsing, performance potential, true data dependences, parallel programming, trace-driven simulation, data dependence speculation, address prediction
19	Ulrich Sigmund, Theo Ungerer	Identifying Bottlenecks in a Multithreaded Superscalar Microprocessor.	Euro-Par, Vol. II	1996	DBLP DOI BibTeX RDF
19	Bonnie L. Webber	Instructing Animated Agents: Viewing Language in Behavioral Terms.	Multimodal Human-Computer Communication	1995	DBLP DOI BibTeX RDF
19	Hideki Ando, Chikako Nakanishi, Tetsuya Hara, Masao Nakaya	Unconstrained Speculative Execution with Predicated State Buffering.	ISCA	1995	DBLP DOI BibTeX RDF	MIPS R3000
19	Gary S. Tyson	The effects of predicated execution on branch prediction.	MICRO	1994	DBLP DOI BibTeX RDF	HP-RISC, Pentium, high-performance, ATOM, branch prediction, predication, PowerPC, Alpha
19	Mauricio J. Serrano, Wayne Yamamoto, Roger C. Wood, Mario Nemirovsky	A Model for Performance Estimation in a Multistreamed Superscalar Processor.	Computer Performance Evaluation	1994	DBLP DOI BibTeX RDF
19	Andreas Krall, Thomas Berger	Fast Prolog with VAM1p based Prolog Compiler.	PLILP	1992	DBLP DOI BibTeX RDF
19	M. Chastain, G. Gostin, James E. Mankovich, Steven J. Wallach	The convex C240 architecture.	SC	1988	DBLP DOI BibTeX RDF
19	Jim Gray 0001	A View of Database System Performance Measures.	SIGMETRICS	1987	DBLP DOI BibTeX RDF
19	Vishv M. Malhotra, Sanjeev Kumar	Automatic Retargetable Code Generation: A New Technique.	FSTTCS	1986	DBLP DOI BibTeX RDF
19	Robert R. Kessler	Peep: an architectural description driven peephole optimizer.	SIGPLAN Symposium on Compiler Construction	1984	DBLP DOI BibTeX RDF
19	Jack W. Davidson, Christopher W. Fraser	The Design and Application of a Retargetable Peephole Optimizer.	ACM Trans. Program. Lang. Syst.	1980	DBLP DOI BibTeX RDF
18	Zhanpeng Jin, Richard Neil Pittman, Alessandro Forin	Reconfigurable custom floating-point instructions (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	emips, reconfigurable, extension, floating-point, partial reconfiguration
18	Garo Bournoutian, Alex Orailoglu	Reducing impact of cache miss stalls in embedded systems by extracting guaranteed independent instructions.	CASES	2009	DBLP DOI BibTeX RDF	compiler assisted hardware, pipeline stalls, embedded processors, data cache
18	Kevin J. M. Martin, Christophe Wolinski, Krzysztof Kuchcinski, Antoine Floch, François Charot	Constraint-Driven Instructions Selection and Application Scheduling in the DURASE system.	ASAP	2009	DBLP DOI BibTeX RDF
18	Yohei Kurata, Hui Shi 0001	Interpreting Motion Expressions in Route Instructions Using Two Projection-Based Spatial Models.	KI	2008	DBLP DOI BibTeX RDF
18	Lars Bauer, Muhammad Shafique 0001, Jörg Henkel	A computation- and communication- infrastructure for modular special instructions in a dynamically reconfigurable processor.	FPL	2008	DBLP DOI BibTeX RDF
18	Paolo Bonzini, Giovanni Ansaloni, Laura Pozzi	Compiling custom instructions onto expression-grained reconfigurable architectures.	CASES	2008	DBLP DOI BibTeX RDF	horizontal microprogramming, compilers, instruction set extensions, coarse-grained reconfigurable architectures, data-flow architectures
18	Shijian Zhang, Weiwu Hu	Fetching Primary and Redundant Instructions in Turn for a Fault-Tolerant Embedded Microprocessor.	PRDC	2008	DBLP DOI BibTeX RDF
18	Todd T. Hahn, Eric Stotzer, Dineel Sule, Mike Asal	Compilation Strategies for Reducing Code Size on a VLIW Processor with Variable Length Instructions.	HiPEAC	2008	DBLP DOI BibTeX RDF
18	Xiaoyong Chen, Douglas L. Maskell, Yang Sun	Fast Identification of Custom Instructions for Extensible Processors.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
18	Hamid Noori, Farhad Mehdipour, Kazuaki J. Murakami, Koji Inoue, Maziar Goudarzi	Interactive presentation: Generating and executing multi-exit custom instructions for an adaptive extensible processor.	DATE	2007	DBLP DOI BibTeX RDF
18	Anne Dickinson	Is the shortcut the quickest way to go?: translating instructions for keyboard navigation and other stories.	ITiCSE	2007	DBLP DOI BibTeX RDF	keyboard shortcuts, university student, e-learning, information technology, disabilities, online learning, stories, braille