Search results for "multiplexers"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
12	Kuo-Hsing Cheng, Shun-Wen Cheng, Che-Yu Liao	64-bit Low Threshold Voltage High-Speed Conditional Carry Adder by Complementary Pass-Transistor Logi.	ISVLSI	2004	DBLP DOI BibTeX RDF	CPL, conditional sum adder, low-threshold voltage, differential-end, VLSI design, low-voltage
12	Erik Chmelar	Subframe multiplexing for FPGA manufacturing test configuration.	FPGA	2004	DBLP DOI BibTeX RDF
12	Anatole D. Ruslanov, Jeremy R. Johnson	An FPGA implementation of bene permutation networks.	FPGA	2004	DBLP DOI BibTeX RDF
12	Deming Chen, Jason Cong	Register binding and port assignment for multiplexer optimization.	ASP-DAC	2004	DBLP DOI BibTeX RDF
12	Il-soo Lee, Yong Min Hur, Tony Ambler	The Efficient Multiple Scan Chain Architecture Reducing Power Dissipation and Test Time.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
12	Jianhui Xing, Hong Wang, Shiyuan Yang	Constructing Transparency Paths for IP Cores Using Greedy Searching Strategy.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
12	Oliver A. Pfänder, Roland Hacker, Hans-Jörg Pfleiderer	A Multiplexer-Based Concept for Reconfigurable Multiplier Arrays.	FPL	2004	DBLP DOI BibTeX RDF
12	Kanishka Lahiri, Anand Raghunathan	Power analysis of system-level on-chip communication architectures.	CODES+ISSS	2004	DBLP DOI BibTeX RDF	system-on-chip, network-on-chip, low-power design, power analysis, communication architectures
12	Shao-Hua Lee, Jeen-Shing Wang	Design of a neuro-fuzzy chip using adaptive multimode approaches for an intelligent car-backing system.	SMC (4)	2004	DBLP DOI BibTeX RDF
12	Leah Epstein, Asaf Levin	Better Bounds for Minimizing SONET ADMs.	WAOA	2004	DBLP DOI BibTeX RDF
12	Edward J. McCluskey, Ahmad A. Al-Yamani, Chien-Mo James Li, Chao-Wen Tseng, Erik H. Volkerink, François-Fabien Ferhani, Edward Li, Subhasish Mitra	ELF-Murphy Data on Defects and Test Sets.	VTS	2004	DBLP DOI BibTeX RDF
12	David C. Keezer, Dany Minier, F. Binette	Modular Extension of ATE to 5 Gbps.	ITC	2004	DBLP DOI BibTeX RDF
12	Rohini Krishnan, José Pineda de Gyvez	Low Energy Switch Block For FPGAs.	VLSI Design	2004	DBLP DOI BibTeX RDF
12	Anand Raghunathan, Sujit Dey, Niraj K. Jha	High-level macro-modeling and estimation techniques for switching activity and power consumption.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
12	Arturo Hernández Aguirre, Carlos A. Coello Coello	Evolutionary Synthesis of Logic Circuits Using Information Theory.	Artif. Intell. Rev.	2003	DBLP DOI BibTeX RDF	evolutionary algorithms, genetic programming, computer-aided design, information theory, evolvable hardware, circuit synthesis
12	Bibhudatta Sahoo 0002, Keshab K. Parhi	A Low Power Correlator for CDMA Wireless Systems.	J. VLSI Signal Process.	2003	DBLP DOI BibTeX RDF	low-power, correlator, CDMA, incrementer
12	Peter Winkler 0001, Lisa Zhang	Wavelength assignment and generalized interval graph coloring.	SODA	2003	DBLP BibTeX RDF
12	Jong-Ru Guo, Chao You, Kuan Zhou, Bryan S. Goda, Russell P. Kraft, John F. McDonald 0001	A scalable 2 V, 20 GHz FPGA using SiGe HBT BiCMOS technology.	FPGA	2003	DBLP DOI BibTeX RDF	basic cell, FPGA, CML, SiGe
12	Aneesh Koorapaty, Vikas Chandra, Kim Yaw Tong, Chetan Patel, Lawrence T. Pileggi, Herman Schmit	Heterogeneous Programmable Logic Block Architectures.	DATE	2003	DBLP DOI BibTeX RDF
12	Irith Pomeranz, Sudhakar M. Reddy	A DFT Approach for Path Delay Faults in Interconnected Circuits.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
12	Arturo Hernández Aguirre, Edgar C. González Equihua, Carlos A. Coello Coello	Synthesis of Boolean Functions Using Information Theory.	ICES	2003	DBLP DOI BibTeX RDF
12	James R. Heath	A systems approach to molecular electronics.	ISLPED	2003	DBLP DOI BibTeX RDF
12	Arturo Hernández Aguirre, Carlos A. Coello Coello	Gate-level Synthesis of Boolean Functions using Information Theory Concepts.	ENC	2003	DBLP DOI BibTeX RDF
12	Manev Luthra, Sumit Gupta, Nikil D. Dutt, Rajesh K. Gupta 0001, Alexandru Nicolau	Interface Synthesis using Memory Mapping for an FPGA Platform.	ICCD	2003	DBLP DOI BibTeX RDF
12	Süleyman Sirri Demirsoy, Andrew G. Dempster, Izzet Kale	Design guidelines for reconfigurable multiplier blocks.	ISCAS (4)	2003	DBLP DOI BibTeX RDF
12	Yeong-Kang Lai, Han-Jen Hsu	A cost-effective 2-D discrete cosine transform processor with reconfigurable datapath.	ISCAS (2)	2003	DBLP DOI BibTeX RDF
12	Chao You, Jong-Ru Guo, Russell P. Kraft, Kuan Zhou, Michael Chu, John F. McDonald 0001	A 5-20 GHz, low power FPGA implemented by SiGe HBT BiCMOS technology.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	BC, BCII, FPGA, dynamic routing, CML
12	Tomokazu Yoneda, Hideo Fujiwara	Design for Consecutive Transparency of Cores in System-on-a-Chip.	VTS	2003	DBLP DOI BibTeX RDF	consecutive transparency, design for testability, system-on a chip, register transfer level, test access mechanism, consecutive testability
12	Cristian Estan, George Varghese, Mike Fisk	Counting the number of active flows on a high speed link.	Comput. Commun. Rev.	2002	DBLP DOI BibTeX RDF
12	Witold Pedrycz, George Vukovich	An fMUX architecture: data modularization and mixed-mode system modeling.	Soft Comput.	2002	DBLP DOI BibTeX RDF	Fuzzy multiplexer, Mixed-mode modeling, OR and AND neurons, Learning, Multivalued logic, Digital systems, Logic modeling
12	George Koutroumpezis, Konstantinos Tatas, Dimitrios Soudris, Spyros Blionas, Kostas Masselos, Adonios Thanailakis	Architecture Design of a Reconfigurable Multiplier for Flexible Coarse-Grain Implementations.	FPL	2002	DBLP DOI BibTeX RDF
12	Steve L. Ferenci, Richard M. Fujimoto, Mostafa H. Ammar, Kalyan S. Perumalla, George F. Riley	Updateable simulation of communication networks.	PADS	2002	DBLP DOI BibTeX RDF	event composition, event reuse, incremental simulation, shared computation
12	Mario R. Casu, Philippe Flatresse	Converting an Embedded Low-Power SRAM from Bulk to PD-SOI.	MTDT	2002	DBLP DOI BibTeX RDF
12	Lin Zhong 0001, Niraj K. Jha	Interconnect-aware high-level synthesis for low power.	ICCAD	2002	DBLP DOI BibTeX RDF
12	Joshua J. Yi, David J. Lilja	Improving Processor Performance by Simplifying and Bypassing Trivial Computations.	ICCD	2002	DBLP DOI BibTeX RDF
12	Salvatore Pontarelli, Gian Carlo Cardarilli, A. Leandri, Marco Ottavi, Marco Re, Adelio Salsano	A self-checking cell logic block for fault tolerant FPGAs.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
12	Yuanyuan Yang 0001, Jianchao Wang	A Class of Multistage Conference Switching Networks for Group Communication.	ICPP	2002	DBLP DOI BibTeX RDF
12	Richard J. Blaikie, Maan M. Alkaisi, Steven M. Durbin, David R. S. Cumming	Teaching Integrated Circuit and Semiconductor Device Design in New Zealand: The University of Canterbury Approach.	DELTA	2002	DBLP DOI BibTeX RDF	Semiconductor Devices, Education, Integrated Circuit
12	Miron Abramovici, Charles E. Stroud	BIST-based test and diagnosis of FPGA logic blocks.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
12	Zaher Abdulkarim Baidas, Andrew D. Brown, Alan Christopher Williams	Floating-point behavioral synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
12	Xin Yuan, Amit Fulay	A Wavelength Assignment Heuristic to Minimize SONET ADMs in WDM Rings.	ICPP Workshops	2001	DBLP DOI BibTeX RDF
12	Lawrence Davis, Chunsheng Fu, Stewart W. Wilson	An Incremental Multiplexer Problem and Its Uses in Classifier System Research.	IWLCS	2001	DBLP DOI BibTeX RDF
12	Chi-Li Yu, An-Yeu Wu	An improved time-recursive lattice structure for low-latency IFFT architecture in DMT transmitter.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
12	Youngjoon Kim, Lee-Sup Kim	A low power carry select adder with reduced area.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
12	Kisun Kim, Taekyoon Ahn, Sang-Yeol Han, Chang-Seung Kim, Ki-Hyun Kim	Low-power multiplexer decomposition by suppressing propagation of signal transitions.	ISCAS (5)	2001	DBLP DOI BibTeX RDF
12	Kamal Rajagopalan, Peter R. Sutton	A flexible multiplication unit for an FPGA logic block.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
12	Tat Ngai, Earl E. Swartzlander Jr., Chen He	Enhanced Concurrent Error Correcting Arithmetic Unit Design Using Alternating Logic.	DFT	2001	DBLP DOI BibTeX RDF	Alternating Logic, Fault Tolerance, TMR, Concurrent Error Correcting, Arithmetic Unit
12	Ralf Münzenberger, Frank Slomka, Matthias Dörfel, Richard Hofmann	A General Approach for the Specification of Real-Time Systems with SDL.	SDL Forum	2001	DBLP DOI BibTeX RDF
12	Roberto Battiti, Mauro Brunato	Reactive Search for Traffic Grooming in WDM Networks.	IWDC	2001	DBLP DOI BibTeX RDF
12	Indradeep Ghosh, Niraj K. Jha, Sudipta Bhawmik	A BIST scheme for RTL circuits based on symbolic testabilityanalysis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
12	Taewhan Kim, Junhyung Um	A practical approach to the synthesis of arithmetic circuits usingcarry-save-adders.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
12	Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian	Testing the Local Interconnect Resources of SRAM-Based FPGA's.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	FPGA, VLSI, test, ATPG
12	Kanad Chakraborty, Pinaki Mazumder	New March Tests for Multiport RAM Devices.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	multi-port RAM, simplex and duplex coupling faults, concurrent coupling faults
12	Subhasish Mitra, LaNae J. Avra, Edward J. McCluskey	Efficient Multiplexer Synthesis Techniques.	IEEE Des. Test Comput.	2000	DBLP DOI BibTeX RDF
12	Thomas Bräunl	Register-Transfer Level Simulation.	MASCOTS	2000	DBLP DOI BibTeX RDF
12	Saso Stojanovski, Maurice Gagnaire, Rudy Hoebeke	Probiding GFR Guarantees for TCP/IP Traffic over APON Access Systems.	NETWORKING	2000	DBLP DOI BibTeX RDF
12	Christoph Scholl 0001, Bernd Becker 0001	On the Generation of Multiplexer Circuits for Pass Transistor Logic.	DATE	2000	DBLP DOI BibTeX RDF
12	Marcos Postigo-Boix, Mónica Aguilar-Igartua, Joan García-Haro	Inverse Multiplexing for ATM. Technical Operation, Applications and Performance Evaluation Study.	ISCC	2000	DBLP DOI BibTeX RDF
12	Zlatko Zografski, Toni Janevski	Analyses of MPEG-4 Video Streams Processing in Computer Clusters Based on Multihop ATM Networks.	ISCC	2000	DBLP DOI BibTeX RDF	Video networking, multihop ATM networks, QoS, MPEG-4, computer clusters
12	Rolf Drechsler, Mitchell A. Thornton, David Wessels	MDD-Based Synthesis of Multi-Valued Logic Networks.	ISMVL	2000	DBLP DOI BibTeX RDF
12	Bibhudatta Sahoo 0002, Martin Kuhlmann, Keshab K. Parhi	A low-power correlator.	ACM Great Lakes Symposium on VLSI	2000	DBLP DOI BibTeX RDF
12	Bogdan J. Falkowski, Sudha Kannurao	Spectral Theory of Disjunctive Decomposition for Balanced Boolean Functions.	VLSI Design	2000	DBLP DOI BibTeX RDF	Disjunctive decomposition, Balanced Boolean functions, Walsh Transform
12	Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha	Hierarchical test generation and design for testability methods for ASPPs and ASIPs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
12	Matthias Falkner, Michael Devetsikiotis, Ioannis Lambadaris	Fast Simulation of Networks of Queues with Effective and Decoupling Bandwidths.	ACM Trans. Model. Comput. Simul.	1999	DBLP DOI BibTeX RDF	asynchronous transfer mode, importance sampling, rare events, fast simulation
12	Dimitris Nikolos, Haridimos T. Vergos, Th. Haniotakis, Y. Tsiatouhas	Path Delay Fault Testing of ICs with Embedded Intellectual Property Blocks.	DATE	1999	DBLP DOI BibTeX RDF
12	Shyue-Kung Lu, Cheng-Wen Wu	A novel approach to testing LUT-based FPGAs.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
12	John F. McDonald 0001, Bryan S. Goda	Reconfigurable FPGA's in the 1-20 GHz Band with HBT BiCMOS.	Evolvable Hardware	1999	DBLP DOI BibTeX RDF
12	Wei-Kang Huang, Fred J. Meyer, Xiao-Tao Chen, Fabrizio Lombardi	Testing configurable LUT-based FPGA's.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
12	Nick G. Duffield	Queueing at large resources driven by long-tailed M/G/Y-modulated processes.	Queueing Syst. Theory Appl.	1998	DBLP DOI BibTeX RDF	shape function, self-similarity, large deviations, long-range dependence, heavy-tailed distribution, multiple time-scales
12	Lan Zhao, D. M. H. Walker, Fabrizio Lombardi	IDDQ Testing of Bridging Faults in Logic Resources of Reconfigurable Field Programmable Gate Arrays.	IEEE Trans. Computers	1998	DBLP DOI BibTeX RDF
12	Chih-Chang Lin, Malgorzata Marek-Sadowska, Mike Tien-Chien Lee, Kuang-Chien Chen	Cost-free scan: a low-overhead scan path design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
12	Chih-Chang Lin, Malgorzata Marek-Sadowska, Kwang-Ting Cheng, Mike Tien-Chien Lee	Test-point insertion: scan paths through functional logic.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
12	Wenyi Feng, Fred J. Meyer, Wei-Kang Huang, Fabrizio Lombardi	On the Complexity of Sequential Testing in Configurable FPGAs.	DFT	1998	DBLP DOI BibTeX RDF	FPGA, pipeline, PLD, sequential testing, iterative array
12	Indradeep Ghosh, Niraj K. Jha, Sudipta Bhawmik	A BIST Scheme for RTL Controller-Data Paths Based on Symbolic Testability Analysis.	DAC	1998	DBLP DOI BibTeX RDF
12	Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj	Analytical estimation of signal transition activity from word-level statistics.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
12	Nur A. Touba, Bahram Pouya	Using Partial Isolation Rings to Test Core-Based Designs.	IEEE Des. Test Comput.	1997	DBLP DOI BibTeX RDF
12	Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian	Test Pattern and Test Configuration Generation Methodology for the Logic of RAM-Based FPGA.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	FPGA, VLSI, Test, CMOS, IC
12	Edward W. Knightly	Second Moment Resource Allocation in Multi-Service Networks.	SIGMETRICS	1997	DBLP DOI BibTeX RDF
12	C. P. Ravikumar, R. Aggarwal, C. Sharma	A Graph-Theoretic Approach for Register File Based Synthesis.	VLSI Design	1997	DBLP DOI BibTeX RDF
12	Krishnendu Chakrabarty, John P. Hayes	Test response compaction using multiplexed parity trees.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
12	Anand Raghunathan, Sujit Dey, Niraj K. Jha	Register-transfer level estimation techniques for switching activity and power consumption.	ICCAD	1996	DBLP DOI BibTeX RDF	gate-level implementation, register-transfer level estimation, logic design, power consumption, switching activity, glitching, RTL designs
12	Lizy Kurian John	VaWiRAM: a variable width random access memory module.	VLSI Design	1996	DBLP DOI BibTeX RDF	VaWiRAM, variable width random access memory, flexible memory systems, configuration pins, pass gates, reconfigurability, reconfigurable architectures, memory architecture, programmable logic, random-access storage, integrated circuit interconnections, programmable logic devices, programmable interconnect
12	Santonu Sarkar, Anupam Basu, Arun K. Majumdar	Representation and Synthesis of Interface of a Circuit for its Reuse.	VLSI Design	1996	DBLP DOI BibTeX RDF	VaWiRAM, variable width random access memory, flexible memory systems, configuration pins, pass gates, reconfigurability, reconfigurable architectures, memory architecture, programmable logic, random-access storage, integrated circuit interconnections, programmable logic devices, programmable interconnect
12	Israel Cidon, Roch Guérin, Ilan Kessler, Asad Khamisy	Analysis of a statistical multiplexer with generalized periodic sources.	Queueing Syst. Theory Appl.	1995	DBLP DOI BibTeX RDF	Periodic queue, ON-OFF sources, ballot theory, fluid model
12	Muhammad K. Dhodhi, Frank H. Hielscher, Robert H. Storer, Jayaram Bhasker	Datapath synthesis using a problem-space genetic algorithm.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
12	Rajesh Gupta 0003, Melvin A. Breuer	Partial scan design of register-transfer level circuits.	J. Electron. Test.	1995	DBLP DOI BibTeX RDF	serial scan design, I-paths, design for testability, register-transfer level designs, balanced structures, partial scan design
12	Gensoh Matsubara, Nobuhiro Ide, Haruyuki Tago, Seigo Suzuki, Nobuyuki Goto	30-ns 55-b Radix 2 Division and Square Root Using a Self-Timed Circuit.	IEEE Symposium on Computer Arithmetic	1995	DBLP DOI BibTeX RDF	simulation, CMOS, division, square root, self-timed, SRT, on-the-fly
12	Amit Chowdhary, John P. Hayes	Technology mapping for field-programmable gate arrays using integer programming.	ICCAD	1995	DBLP DOI BibTeX RDF	Field-programmable gate arrays (FPGAs), technology mapping, mixed integer linear programming (MILP), lookup tables, circuit partitioning
12	Thomas M. Sarfert, Remo G. Markgraf, Michael H. Schulz, Erwin Trischler	A hierarchical test pattern generation system based on high-level primitives.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
12	Raul Camposano	From Behavior to Structure: High-Level Synthesis.	IEEE Des. Test Comput.	1990	DBLP DOI BibTeX RDF
12	W. E. Mattis	A Hybrid Architecture for Neurocomputing (Abstract).	ACM Conference on Computer Science	1990	DBLP DOI BibTeX RDF
12	Forrest Brewer, Barry M. Pangrle, Andrew Seawright	Interconnection synthesis with geometric constraints.	MICRO	1990	DBLP BibTeX RDF
12	Hussam Y. Abujbara, Sami A. Al-Arian	Self-testing and self-reconfiguration architecture for 2-D WSI arrays.	SPDP	1990	DBLP DOI BibTeX RDF
12	Kayhan Küçükçakar, Alice C. Parker	Data Path Tradeoffs Using MABAL.	DAC	1990	DBLP DOI BibTeX RDF
12	Richard J. Reid	Interactive digital-simulation laboratory gains special components.	ACM Conference on Computer Science	1987	DBLP DOI BibTeX RDF
12	Thomas Philip	Using animated color graphics to illustrate software and hardware organizations (abstract only).	ACM Conference on Computer Science	1987	DBLP DOI BibTeX RDF
12	Rajiv Jain, Alice C. Parker, Nohbyung Park	Predicting Area-Time Tradeoffs for Pipelined Design.	DAC	1987	DBLP DOI BibTeX RDF
12	Robert C. Fairfield, Alex Matusevich, Joseph Plany	An LSI Digital Encryption Processor (DEP).	CRYPTO	1984	DBLP DOI BibTeX RDF
12	S. M. Schiffman	Designing and managing an SNA network for growth.	AFIPS National Computer Conference	1983	DBLP DOI BibTeX RDF