Search results for "retiming"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
18	Abhishek Ranjan, Ankur Srivastava 0001, V. Karnam, Majid Sarrafzadeh	Layout aware retiming.	ACM Great Lakes Symposium on VLSI	2001	DBLP DOI BibTeX RDF
18	Abdallah Tabbara, Bassam Tabbara, Robert K. Brayton, A. Richard Newton	Integration of retiming with architectural floorplanning.	Integr.	2000	DBLP DOI BibTeX RDF
18	Tzu-Chieh Tien, Youn-Long Lin	Performance-optimal clustering with retiming for sequential circuits.	ASP-DAC	2000	DBLP DOI BibTeX RDF
18	Jason Cong, Sung Kyu Lim	Physical Planning with Retiming.	ICCAD	2000	DBLP DOI BibTeX RDF
18	Zhan Yu, Kei-Yong Khoo, Alan N. Willson Jr.	Joint module selection and retiming with carry-save representation.	EUSIPCO	2000	DBLP BibTeX RDF
18	Naresh Maheshwari, Sachin S. Sapatnekar	Retiming control logic.	Integr.	1999	DBLP DOI BibTeX RDF
18	Timothy W. O'Neil, Sissades Tongsima, Edwin Hsing-Mean Sha	Extended retiming: optimal scheduling via a graph-theoretical approach.	ICASSP	1999	DBLP DOI BibTeX RDF
18	Aarti Gupta, Pranav Ashar, Sharad Malik	Exploiting Retiming in a Guided Simulation Based Validation Methodology.	CHARME	1999	DBLP DOI BibTeX RDF
18	Margarida F. Jacome, Gustavo de Veciana, Cagdas Akturan	Resource constrained dataflow retiming heuristics for VLIW ASIPs.	CODES	1999	DBLP DOI BibTeX RDF
18	Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman	Maximizing Performance by Retiming and Clock Skew Scheduling.	DAC	1999	DBLP DOI BibTeX RDF
18	Peichen Pan	Performance-Driven Integration of Retiming and Resynthesis.	DAC	1999	DBLP DOI BibTeX RDF
18	Abdallah Tabbara, Robert K. Brayton, A. Richard Newton	Retiming for DSM with Area-Delay Trade-Offs and Delay Constraints.	DAC	1999	DBLP DOI BibTeX RDF
18	Jason Cong, Honching Li, Chang Wu	Simultaneous Circuit Partitioning/Clustering with Retiming for Performance Optimization.	DAC	1999	DBLP DOI BibTeX RDF
18	Klaus Eckl, Jean Christophe Madre, Peter Zepter, Christian Legl	A Practical Approach to Multiple-Class Retiming.	DAC	1999	DBLP DOI BibTeX RDF
18	Karam S. Chatha, Ranga Vemuri	RECOD: a retiming heuristic to optimize resource and memory utilization in HW/SW codesigns.	CODES	1998	DBLP DOI BibTeX RDF
18	Soha Hassoun	Fine Grain Incremental Rescheduling Via Architectural Retiming.	ISSS	1998	DBLP DOI BibTeX RDF
18	Marios C. Papaefthymiou	Asymptotically efficient retiming under setup and hold constraints.	ICCAD	1998	DBLP DOI BibTeX RDF
18	Gagan Hasteer, Anmol Mathur, Prithviraj Banerjee	Efficient equivalence checking of multi-phase designs using retiming.	ICCAD	1998	DBLP DOI BibTeX RDF
18	Rajeev K. Ranjan 0001, Vigyan Singhal, Fabio Somenzi, Robert K. Brayton	On the optimization power of retiming and resynthesis transformations.	ICCAD	1998	DBLP DOI BibTeX RDF
18	Tzu-Chieh Tien, Hsiao-Pin Su, Yu-Wen Tsay, Yih-Chih Chou, Youn-Long Lin	Integrating logic retiming and register placement.	ICCAD	1998	DBLP DOI BibTeX RDF
18	Prashant Saxena	The Retiming and Routing of VLSI Circuits		1998	RDF
18	Alain Darte, Georges-André Silber, Frédéric Vivien	Combining Retiming and Scheduling Techniques for Loop Parallelization and Loop Tiling.	Parallel Process. Lett.	1997	DBLP DOI BibTeX RDF
18	Narendra V. Shenoy	Retiming: Theory and practice.	Integr.	1997	DBLP DOI BibTeX RDF
18	Yao-Ping Chen, D. F. Wong 0001	On retiming for FPGA logic module minimization.	Integr.	1997	DBLP DOI BibTeX RDF
18	Peichen Pan	Continuous Retiming: Algorithms and Applications.	ICCD	1997	DBLP DOI BibTeX RDF
18	Arvind K. Karandikar, Peichen Pan, C. L. Liu 0001	Optimal Clock Period Clustering for Sequential Circuits with Retiming.	ICCD	1997	DBLP DOI BibTeX RDF
18	Guy Even	The Retiming Lemma: A simple proof and applications.	Integr.	1996	DBLP DOI BibTeX RDF
18	Dimitrios Kagaris, Spyros Tragoudas	Retiming-Based Partial Scan.	IEEE Trans. Computers	1996	DBLP DOI BibTeX RDF
18	Nelson L. Passos, Edwin Hsing-Mean Sha, Steven C. Bass	Optimizing DSP flow graphs via schedule-based multidimensional retiming.	IEEE Trans. Signal Process.	1996	DBLP DOI BibTeX RDF
18	Vojin Zivojnovic, Rainer Schoenen	On retiming of multirate DSP algorithms.	ICASSP	1996	DBLP DOI BibTeX RDF
18	Tracy C. Denk, Mayukh Majumdar, Keshab K. Parhi	Two-dimensional retiming with low memory requirements.	ICASSP	1996	DBLP DOI BibTeX RDF
18	Marios C. Papaefthymiou, Kumar N. Lalgudi	Fixed-phase retiming for low power design.	ISLPED	1996	DBLP DOI BibTeX RDF
18	Andrea Maggiolo-Schettini, Adriano Peron	Retiming Techniques for Statecharts.	FTRTFT	1996	DBLP DOI BibTeX RDF
18	Huoy-Yu Liou, Ting-Ting Y. Lin, Chung-Kuan Cheng	Area Efficient Pipelined Pseudo-Exhaustive Testing with Retiming.	DAC	1996	DBLP DOI BibTeX RDF
18	Soha Hassoun, Carl Ebeling	Architectural Retiming: Pipelining Latency-Constrained Circuts.	DAC	1996	DBLP DOI BibTeX RDF
18	Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita	Retiming for Sequential Circuits with a Specified Initial State and Its Application to Testability Enhancement.	IEICE Trans. Inf. Syst.	1995	DBLP BibTeX RDF
18	Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita	Synthesis for Testability by Sequential Redundancy Removal Using Retiming.	FTCS	1995	DBLP DOI BibTeX RDF
18	Leon Stok, Ilan Y. Spillinger, Guy Even	Improving initialization through reversed retiming.	ED&TC	1995	DBLP DOI BibTeX RDF
18	F. Fernández, A. Sánchez	Design and Optimization of MuItiphase Clocking Systolic Architectures using Algebraic Retiming Techniques: Extension to Regular Graphs.	PARCO	1995	DBLP BibTeX RDF
18	Vigyan Singhal, Robert K. Brayton, Carl Pixley	Power-Up Delay for Retiming Digital Circuits.	ISCAS	1995	DBLP DOI BibTeX RDF
18	Samir Lejmi, Bozena Kaminska, Bechir Ayari	Retiming for BIST-Sequential Circuits.	ISCAS	1995	DBLP DOI BibTeX RDF
18	Sven Simon 0001, Johann Hofner, Josef A. Nossek	Retiming of Circuits Containing Multiplexers.	ISCAS	1995	DBLP BibTeX RDF
18	Tolga Soyata, Eby G. Friedman, James H. Mulligan Jr.	Monotonicity Constraints on Path Delays for Efficient Retiming with Localized Clock Skew and Variable Register Delay.	ISCAS	1995	DBLP DOI BibTeX RDF
18	Samir Lejmi, Bozena Kaminska, Bechir Ayari	Synthesis and Retiming for the Pseudo-Exhaustive BIST of Synchronous Sequential Circuits.	ITC	1995	DBLP DOI BibTeX RDF
18	Vigyan Singhal, Carl Pixley, Richard L. Rudell, Robert K. Brayton	The Validity of Retiming Sequential Circuits.	DAC	1995	DBLP DOI BibTeX RDF
18	Kumar N. Lalgudi, Marios C. Papaefthymiou	DELAY: An Efficient Tool for Retiming with Realistic Delay Modeling.	DAC	1995	DBLP DOI BibTeX RDF
18	Y. G. DeCastelo-Vide-e-Souza, Miodrag Potkonjak, Alice C. Parker	Optimal ILP-Based Approach for Throughput Optimization Using Simultaneous Algorithm/Architecture Matching and Retiming.	DAC	1995	DBLP DOI BibTeX RDF
18	Ireneusz Karkowski, Ralph H. J. M. Otten	Retiming Synchronous Circuitry with Imprecise Delays.	DAC	1995	DBLP DOI BibTeX RDF
18	Rahul B. Deokar, Sachin S. Sapatnekar	A Fresh Look at Retiming Via Clock Skew Optimization.	DAC	1995	DBLP DOI BibTeX RDF
18	Marios C. Papaefthymiou	Understanding Retiming Through Maximum Avarage-Delay Cycles.	Math. Syst. Theory	1994	DBLP DOI BibTeX RDF
18	Vojin Zivojnovic, Sebastian Ritz, Heinrich Meyr	Retiming of DSP programs for optimum vectorization.	ICASSP (2)	1994	DBLP DOI BibTeX RDF
18	Nelson L. Passos, Edwin Hsing-Mean Sha, Steven C. Bass	Schedule-Based Multi-Dimensional Retiming on Data Flow Graphs.	IPPS	1994	DBLP DOI BibTeX RDF
18	Albert van der Werf, Jef L. van Meerbergen, Emile H. L. Aarts, Wim F. J. Verhaegh, Paul E. R. Lippens	Efficient timing constraint derivation for optimal retiming high speed processing units.	HLSS	1994	DBLP DOI BibTeX RDF
18	Norbert Wehn, Jörg Biesenack, Peter Duzy, T. Langmaier, Michael Münch, Michael Pilsl, Steffen Rumler	Scheduling of behavioral VHDL by retiming techniques.	EURO-DAC	1994	DBLP DOI BibTeX RDF	VHDL
18	Joel Grodstein, Eric Lehman, Heather Harkness, Hervé J. Touati, Bill Grundmann	Optimal latch mapping and retiming within a tree.	ICCAD	1994	DBLP DOI BibTeX RDF
18	Yao-Ping Chen, D. F. Wong 0001	On Retiming for FPGA Logic Module Minimization.	ICCD	1994	DBLP DOI BibTeX RDF
18	Samir Lejmi, Bozena Kaminska, Edouard Wagneur	Retiming for the Global Optimization of Synchronous Sequential Circuits.	ICCD	1994	DBLP DOI BibTeX RDF
18	Sven Simon 0001, Ernst G. Bernard, Matthias Sauer 0001, Josef A. Nossek	A New Retiming Algorithm for Circuit Design.	ISCAS	1994	DBLP DOI BibTeX RDF
18	Liang-Fang Chao, Edwin Hsing-Mean Sha	Retiming and Clock Skew for Synchronous Systems.	ISCAS	1994	DBLP DOI BibTeX RDF
18	Nelson L. Passos, Edwin Hsing-Mean Sha, Steven C. Bass	Partitioning and Retiming of Multi-Dimensional Systems.	ISCAS	1994	DBLP DOI BibTeX RDF
18	Dimitrios Kagaris, Spyros Tragoudas	Retiming algorithms with application to VLSI testability.	Great Lakes Symposium on VLSI	1994	DBLP DOI BibTeX RDF
18	Sujit Dey, Srimat T. Chakradhar	Retiming sequential circuits to enhance testability.	VTS	1994	DBLP DOI BibTeX RDF
18	Nelson L. Passos, Edwin Hsing-Mean Sha	Full Parallelism in Uniform Nested Loops Using Multi-Dimensional Retiming.	ICPP (2)	1994	DBLP DOI BibTeX RDF
18	Srimat T. Chakradhar, Sujit Dey	Resynthesis and Retiming for Optimum Partial Scan.	DAC	1994	DBLP DOI BibTeX RDF
18	Guy Even	Design of VLSI circuits using Retiming.		1994	RDF
18	Stephen D. Brookes	Using Fixed-Point Semantics to Prove Retiming Lemmas.	Formal Methods Syst. Des.	1993	DBLP DOI BibTeX RDF
18	Albert van der Werf, Emile H. L. Aarts, E. W. Heijnen, Jef L. van Meerbergen, Wim F. J. Verhaegh, Paul E. R. Lippens	A new method for retiming multi-functional processing units.	VLSI	1993	DBLP BibTeX RDF
18	Liang-Fang Chao, Edwin Hsing-Mean Sha	Efficient retiming and unfolding.	ICASSP (1)	1993	DBLP DOI BibTeX RDF
18	Ulrich Weinmann, Wolfgang Rosenstiel	Technology mapping for sequential circuits based on retiming techniques.	EURO-DAC	1993	DBLP DOI BibTeX RDF
18	Hans-Georg Martin	Retiming by combination of relocation and clock delay adjustment.	EURO-DAC	1993	DBLP DOI BibTeX RDF
18	Brian Lockyear, Carl Ebeling	The practical application of retiming to the design of high-performance systems.	ICCAD	1993	DBLP DOI BibTeX RDF
18	José Monteiro 0001, Srinivas Devadas, Abhijit Ghosh	Retiming sequential circuits for low power.	ICCAD	1993	DBLP DOI BibTeX RDF
18	Alexander T. Ishii	Retiming gated-clocks and precharged circuit structures.	ICCAD	1993	DBLP DOI BibTeX RDF
18	Lung-Tien Liu, Minshine Shih, Nan-Chi Chou, Chung-Kuan Cheng, Walter H. Ku	Performance-driven partitioning using retiming and replication.	ICCAD	1993	DBLP DOI BibTeX RDF
18	Miodrag Potkonjak, Sujit Dey, Zia Iqbal, Alice C. Parker	High Performance Embedded System Optimization Using Algebraic and Generalized Retiming Techniques.	ICCD	1993	DBLP DOI BibTeX RDF
18	Samir Lejmi, Bozena Kaminska, Edouard Wagneur	Resynthesis and Retiming of Synchronous Sequential Cirucits.	ISCAS	1993	DBLP BibTeX RDF
18	Tolga Soyata, Eby G. Friedman, James H. Mulligan Jr.	Integration of Clock Skew and Register Delays into a Retiming Algorithm.	ISCAS	1993	DBLP BibTeX RDF
18	Dimitrios Kagaris, Spyros Tragoudas	Partial Scan with Retiming.	DAC	1993	DBLP DOI BibTeX RDF
18	Zia Iqbal, Miodrag Potkonjak, Sujit Dey, Alice C. Parker	Critical Path Minimization Using Retiming and Algebraic Speed-Up.	DAC	1993	DBLP DOI BibTeX RDF
18	Ming-Kang Liu	Using negative stuffing retiming for circuit emulation in a packet switching network.	IEEE Trans. Commun.	1992	DBLP DOI BibTeX RDF
18	Liang-Fang Chao, Edwin Hsing-Mean Sha	Unfolding and retiming data-flow DSP programs for RISC multiprocessor scheduling.	ICASSP	1992	DBLP DOI BibTeX RDF
18	Sujit Dey, Miodrag Potkonjak, Steven G. Rothweiler	Performance optimization of sequential circuits by eliminating retiming bottlenecks.	ICCAD	1992	DBLP DOI BibTeX RDF
18	Jin-Chin Chung	Optimal Loope Parallelization Based on a Retiming Technique.	ICPP (2)	1992	DBLP BibTeX RDF
18	Liang-Fang Chao, Edwin Hsing-Mean Sha	Retiming and Unfolding Data-Flow Graphs.	ICPP (2)	1992	DBLP BibTeX RDF
18	Charles E. Leiserson, James B. Saxe	Retiming Synchronous Circuitry.	Algorithmica	1991	DBLP DOI BibTeX RDF
18	Ellen Sentovich, Robert K. Brayton	Preserving Don't Care Conditions During Retiming.	VLSI	1991	DBLP BibTeX RDF
18	Albert van der Werf, B. T. McSweeney, Jef L. van Meerbergen, Paul E. R. Lippens, Wim F. J. Verhaegh	Hierarchical Retiming Including Pipelining.	VLSI	1991	DBLP BibTeX RDF
18	Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli	Retiming of Circuits with Single Phase Transparent Latches.	ICCD	1991	DBLP DOI BibTeX RDF
18	Marios C. Papaefthymiou	Understanding Retiming Through Maximum Average-Weight Cycles.	SPAA	1991	DBLP DOI BibTeX RDF
18	Daniel A. Fishman, Robert L. Rosenberg, Christodoulos Chamzas	Analysis of Jitter Peaking Effects in Digital Long-Haul Transmission Systems Using SAW-Filter Retiming.	IEEE Trans. Commun.	1985	DBLP DOI BibTeX RDF
17	Toshinori Sato, Yuji Kunitake	Exploiting Input Variations for Energy Reduction.	PATMOS	2007	DBLP DOI BibTeX RDF	typical-case design, dynamic retiming, reliable microarchitecture, robust microarchitecture, DVFS, deep sub-micron
17	Zili Shao, Bin Xiao 0001, Chun Xue, Qingfeng Zhuge, Edwin Hsing-Mean Sha	Loop scheduling with timing and switching-activity minimization for VLIW DSP.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	instruction bus optimization, low-power optimization, compilers, software pipelining, VLIW, retiming, instruction scheduling, loops
17	Xinmiao Zhang, Keshab K. Parhi	High-speed architectures for parallel long BCH encoders.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	BCH, critical loop, iteration bound, parallel processing, encoder, linear feedback shift register, retiming, unfolding, fanout, generator polynomial
17	Akshay Sharma, Carl Ebeling, Scott Hauck	PipeRoute: a pipelining-aware router for FPGAs.	FPGA	2003	DBLP DOI BibTeX RDF	BFS, PipeRoute, retimed circuits, routing, pipelining, minimum spanning tree, retiming, pipelined circuits
17	Jason Cong, Chang Wu	Global clustering-based performance-driven circuit partitioning.	ISPD	2002	DBLP DOI BibTeX RDF	clustering, partitioning, performance optimization, retiming, VLSI CAD
17	Fei Chen, Timothy W. O'Neil, Edwin Hsing-Mean Sha	Optimizing Overall Loop Schedules Using Prefetching and Partitioning.	IEEE Trans. Parallel Distributed Syst.	2000	DBLP DOI BibTeX RDF	scheduling, partitioning, Prefetching, retiming, latency-hiding
17	Peichen Pan, C. L. Liu 0001	Partial Scan with Preselected Scan Signals.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	design for testability, retiming, partial scan, Digital testing
17	Fenghao Mu, Christer Svensson	Vector Transfer by Self-Tested Self-Synchronization for Parallel Systems.	IEEE Trans. Parallel Distributed Syst.	1999	DBLP DOI BibTeX RDF	VLSI, synchronization, Parallel systems, retiming, metastability, high speed interconnect
17	Kaisheng Wang, Ted Zhihong Yu, Edwin Hsing-Mean Sha	RCRS: A Framework for Loop Scheduling with Limited Number of Registers.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	retiming, rotation, data-flow graphs, Loop scheduling, registers
17	Alexander T. Ishii, Charles E. Leiserson, Marios C. Papaefthymiou	Optimizing two-phase, level-clocked circuitry.	J. ACM	1997	DBLP DOI BibTeX RDF	clock tuning, level-clocked circuitry, multiphase clocking, timing analysis and optimization, VLSI, retiming