Search results for "slew"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
19	John G. Kenney, Giri Rangan, Karthik Ramamurthy, Gabor C. Temes	An enhanced slew rate source follower.	IEEE J. Solid State Circuits	1995	DBLP DOI BibTeX RDF
19	Andrew E. Stevens, Gerald A. Miller	A high-slew integrator for switched-capacitor circuits.	IEEE J. Solid State Circuits	1994	DBLP DOI BibTeX RDF
19	Jaime Ramírez-Angulo	High Slew Rate, Low Voltage BiCMOS and Bipolar Operational Amplifier Architectures with Rail to Rrail Common Mode Input Voltage Swing.	ISCAS	1994	DBLP DOI BibTeX RDF
19	Hironori Fujii, Shigeyuki Takeda	Control of a flexible space structure with a tip mass in minimum time slew maneuver.	Robotics, Mechatronics and Manufacturing Systems	1993	DBLP DOI BibTeX RDF
19	Kartahik Ramamurthy, John G. Kenney, Giri Rangan	On-chip Tests for Gain Bandwidth Product and Slew Rate.	ISCAS	1993	DBLP BibTeX RDF
19	Dong Li	A control design approach for slew maneuver of elastic multibody systems.	ICRA	1992	DBLP DOI BibTeX RDF
19	Andrzej Borys	Sinusoidal oscillators with slew-rate type nonlinearity.	Eur. Trans. Telecommun.	1991	DBLP DOI BibTeX RDF
19	Hiekeun Ko, Clark C. Davis, Edwin K. Iversen, Stephen C. Jacobsen	High stiffness and low slew drag in an antagonistic control system.	ICRA	1990	DBLP DOI BibTeX RDF
19	P. P. J. van den Bosch, W. Jongkind, A. C. M. van Swieten	Adaptive attitude control for large-angle slew manoeuvres.	Autom.	1986	DBLP DOI BibTeX RDF
12	Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs	RDE-based transistor-level gate simulation for statistical static timing analysis.	DAC	2010	DBLP DOI BibTeX RDF	non-Monte Carlo, transistor-level modeling, statistical static timing analysis
12	Abhishek A. Sinkar, Nam Sung Kim	Analyzing potential power reduction with adaptive voltage positioning optimized for multicore processors.	ISLPED	2009	DBLP DOI BibTeX RDF	adaptive voltage positioning, multicore processor
12	Pinaki Mazumder	Disruptive technologies and neurally-inspired architectures.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	glsvlsi 2009 invited talk
12	Ali Dasdan, Santanu Kolay, Mustafa Yazgan	Derating for static timing analysis: Theory and practice.	ISQED	2009	DBLP DOI BibTeX RDF
12	Kwangok Jeong, Andrew B. Kahng, Hailong Yao	Revisiting the linear programming framework for leakage power vs. performance optimization.	ISQED	2009	DBLP DOI BibTeX RDF
12	Nagendra Krishnapura, Shanthi Pavan	Negative Feedback System and Circuit Design.	VLSI Design	2009	DBLP DOI BibTeX RDF
12	Jaime Ramírez-Angulo, Ramón González Carvajal, Antonio J. López-Martín	Techniques for the Design of Low Voltage Power Efficient Analog and Mixed Signal Circuits.	VLSI Design	2009	DBLP DOI BibTeX RDF
12	Maik Nijhuis, Herbert Bos, Henri E. Bal, Cédric Augonnet	Mapping and Synchronizing Streaming Applications on Cell Processors.	HiPEAC	2009	DBLP DOI BibTeX RDF
12	Sari Onaissi, Farid N. Najm	A Linear-Time Approach for Static Timing Analysis Covering All Process Corners.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
12	Vaddadi P. Chandu, Karandeep Singh	A Model for Multiplayer Interactive Games in Cellular Wireless Environment.	Innovative Techniques in Instruction Technology, E-learning, E-assessment, and Education	2008	DBLP DOI BibTeX RDF
12	Sean X. Shi, Anand Ramalingam, Daifeng Wang, David Z. Pan	Latch Modeling for Statistical Timing Analysis.	DATE	2008	DBLP DOI BibTeX RDF
12	Tao Luo 0002, David Newmark, David Z. Pan	Total power optimization combining placement, sizing and multi-Vt through slack distribution management.	ASP-DAC	2008	DBLP DOI BibTeX RDF
12	Seulki Lee, Jerald Yoo, Hoi-Jun Yoo	A 200Mbps 0.02nJ/b dual-mode inductive coupling transceiver for cm-range interconnection.	ISCAS	2008	DBLP DOI BibTeX RDF
12	Weixun Yan, Robert Kolm, Horst Zimmermann	Efficient four-stage frequency compensation for low-voltage amplifiers.	ISCAS	2008	DBLP DOI BibTeX RDF
12	Sachin Shrivastava, Harindranath Parameswaran	Statistical Crosstalk Noise Analysis Using First Order Parameterized Approach for Aggressor Grouping.	ISQED	2008	DBLP DOI BibTeX RDF	statistical crosstalk, aggressor grouping
12	Xin Wang, Alireza Kasnavi, Harold Levy	An Efficient Method for Fast Delay and SI Calculation Using Current Source Models.	ISQED	2008	DBLP DOI BibTeX RDF	Delay calculation, gate-level analysis, transient simulation, SI
12	Vineeth Veetil, Dennis Sylvester, David T. Blaauw	Fast and Accurate Waveform Analysis with Current Source Models.	ISQED	2008	DBLP DOI BibTeX RDF	weibull, bicubic spline, current source model
12	Savithri Sundareswaran, Jacob A. Abraham, Alexandre Ardelea, Rajendran Panda	Characterization of Standard Cells for Intra-Cell Mismatch Variations.	ISQED	2008	DBLP DOI BibTeX RDF	Statistical Characterization, Intra-Cell Variations, Random Variations, Mismatch Variations
12	Gerald Bortis	Experiences with Mirth: an open source health care integration engine.	ICSE	2008	DBLP DOI BibTeX RDF	health care integration, software architecture, middleware
12	Chih-Wen Lu, Yen-Chih Shen, Meng-Lieh Sheu	A high-driving class-AB buffer amplifier with a new pseudo source follower.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
12	Run Chen, Liyuan Liu, Dongmei Li, Zhihua Wang 0001	Full custom design of a three-stage amplifier with 5500MHz·pF/mW Performance in 0.18 mum CMO S.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
12	Haoxing Ren, David Z. Pan, Charles J. Alpert, Gi-Joon Nam, Paul G. Villarrubia	Hippocrates: First-Do-No-Harm Detailed Placement.	ASP-DAC	2007	DBLP DOI BibTeX RDF	synthesis optimizations, Hippocrates, first-do-no-harm detailed placement, pin-based timing constraint, electrical constraints, reduced wire-length
12	Mark Peters, Anthony Man-Cho So, Yinyu Ye 0001	Pari-Mutuel Markets: Mechanisms and Performance.	WINE	2007	DBLP DOI BibTeX RDF
12	Gianluca Giustolisi	Two-Stage OTA Design Based on Settling-Time Constraints.	ISCAS	2007	DBLP DOI BibTeX RDF
12	Mike Bichan, Anthony Chan Carusone	Crosstalk-Aware Transmitter Pulse-Shaping for Parallel Chip-to-Chip Links.	ISCAS	2007	DBLP DOI BibTeX RDF
12	Jingjing Hu, Johan H. Huijsing, Kofi A. A. Makinwa	A Three-Stage Amplifier with Quenched Multipath Frequency Compensation for All Capacitive Loads.	ISCAS	2007	DBLP DOI BibTeX RDF
12	Ram Dantu, Prakash Kolan, Robert Akl, Kall Loper	Classification of Attributes and Behavior in Risk Management Using Bayesian Networks.	ISI	2007	DBLP DOI BibTeX RDF
12	Jens Vygen	Slack in static timing analysis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
12	Kanak Agarwal, Mridul Agarwal, Dennis Sylvester, David T. Blaauw	Statistical interconnect metrics for physical-design optimization.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
12	Yang Fang, Xiaobo Tan	A Dynamic JKR Model with Application to Vibrational Release in Micromanipulation.	IROS	2006	DBLP DOI BibTeX RDF
12	Naoaki Ohkubo, Kimiyoshi Usami	Delay modeling and static timing analysis for MTCMOS circuits.	ASP-DAC	2006	DBLP DOI BibTeX RDF	interpolation., selective-MT, delay, leakage power, static timing analysis, MTCMOS
12	Fabio Lacerda, Stefano Pietri, Alfredo Olmos	A differential switched-capacitor amplifier with programmable gain and output offset voltage.	SBCCI	2006	DBLP DOI BibTeX RDF	differential to single ended, switched capacitor stage, analog integrated circuits
12	Lukas Fujcik, Jiri Haze, Radimir Vrba, Thibault Mougel	Modeling and design of novel architecture of multibit switched-capacitor sigma-delta converter with two-step quantization process.	ICN/ICONS/MCL	2006	DBLP DOI BibTeX RDF
12	Zhanyuan Jiang, Shiyan Hu, Jiang Hu, Zhuo Li 0001, Weiping Shi	A new RLC buffer insertion algorithm.	ICCAD	2006	DBLP DOI BibTeX RDF
12	Anas A. Hamoui, T. Alhajj, Mohammad Taherzadeh-Sani	Behavioral modeling of Opamp gain and dynamic effectsfor power optimization of Delta-Sigma modulators and pipelined ADCs.	ISLPED	2006	DBLP DOI BibTeX RDF	sigma-delta (??) modulation, synthesis, behavioral modeling, discrete-time systems, analog-to-digital conversion
12	Alexey Teplinsky, Raymond Flynn, Orla Feely	Limit cycles in bang-bang phase-locked loops.	ISCAS	2006	DBLP DOI BibTeX RDF
12	Yasutaka Haga, Richard C. S. Morling, Izzet Kale	A new bulk-driven input stage design for sub 1-volt CMOS op-amps.	ISCAS	2006	DBLP DOI BibTeX RDF
12	Mona Safi-Harb, Gordon W. Roberts	A CMOS circuit for embedded GHz measurement of digital signal rise time degradation.	ISCAS	2006	DBLP DOI BibTeX RDF
12	Hanif Fatemi, Soroush Abbaspour, Massoud Pedram, Amir H. Ajami, Emre Tuncer	SACI: statistical static timing analysis of coupled interconnects.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	coupled interconnect, sources of variation, crosstalk noise, statistical timing analysis
12	Roopak Suri, C. M. Markan	Threshold Trimming Based Design of a CMOS Programmable Operational Amplifier.	VLSI Design	2006	DBLP DOI BibTeX RDF
12	Kornika Moolpho, Jitkasame Ngarmnil	Low Voltage High-Performance Class-AB FGMOS Buffer.	APCCAS	2006	DBLP DOI BibTeX RDF
12	Tao Luo 0002, David Newmark, David Z. Pan	A new LP based incremental timing driven placement for high performance designs.	DAC	2006	DBLP DOI BibTeX RDF
12	Hamid Hatamkhani, Frank Lambrecht, Vladimir Stojanovic, Chih-Kong Ken Yang	Power-centric design of high-speed I/Os.	DAC	2006	DBLP DOI BibTeX RDF	serial link, convex optimization, I/O, power minimization, channel model
12	Yu Cao 0001, Xuejue Huang, Dennis Sylvester, Tsu-Jae King 0001, Chenming Hu	Impact of on-chip interconnect frequency-dependent R(f)L(f) on digital and RF design.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
12	Timothy M. Chan	On Levels in Arrangements of Curves, II: A Simple Inequality and Its Consequences.	Discret. Comput. Geom.	2005	DBLP DOI BibTeX RDF
12	Flavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner	Two-Phase Clocking and a New Latch Design for Low-Power Portable Applications.	PATMOS	2005	DBLP DOI BibTeX RDF
12	Paolo Ferragina, Fabrizio Luccio, Giovanni Manzini, S. Muthukrishnan 0001	Structuring labeled trees for optimal succinctness, and beyond.	FOCS	2005	DBLP DOI BibTeX RDF
12	Kalle Folkesson, Christer Svensson, B. Knuthammar, A. Dreyfert	A high-level dynamic-error model of a pipelined analog-to-digital converter.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
12	Brock J. LaMeres, Sunil P. Khatri	Performance model for inter-chip communication considering inductive cross-talk and cost.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
12	Shouli Yan, Jingyu Hu, Tongyu Song	Novel and robust constant-gm technique for rail-to-rail CMOS amplifier input stages.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
12	Kyung Ki Kim, Yong-Bin Kim, Fabrizio Lombardi	Data Dependent Jitter (DDJ) Characterization Methodology.	DFT	2005	DBLP DOI BibTeX RDF
12	Puneet Gupta 0001, Andrew B. Kahng, Puneet Sharma	A Practical Transistor-Level Dual Threshold Voltage Assignment Methodology.	ISQED	2005	DBLP DOI BibTeX RDF
12	Chung-Kuan Tsai, Malgorzata Marek-Sadowska	An Interconnect Insensitive Linear Time-Varying Driver Model for Static Timing Analysis.	ISQED	2005	DBLP DOI BibTeX RDF
12	Ram Dantu, Prakash Kolan	Risk Management Using Behavior Based Bayesian Networks.	ISI	2005	DBLP DOI BibTeX RDF
12	Hiran Tennakoon, Carl Sechen	Efficient and accurate gate sizing with piecewise convex delay models.	DAC	2005	DBLP DOI BibTeX RDF	piecewise convex, optimization, Lagrangian relaxation, gate sizing, delay modeling
12	Lakshmi Kalpana Vakati, Janet Meiling Wang	A new multi-ramp driver model with RLC interconnect load.	ISPD	2004	DBLP DOI BibTeX RDF	inductance criteria, multi-ramp driver model, transmission line effects, interconnect modeling, effective capacitance
12	Nima Maghari, Mohammad Yavari, Omid Shoaei	An analytical model for the slewing behavior of CMOS two-stage operational transconductance amplifiers.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
12	Walter Aloisi, Stello Matteo Billé, Gaetano Palumbo	Low-voltage linear voltage regulator suitable for memories.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
12	Friedel Gerfers, Maurits Ortmanns, Yiannos Manoli	Design issues and performance limitations of a clock jitter insensitive multibit DAC architecture for high-performance low-power CT Sigma Delta modulators.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
12	Amr A. Tammam, Khaled Hayatleh, Bryan L. Hart, F. John Lidgey	High performance current-feedback op-amps.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
12	Mohammad Taherzadeh-Sani, Reza Lotfi, Omid Shoaei	A pseudo-class-AB telescopic-cascode operational amplifier.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
12	Ram Dantu, Kall Loper, Prakash Kolan	Risk Management using Behavior based Attack Graphs.	ITCC (1)	2004	DBLP DOI BibTeX RDF
12	Richard Goldman, Kurt Keutzer, Clive Bittlestone, Ahsan Bootehsaz, Shekhar Y. Borkar, E. Chen, Louis Scheffer, Chandramouli Visweswariah	Is statistical timing statistically significant?	DAC	2004	DBLP DOI BibTeX RDF
12	Yatin Chawathe	Scattercast: an adaptable broadcast distribution framework.	Multim. Syst.	2003	DBLP DOI BibTeX RDF	Scattercast, Overlay networks, Content distribution, Application-layer multicast
12	Wen-Tsong Shiue, Weetit Wanalertlak	Advanced Cell Modeling Techniques Based on Polynomial Expressions.	PATMOS	2003	DBLP DOI BibTeX RDF
12	Timothy M. Chan	On Levels in Arrangements of Curves, II: A Simple Inequality and Its Consequences.	FOCS	2003	DBLP DOI BibTeX RDF
12	Salvador Pinillos Gimenez, Marcelo Antonio Pavanello, João Antonio Martino, Stephane Adriaensen, Denis Flandre	Design of Operational Transconductance Amplifiers with Improved Gain by Using Graded-Channel SOI nMOSFETs.	SBCCI	2003	DBLP DOI BibTeX RDF
12	Masanori Hashimoto, Yuji Yamada, Hidetoshi Onodera	Capturing crosstalk-induced waveform for accurate static timing analysis.	ISPD	2003	DBLP DOI BibTeX RDF	capacitive coupling noise, delay calculation, slope propagation, static timing analysis, crosstalk noise
12	Shidhartha Das, Kanak Agarwal, David T. Blaauw, Dennis Sylvester	Optimal Inductance for On-chip RLC Interconnections.	ICCD	2003	DBLP DOI BibTeX RDF
12	Gerry Quilligan, D. P. Burton	A 0.35µm CMOS voltage derivative sensor with sign and inflection outputs.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
12	Haibin Huang, Ezz I. El-Masry	A fast settling CMOS operational amplifier.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
12	Jozef Adut, José Silva-Martínez	Cascode transconductance amplifiers for HF switched-capacitor applications.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
12	Dirk Weiler, Ton J. J. van den Boom, Bedrich J. Hosticka	Resolution prediction for bandpass-Sigma-Delta-modulators using SIMULINK behavior simulation.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
12	Kelvin Ka Sing Leung, Henry Shu-Hung Chung, Ron Shu-Yuen Hui	Use of state trajectory prediction in hysteresis control for achieving fast transient response of the buck converter.	ISCAS (3)	2003	DBLP DOI BibTeX RDF
12	Thilak Senanayake, Tamotsu Ninomiya	High-current clamp for fast-response load transitions of DC-DC converter.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
12	Gianluca Giustolisi, Gaetano Palumbo	A novel 1-V class-AB transconductor for improving speed performance in SC applications.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
12	M. Pauli, M. C. Ertem, E. Heidhausen	Quick Response Airborne Deployment of Viper Muzzle Flash Detection and Location System During DC Sniper Attacks.	AIPR	2003	DBLP DOI BibTeX RDF
12	José Luis Rosselló, Jaume Segura 0001	Charge-based analytical model for the evaluation of powerconsumption in submicron CMOS buffers.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
12	Guy G. Lemieux, David M. Lewis	Circuit design of routing switches.	FPGA	2002	DBLP DOI BibTeX RDF
12	Hiran Tennakoon, Carl Sechen	Gate sizing using Lagrangian relaxation combined with a fast gradient-based pre-processing step.	ICCAD	2002	DBLP DOI BibTeX RDF
12	Christopher R. Wagner, Susan J. Lederman, Robert D. Howe	A Tactile Shape Display Using RC Servomotors.	Symposium on Haptic Interfaces for Virtual Environment and Teleoperator Systems	2002	DBLP DOI BibTeX RDF	tactile shape display, spatially distributed forces, taction, teletaction, mechanical pin, fingertip, servo, rc servo, servomotor, tactile array, haptics, tactile display
12	Li Ding 0002, Pinaki Mazumder, David T. Blaauw	Crosstalk noise estimation using effective coupling capacitance.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
12	Robert M. Fox, Inchang Seo, Hyeopgoo Yeo, Okjune Jeon	Leveraged current mirror op amp.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
12	Xiaoliang Bai, Chandramouli Visweswariah, Philip N. Strenski	Uncertainty-aware circuit optimization.	DAC	2002	DBLP DOI BibTeX RDF	small uncertainty, optimization, process variation, nonlinear, performance optimization, transistor sizing, circuit tuning
12	Yehea I. Ismail, Eby G. Friedman, José Luis Neves	Exploiting the on-chip inductance in high-speed clock distribution networks.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
12	José Vicente Calvano, Antonio Carneiro de Mesquita Filho, Vladimir Castro Alves, Marcelo Lubaszewski	Fault Models and Test Generation for OpAmp Circuits - The FFM.	J. Electron. Test.	2001	DBLP DOI BibTeX RDF	test generation, fault model, analog test, operational amplifiers
12	Giuseppe Palmisano, Salvatore Pennisi	Low-voltage continuous-time CMOS current amplifier with dynamic biasing.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
12	Amir Hossein Nejad-Malayeri, Tajinder Manku	A 270 MHz, 1.8 V fully differential CMOS operational amplifier for switched capacitor channel select filters in wide-band wireless applications.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
12	Alex Doboli, Ranga Vemuri	Hierarchical performance optimization for synthesis of linear analog systems.	ISCAS (5)	2001	DBLP DOI BibTeX RDF
12	Rohit Khare	Seventh Heaven - How Functions: Transcending the Web as GUI, Part I.	IEEE Internet Comput.	2000	DBLP DOI BibTeX RDF
12	Kamlesh Rath	Broadband Networks.	IEEE Multim.	2000	DBLP DOI BibTeX RDF