Search results for "switch"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
25	Steven G. McDonagh, Benjamin Hou, Amir Alansary, Ozan Oktay, Konstantinos Kamnitsas, Mary A. Rutherford, Joseph V. Hajnal, Bernhard Kainz	Context-Sensitive Super-Resolution for Fast Fetal Magnetic Resonance Imaging.	CMMI/RAMBO/SWITCH@MICCAI	2017	DBLP DOI BibTeX RDF
25	Serkan Çimen, Mathias Unberath, Alejandro F. Frangi, Andreas K. Maier	CoronARe: A Coronary Artery Reconstruction Challenge.	CMMI/RAMBO/SWITCH@MICCAI	2017	DBLP DOI BibTeX RDF
25	Nicolas Basty, Darryl McClymont, Irvin Teh, Jürgen E. Schneider, Vicente Grau	Reconstruction of 3D Cardiac MR Images from 2D Slices Using Directional Total Variation.	CMMI/RAMBO/SWITCH@MICCAI	2017	DBLP DOI BibTeX RDF
25	Yiming Xiao, Ali Alamer, Vladimir S. Fonov, Benjamin W. Y. Lo, Donatella Tampieri, D. Louis Collins, Hassan Rivaz, Marta Kersten-Oertel	Towards Automatic Collateral Circulation Score Evaluation in Ischemic Stroke Using Image Decompositions and Support Vector Machines.	CMMI/RAMBO/SWITCH@MICCAI	2017	DBLP DOI BibTeX RDF
25	Ninon Burgos, Jorge Samper-González, Anne Bertrand, Marie Odile Habert, Sébastien Ourselin, Stanley Durrleman, M. Jorge Cardoso, Olivier Colliot	Individual Analysis of Molecular Brain Imaging Data Through Automatic Identification of Abnormality Patterns.	CMMI/RAMBO/SWITCH@MICCAI	2017	DBLP DOI BibTeX RDF
25	Yipeng Hu, Eli Gibson, Li-Lin Lee, Weidi Xie, Dean C. Barratt, Tom Vercauteren, J. Alison Noble	Freehand Ultrasound Image Simulation with Spatially-Conditioned Generative Adversarial Networks.	CMMI/RAMBO/SWITCH@MICCAI	2017	DBLP DOI BibTeX RDF
25	Edward Ferdian, Anna M. M. Boers, Ludo F. M. Beenen, B. M. Cornelissen, Ivo G. H. Jansen, K. M. Treurniet, Jordi Borst, Charles B. L. M. Majoie, Henk A. Marquering	Automated Ventricular System Segmentation in CT Images of Deformed Brains Due to Ischemic and Subarachnoid Hemorrhagic Stroke.	CMMI/RAMBO/SWITCH@MICCAI	2017	DBLP DOI BibTeX RDF
25	Rosa-María Menchón-Lara, Javier Royuela-del-Val, Alejandro Godino-Moya, Lucilio Cordero-Grande, Federico Simmross-Wattenberg, Marcos Martín-Fernández, Carlos Alberola-López	An Efficient Multi-resolution Reconstruction Scheme with Motion Compensation for 5D Free-Breathing Whole-Heart MRI.	CMMI/RAMBO/SWITCH@MICCAI	2017	DBLP DOI BibTeX RDF
25	Cao-Dung Truong, Manh-Cuong Nguyen, Duy-Tien Le, Trung-Thanh Le	All-optical switch based on 1×3 multimode interference couplers.	Opt. Switch. Netw.	2016	DBLP DOI BibTeX RDF
25	Muhammad Imran 0016, Martin Collier, Pascal Landais, Kostas Katrinis	Performance evaluation of hybrid optical switch architecture for data center networks.	Opt. Switch. Netw.	2016	DBLP DOI BibTeX RDF
25	Ivan Plander, Michal Stepanovsky	Advanced three-dimensional MEMS photonic cross-connect switch for nonblocking all-optical networks.	Opt. Switch. Netw.	2016	DBLP DOI BibTeX RDF
25	Masoud Asghari, Akbar Ghaffarpour Rahbar	Contention avoidance in bufferless slotted optical packet switched networks with egress switch coordination.	Opt. Switch. Netw.	2015	DBLP DOI BibTeX RDF
25	Hung Nguyen Tan, Nattapong Kitsuwan, Motoharu Matsuura, Naoto Kishi, Eiji Oki	Demonstration of bufferless optical packet switch with recursive stages of parametric wavelength converter.	Opt. Switch. Netw.	2012	DBLP DOI BibTeX RDF
25	Yusuke Hirota, Shinya Yatsuo, Hideki Tode, Koso Murakami	Scheduling scheme using Look-ahead Buffer and Loop-back Buffer in Two-stage variable optical packet switch.	Opt. Switch. Netw.	2012	DBLP DOI BibTeX RDF
25	Kazumasa Tokuhashi, Kunitaka Ashizawa, Daisuke Ishii, Satoru Okamoto, Naoaki Yamanaka, Koji Wakayama, Keiichi Nashimoto	MPCP based active optical access network with PLZT high-speed optical switch.	Opt. Switch. Netw.	2012	DBLP DOI BibTeX RDF
25	Rajiv Srivastava, Vinamra Gupta, Yatindra Nath Singh	Gain dynamics of EDFA in loop buffer switch.	Opt. Switch. Netw.	2011	DBLP DOI BibTeX RDF
25	Ronelle Geldenhuys, Jacobus Stefanus van der Merwe, Kornkamol Thakulsukanant, Zhuoran Wang, Nan Chi, Siyuan Yu	Contention resolution and variable length optical packet switching using the active vertical-coupler-based optical Crosspoint switch.	Opt. Switch. Netw.	2011	DBLP DOI BibTeX RDF
25	Rajiv Srivastava, Yatindra Nath Singh	Feedback fiber delay lines and AWG based optical packet switch architecture.	Opt. Switch. Netw.	2010	DBLP DOI BibTeX RDF
25	Kyriakos Vlachos, Kostas Ramantas	A non-competing hybrid optical burst switch architecture for QoS differentiation.	Opt. Switch. Netw.	2008	DBLP DOI BibTeX RDF
25	Satoshi Yoshima, Naoya Wada, Gabriella Cincotti, Tetsuya Miyazaki, Ken-ichi Kitayama	Multicast-capable optical-code label packet switch: Proposal and its experimental demonstration.	Opt. Switch. Netw.	2008	DBLP DOI BibTeX RDF
25	Neha Sharma 0002, Devi Chadha, Vinod S. S. Chandra	The augmented data vortex switch fabric: An all-optical packet switched interconnection network with enhanced fault tolerance.	Opt. Switch. Netw.	2007	DBLP DOI BibTeX RDF
25	Neha Sharma 0002, Devi Chadha, Vinod S. S. Chandra	Performance evaluation of the augmented data vortex switch fabric: An all-optical packet switched interconnection network.	Opt. Switch. Netw.	2007	DBLP DOI BibTeX RDF
25	Crispín Gómez Requena, María Engracia Gómez, Pedro López 0001, José Duato	Reducing Packet Dropping in a Bufferless NoC.	Euro-Par	2008	DBLP DOI BibTeX RDF
25	Crispín Gómez Requena, María Engracia Gómez, Pedro Juan López Rodríguez, José Duato	An Efficient Switching Technique for NoCs with Reduced Buffer Requirements.	ICPADS	2008	DBLP DOI BibTeX RDF
25	Hans Eberle, Pedro Javier García, José Flich, José Duato, Robert J. Drost, Nils Gura, David Hopkins 0001, Wladek Olesinski	High-radix crossbar switches enabled by proximity communication.	SC	2008	DBLP DOI BibTeX RDF
25	Mahshid Sedghi, Elnaz Koopahi, Armin Alaghi, Mahmood Fathy, Zainalabedin Navabi	An NoC Test Strategy Based on Flooding with Power, Test Time and Coverage Considerations.	VLSI Design	2008	DBLP DOI BibTeX RDF
25	Ge Nong, Ning Situ, Mounir Hamdi	Delay Analysis of Combined Input-Crosspoint Queueing Switches.	ICCCN	2007	DBLP DOI BibTeX RDF
25	Rahul Ratan, Manish Kumar Shukla, A. Yavuz Oruç	Quantum Switching Networks with Classical Routing.	CISS	2007	DBLP DOI BibTeX RDF
25	Claus Bauer	Low complexity, stable scheduling algorithms for networks of input queued switches with no or very low speed-up.	Comput. Commun. Rev.	2006	DBLP DOI BibTeX RDF	modeling of communication networks, stability, scheduling algorithms
25	Michael Rosenblum, Constantine Caramanis, Michel X. Goemans, Vahid Tarokh	Approximating fluid schedules in crossbar packet-switches and Banyan networks.	IEEE/ACM Trans. Netw.	2006	DBLP DOI BibTeX RDF	scheduling, graph theory, packet-switching, network calculus, combinatorics
25	Tao Zhang 0043, Kejie Lu, Jason P. Jue	Shared fiber delay line buffers in asynchronous optical packet switches.	IEEE J. Sel. Areas Commun.	2006	DBLP DOI BibTeX RDF
25	Krishna V. Palem	Energy Aware Computing through Probabilistic Switching: A Study of Limits.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	low-power design, Energy-aware systems, probabilistic computation
25	Claus Bauer	Approximations to Maximum Weight Matching Scheduling Algorithms of Low Complexity.	AICT/SAPIR/ELETE	2005	DBLP DOI BibTeX RDF
25	Andrea Lodi 0002, Roberto Giansante, Carlo Chiesa, Luca Ciccarelli, Fabio Campi, Mario Toma	Compact Buffered Routing Architecture.	FPL	2004	DBLP DOI BibTeX RDF
25	Xiaotong Zhuang, Santosh Pande	Balancing register allocation across threads for a multithreaded network processor.	PLDI	2004	DBLP DOI BibTeX RDF	register allocation, network processor, multithreaded processor
25	David W. Weir, Michael A. Peshkin, J. Edward Colgate, Pietro Buttolo, James Rankin, Matthew Johnston	The Haptic Profile: Capturing the Feel of Switches.	HAPTICS	2004	DBLP DOI BibTeX RDF
25	Dan Guez, Alexander Kesselman, Adi Rosén	Packet-mode policies for input-queued switches.	SPAA	2004	DBLP DOI BibTeX RDF	packet-mode scheduling, competitive analysis, input-queued switches
25	Somdip Datta, Subir K. Biswas, Sudipta Sengupta, Debanjan Saha	Routing and Grooming in Two-Tier Survivable Optical Mesh Networks.	IWQoS	2003	DBLP DOI BibTeX RDF
25	Pablo Pavón-Mariño, Joan García-Haro, Josemaria Malgosa-Sanahuja, Fernando Cerdán	Optical Packet Switching Fabrics Comparison under SCWP/SHWP Operational Modes.	ISCC	2003	DBLP DOI BibTeX RDF
25	Murat R. Becer, Ibrahim N. Hajj	An Analytical Model for Delay and Crosstalk Estimation with Application to Decoupling.	ISQED	2000	DBLP DOI BibTeX RDF	delay, analytical model, decoupling, Crosstalk noise
25	Zhen Liu 0001, Philippe Nain, Donald F. Towsley	On optimal polling policies.	Queueing Syst. Theory Appl.	1992	DBLP DOI BibTeX RDF	polling policy, optimal stochastic scheduling, coupling, Polling system, stochastic ordering
24	Yi Zhu 0002, Yuanfang Hu, Michael B. Taylor, Chung-Kuan Cheng	Energy and switch area optimizations for FPGA global routing architectures.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	FPGA, low power, global routing
24	Edgar G. Daylight, Sandeep K. Shukla	On the Difficulties of Concurrent-System Design, Illustrated with a 2×2 Switch Case Study.	FM	2009	DBLP DOI BibTeX RDF	adaptability, non-functional requirements, formal specification languages, local reasoning
24	Matías R. Miguez, Alfredo Arnaud, Joel Gak	A self-protected integrated switch in a HV technology.	SBCCI	2009	DBLP DOI BibTeX RDF	design, drivers
24	Shu Li, Tong Zhang 0002	Exploratory study on circuit and architecture design of very high density diode-switch phase change memories.	ISQED	2009	DBLP DOI BibTeX RDF
24	Aman Gayasen, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Arifur Rahman	Designing a 3-D FPGA: Switch Box Architecture and Thermal Issues.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
24	Gong Chen, Liu Qi, Huijuan Cui, Kun Tang	Switch-Type Hybrid Hard Decision Decoding Algorithms for Regular Low-Density Parity-Check Codes.	IEEE Trans. Inf. Theory	2008	DBLP DOI BibTeX RDF
24	Dongpil Chang, Yunseop Noh, Inbok Yom	Design of High Performance HEMT Switch for S-band MSM of Satellite Transponder.	VTC Spring	2008	DBLP DOI BibTeX RDF
24	Ling Wu, Cheng Li 0005	Performance Modeling of a Reconfigurable Shared Buffer for High-Speed Switch/Router.	ICC	2008	DBLP DOI BibTeX RDF
24	Tetsuro Ueda, Kazunori Takeuchi, Shoji Kaneko, Shingo Nomura	Dynamic Base Station Relocation in Cognitive Mesh Networks Using Packet Switch.	WCNC	2008	DBLP DOI BibTeX RDF
24	Yu-Hao Hsu, Ming-Hao Lu, Ping-Ling Yang, Fanta Chen, You-Hung Li, Min-Sheng Kao, Chih-Hsing Lin, Ching-Te Chiu, Jen-Ming Wu, Shuo-Hung Hsu, Yarsun Hsu	A 28Gbps 4×4 switch with low jitter SerDes using area-saving RF model in 0.13µm CMOS technology.	ISCAS	2008	DBLP DOI BibTeX RDF
24	Dong Tang, William Bryson, Richard Elling	RAS Modeling of an HPC Switch System.	PRDC	2008	DBLP DOI BibTeX RDF
24	Jad Naous, David Erickson, G. Adam Covington, Guido Appenzeller, Nick McKeown	Implementing an OpenFlow switch on the NetFPGA platform.	ANCS	2008	DBLP DOI BibTeX RDF	flow switching, computer networks, packet switching, programmable networks, OpenFlow, NetFPGA
24	Lei Shi 0002, Gao Xia, Bin Liu 0001	Performance Guarantees for Flow-Mapping Parallel Packet Switch.	IPCCC	2007	DBLP DOI BibTeX RDF
24	Retdian Agung Nicodimus, Shigetaka Takagi, Nobuo Fujii	Improvement of Bootstrapped Switch using Track and Precharge Phase.	ISCAS	2007	DBLP DOI BibTeX RDF
24	Li Song, Aijun Liu, Yifei Ma	An On-board Switch Scheme Based on DiffServ.	SERA	2007	DBLP DOI BibTeX RDF
24	Zhendong Gao, Jianbo Su	Switch Images Based on Fusion in Uncalibrated Visual Servoing.	IROS	2006	DBLP DOI BibTeX RDF
24	Kypros Constantinides, Stephen Plaza, Jason A. Blome, Bin Zhang 0011, Valeria Bertacco, Scott A. Mahlke, Todd M. Austin, Michael Orshansky	BulletProof: a defect-tolerant CMP switch architecture.	HPCA	2006	DBLP DOI BibTeX RDF
24	Koichi Ishida, Atit Tamtrakarn, Takayasu Sakurai	A 0.5-V sigma-delta modulator using analog T-switch scheme for the subthreshold leakage suppression.	ASP-DAC	2006	DBLP DOI BibTeX RDF
24	Ling Wang, Tong Shao, Shumei Wang, Gongxuan Zhang	An Apparatus Realizing Switch of Computing Device Status.	IMSCCS (1)	2006	DBLP DOI BibTeX RDF	Computing device, multi operating systems, isolation
24	Itamar Elhanany, Derek Chiou, Vahid Tabatabaee, Raffaele Noro, Ali Poursepanj	The Network Processing Forum switch fabric benchmark specifications: an overview.	IEEE Netw.	2005	DBLP DOI BibTeX RDF
24	Ho-Ting Wu, Kai-Wei Ke, Wang-Rong Chang, Hui-Tang Lin	A switched delay line based optical switch architecture with a bypass line.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
24	Christian Jesús B. Fayomi, Gordon W. Roberts, Mohamad Sawan	Low-voltage CMOS analog bootstrapped switch for sample-and-hold circuit: design and chip characterization.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
24	Kenji Yoshigoe	Rate-based Flow-control for the CICQ Switch.	LCN	2005	DBLP DOI BibTeX RDF
24	Carlos Roberto dos Santos, Shusaburo Motoyama	A QoS Provisioned CIOQ Packet Switch Using Crossbar Structure with m Internal Links.	Systems Communications	2005	DBLP DOI BibTeX RDF
24	Shuo-Yen Robert Li, Xuesong Tan	Theory on Switch Preservation under 2-stage Interconnection.	PDCAT	2005	DBLP DOI BibTeX RDF
24	Chan-Eun Rhee, Han-You Jeong, Soonhoi Ha	Many-to-Many Core-Switch Mapping in 2-D Mesh NoC Architectures.	ICCD	2004	DBLP DOI BibTeX RDF
24	Itamar Elhanany, Kurt Busch, Derek Chiou	Switch Fabric Interfaces.	Computer	2003	DBLP DOI BibTeX RDF
24	Steven P. Young, Peter Alfke, Colm Fewer, Scott McMillan, Brandon Blodget, Delon Levi	A High I/O Reconfigurable Crossbar Switch.	FCCM	2003	DBLP DOI BibTeX RDF
24	Honglin Wu, Amir Gourgy, Ted H. Szymanski	An Optoelectronic Multi-Terabit CMOS Switch Core for Local Area Networks.	LCN	2003	DBLP DOI BibTeX RDF
24	Indrani Paul, Sudhakar Yalamanchili, José Duato	Algorithms for Switch-Scheduling in the Multimedia Router for LANs.	HiPC	2002	DBLP DOI BibTeX RDF
24	Tadashi Suetsugu, Marian K. Kazimierczuk	Voltage-clamped class E amplifier with a Zener diode across the switch.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
24	Terry Tao Ye, Giovanni De Micheli, Luca Benini	Analysis of power consumption on switch fabrics in network routers.	DAC	2002	DBLP DOI BibTeX RDF	interconnect networks, systems on chip, networks on chip, power consumption
24	Sema F. Oktug	A Multicast ATM Switch Based on PIPN.	ICN (2)	2001	DBLP DOI BibTeX RDF
24	Mohamed Escheikh, Kamel Barkaoui, Ammar Bouallegue	Performance Analysis of an N(N ATM Switch with Markov Modulated Poisson Process under Back-Pressure Mechanism.	MASCOTS	2000	DBLP DOI BibTeX RDF
24	Venkatram Krishnaswamy, Jeremy Casas, Thomas Tetzlaff	A switch level fault simulation environment.	DAC	2000	DBLP DOI BibTeX RDF
24	Sofiène Tahar, Xiaoyu Song, Eduard Cerny, Zijian Zhou 0001, Michel Langevin, Otmane Aït Mohamed	Modeling and formal verification of the Fairisle ATM switch fabricusing MDGs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
24	Moustafa A. Youssef 0001, Mohamed N. El-Derini, Hussein H. Aly	Structure and Performance Evaluation of a Replicated Banyan Network Based ATM Switch.	ISCC	1999	DBLP DOI BibTeX RDF	replicated networks, ATM switching, banyan networks
24	Salvador Mir, Adoración Rueda, Diego Vázquez, José Luis Huertas	Switch-Level Fault Coverage Analysis for Switched-Capacitor Systems.	DATE	1998	DBLP DOI BibTeX RDF
24	Bobby Vandalore, Sonia Fahmy, Raj Jain, Rohit Goyal, Mukul Goyal	A Definition of General Weighted Fairness and its Support in Explicit Rate Switch Algorithms.	ICNP	1998	DBLP DOI BibTeX RDF
24	Peter Dahlgren	Switch-level bridging fault simulation in the presence of feedbacks.	ITC	1998	DBLP DOI BibTeX RDF
24	Mike Parks	A Modular Element for Shared Buffer ATM Switch Fabrics.	ASAP	1997	DBLP DOI BibTeX RDF
24	Pierre Plaza, Luis A. Merayo, Juan Carlos Diaz, José Luis Conesa	A 2.5 Gb/s ATM switch chip set.	IEEE Trans. Very Large Scale Integr. Syst.	1996	DBLP DOI BibTeX RDF
24	Byungho Kim, Boseob Kwon, Jinchun Kim, Hyunsoo Yoon, Jung Wan Cho	Performance analysis of an ATM switch with multiple paths.	ICNP	1995	DBLP DOI BibTeX RDF
24	Mazin S. Yousif, Chita R. Das	A Switch Cache Design for MIN-Based Shared-Memory Multiprocessors.	CONPAR	1994	DBLP DOI BibTeX RDF
24	Andrew T. Yang, Yu-Hsu Chang, Daniel G. Saab, Ibrahim N. Hajj	Switch-level timing simulation of bipolar ECL circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
24	Reiner Hähnle, Werner Kernig	Verification of Switch-Level Designs with Many-Valued Logic.	LPAR	1993	DBLP DOI BibTeX RDF
24	Eduard Cerny, John P. Hayes, Nicholas C. Rumin	Accuracy of magnitude-class calculations in switch-level modeling.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
24	Chun-Hung Chen, Jacob A. Abraham	Generation and evaluation of current and logic tests for switch-level sequential circuits.	J. Electron. Test.	1992	DBLP DOI BibTeX RDF	logic tests, test generation, Current tests, I DDQ
24	Saul A. Kravitz, Randal E. Bryant, Rob A. Rutenbar	Massively parallel switch-level simulation: a feasibility study.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
24	Dan Adler	Switch-level simulation using dynamic graph algorithms.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
24	Prathima Agrawal, Scott H. Robinson, Thomas G. Szymanski	Automatic modeling of switch-level networks using partial orders [MOS circuits].	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
24	Steven P. Smith, Ramón D. Acosta	A Value System for Switch-Level Modeling.	IEEE Des. Test Comput.	1990	DBLP DOI BibTeX RDF
24	Rochit Rajsuman, Yashwant K. Malaiya, Anura P. Jayasumana	Limitations of switch level analysis for bridging faults.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
24	Haim E. Mizrahi, Jean-Loup Baer, Edward D. Lazowska, John Zahorjan	Introducing Memory into Switch Elements of Multiprocessor Interconnection Networks.	ISCA	1989	DBLP DOI BibTeX RDF
24	Saul A. Kravitz, Randal E. Bryant, Rob A. Rutenbar	Massively Parallel Switch-Level Simulation: A Feasibility Study.	DAC	1989	DBLP DOI BibTeX RDF
24	Genhong Ruan, Jirí Vlach, James A. Barby	Current-limited switch-level timing simulator for MOS logic networks.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
24	Christer Svensson, Robert Tjärnström	Switch-level simulation and the pass transistor EXOR gate.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
23	Nick McKeown	The iSLIP scheduling algorithm for input-queued switches.	IEEE/ACM Trans. Netw.	1999	DBLP DOI BibTeX RDF	scheduling, IP, ATM switch, crossbar switch, IP router, input-queueing
23	Marco Ajmone Marsan, Rossano Gaeta	Modeling ATMsystems with GSPNs and SWNs.	SIGMETRICS Perform. Evaluation Rev.	1998	DBLP DOI BibTeX RDF	Gauss switch, SWN, knockout switch, ATM, LAN, ABR, GSPN