Search results for "timing"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
23	Christophe Alexandre, Marek Sroka, Hugo Clément, Christian Masson	Zephyr: A Static Timing Analyzer Integrated in a Trans-hierarchical Refinement Design Flow.	PATMOS	2006	DBLP DOI BibTeX RDF
23	Daniel Lima Ferrão, Ricardo Reis 0001, José Luís Almada Güntzel	Considering Zero-Arrival Time and Block-Arrival Time in Hierarchical Functional Timing Analysis.	PATMOS	2006	DBLP DOI BibTeX RDF
23	Eduardo Tavares, Raimundo S. Barreto, Paulo Romero Martins Maciel, Meuse N. Oliveira Jr., Adilson Arcoverde, Gabriel Alves, Ricardo Massa Ferreira Lima, Leonardo Barros, Arthur Bessa	An Integrated Environment for Embedded Hard Real-Time Systems Scheduling with Timing and Energy Constraints.	PATMOS	2005	DBLP DOI BibTeX RDF
23	Nick Kanopoulos	Design Methodology for Rapid Development of SoC ICs Based on an Innovative System Architecture with Emphasis to Timing Closure and Power Consumption Optimization.	PATMOS	2004	DBLP DOI BibTeX RDF
23	Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang	Timing constraints for domino logic gates with timing-dependent keepers.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
23	Tod Amon, Gaetano Borriello, Taokuan Hu, Jiwen Liu	Symbolic Timing Verification of Timing Diagrams using Presburger Formulas.	DAC	1997	DBLP DOI BibTeX RDF
23	Jin-Tai Yan, Zhi-Wei Chen	Resource-constrained timing-driven link insertion for critical delay reduction.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	critical delay, link insertion, non-tree
23	Lin Xie, Azadeh Davoodi	Representative path selection for post-silicon timing prediction under variability.	DAC	2010	DBLP DOI BibTeX RDF	process variations, post-silicon validation
23	Takashi Enami, Shinyu Ninomiya, Masanori Hashimoto	Statistical Timing Analysis Considering Spatially and Temporally Correlated Dynamic Power Supply Noise.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2009	DBLP DOI BibTeX RDF
23	Minxue Pan, Lei Bu, Xuandong Li	TASS: Timing Analyzer of Scenario-Based Specifications.	CAV	2009	DBLP DOI BibTeX RDF
23	HaNeul Chon, Taewhan Kim	Timing variation-aware task scheduling and binding for MPSoC.	ASP-DAC	2009	DBLP DOI BibTeX RDF
23	Yi Wang, Ping Chen 0003, Yi Ge, Bing Mao, Li Xie 0001	Traffic Controller: A Practical Approach to Block Network Covert Timing Channel.	ARES	2009	DBLP DOI BibTeX RDF
23	Yunchuan Guo, Lihua Yin, Yuan Zhou, Chao Li 0027, Li Guo 0001	Simulation Analysis of Probabilistic Timing Covert Channels.	NAS	2009	DBLP DOI BibTeX RDF
23	Menguc Oner	On the effects of random timing jitter on spectrum sensing algorithms based on cyclostationarity.	CCECE	2009	DBLP DOI BibTeX RDF
23	Bart Coppens 0001, Ingrid Verbauwhede, Koen De Bosschere, Bjorn De Sutter	Practical Mitigations for Timing-Based Side-Channel Attacks on Modern x86 Processors.	SP	2009	DBLP DOI BibTeX RDF
23	Ramamurthy Vishweshwara, Ramakrishnan Venkatraman, H. Udayakumar, N. V. Arvind	An Approach to Measure the Performance Impact of Dynamic Voltage Fluctuations Using Static Timing Analysis.	VLSI Design	2009	DBLP DOI BibTeX RDF
23	Jinjun Xiong, Chandu Visweswariah, Vladimir Zolotov	Statistical ordering of correlated timing quantities and its application for path ranking.	DAC	2009	DBLP DOI BibTeX RDF	path ranking, statistical ordering, testing, correlation
23	Lin Wu, Vincenzo Lottici, Zhi Tian	Maximum Likelihood Multiple Access Timing Synchronization for UWB Communications.	IEEE Trans. Wirel. Commun.	2008	DBLP DOI BibTeX RDF
23	Ruiming Chen, Hai Zhou 0001	Fast Estimation of Timing Yield Bounds for Process Variations.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
23	Sari Onaissi, Farid N. Najm	A Linear-Time Approach for Static Timing Analysis Covering All Process Corners.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
23	Vamsi Vankamamidi, Marco Ottavi, Fabrizio Lombardi	Two-Dimensional Schemes for Clocking/Timing of QCA Circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
23	Kotipalli Pushpa, Chavali Nanda Kishore, Yeleswarapu Yoganandam	Comparative study of four modified timing metrics for the frame synchronization in OFDMA mode of WMAN.	PIMRC	2008	DBLP DOI BibTeX RDF
23	Xiapu Luo, Edmond W. W. Chan, Rocky K. C. Chang	TCP covert timing channels: Design and detection.	DSN	2008	DBLP DOI BibTeX RDF
23	Sean X. Shi, Anand Ramalingam, Daifeng Wang, David Z. Pan	Latch Modeling for Statistical Timing Analysis.	DATE	2008	DBLP DOI BibTeX RDF
23	Raman Venkataramani, Mehmet Fatih Erden	MAP-Based Timing Recovery for Magnetic Recording.	ICC	2008	DBLP DOI BibTeX RDF
23	Rajeshwary Tayade, Sani R. Nassif, Jacob A. Abraham	Analytical model for the impact of multiple input switching noise on timing.	ASP-DAC	2008	DBLP DOI BibTeX RDF
23	Khaled R. Heloue, Sari Onaissi, Farid N. Najm	Efficient block-based parameterized timing analysis covering all potentially critical paths.	ICCAD	2008	DBLP DOI BibTeX RDF
23	Javid Jaffari, Mohab Anis	On efficient Monte Carlo-based statistical static timing analysis of digital circuits.	ICCAD	2008	DBLP DOI BibTeX RDF
23	Shiyan Hu, Zhuo Li 0001, Charles J. Alpert	A polynomial time approximation scheme for timing constrained minimum cost layer assignment.	ICCAD	2008	DBLP DOI BibTeX RDF
23	Veerapaneni Nagbhushan, C. Y. Roger Chen	Modeling and reduction of complex timing constraints in high performance digital circuits.	ICCD	2008	DBLP DOI BibTeX RDF
23	Anuj Kumar, Tai-Hsuan Wu, Azadeh Davoodi	SynECO: Incremental technology mapping with constrained placement and fast detail routing for predictable timing improvement.	ICCD	2008	DBLP DOI BibTeX RDF
23	Hatim Daginawala, Matthew K. Wright	Studying Timing Analysis on the Internet with SubRosa.	Privacy Enhancing Technologies	2008	DBLP DOI BibTeX RDF
23	Yongjian Tang, Hans Hegt, Arthur H. M. van Roermund	Predictive timing error calibration technique for RF current-steering DACs.	ISCAS	2008	DBLP DOI BibTeX RDF
23	Johannes Partzsch, Christian Mayr 0001, René Schüffny	BCM and Membrane Potential: Alternative Ways to Timing Dependent Plasticity.	ICONIP (1)	2008	DBLP DOI BibTeX RDF
23	Shiyan Hu, Qiuyang Li, Jiang Hu, Peng Li 0001	Utilizing Redundancy for Timing Critical Interconnect.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
23	Farid N. Najm, Noel Menezes, Imad A. Ferzli	A Yield Model for Integrated Circuits and its Application to Statistical Timing Analysis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
23	Rutuparna Tamhankar, Srinivasan Murali, Stergios Stergiou, Antonio Pullini, Federico Angiolini, Luca Benini, Giovanni De Micheli	Timing-Error-Tolerant Network-on-Chip Design Methodology.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
23	Puneet Gupta 0001, Andrew B. Kahng, Youngmin Kim, Dennis Sylvester	Self-Compensating Design for Reduction of Timing and Leakage Sensitivity to Systematic Pattern-Dependent Variation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
23	Desta Tadesse, D. Sheffield, E. Lenge, R. Iris Bahar, Joel Grodstein	Accurate timing analysis using SAT and pattern-dependent delay models.	DATE	2007	DBLP DOI BibTeX RDF
23	Jing Xu, Wensheng Yu, Jian-Qiang Yi, Zhishou Tu	Traffic Signal Timing with Neural Dynamic Optimization.	ISNN (1)	2007	DBLP DOI BibTeX RDF
23	Daniel Parthey, Robert Baumgartl	Analyzing Access Timing of Removable Flash Media.	RTCSA	2007	DBLP DOI BibTeX RDF
23	Michael Ward, Neil C. Audsley	A Deterministic Implementation Process for Accurate and Traceable System Timing and Space Analysis.	RTCSA	2007	DBLP DOI BibTeX RDF
23	Jongyoon Jung, Taewhan Kim	Timing variation-aware high-level synthesis.	ICCAD	2007	DBLP DOI BibTeX RDF
23	Yen-Pin Chen, Jia-Wei Fang, Yao-Wen Chang	ECO timing optimization using spare cells.	ICCAD	2007	DBLP DOI BibTeX RDF
23	Veerapaneni Nagbhushan, C. Y. Roger Chen	Algorithms to simplify multi-clock/edge timing constraints.	ICCD	2007	DBLP DOI BibTeX RDF
23	Dylan Stark, Gabrielle Allen, Tom Goodale, Thomas Radke, Erik Schnetter	An Extensible Timing Infrastructure for Adaptive Large-Scale Applications.	PPAM	2007	DBLP DOI BibTeX RDF
23	Tadesse Ghirmai	Data Detection and Fixed Symbol-Timing Estimation in Flat Fading Channels.	CISS	2007	DBLP DOI BibTeX RDF
23	Harry I. A. Chen, Edward K. W. Loo, James B. Kuo, Marek Syrzycki	Triple-Threshold Static Power Minimization in High-Level Synthesis of VLSI CMOS.	PATMOS	2007	DBLP DOI BibTeX RDF
23	Jochen A. G. Jess, Kerim Kalafala, Srinath R. Naidu, Ralph H. J. M. Otten, Chandramouli Visweswariah	Statistical Timing for Parametric Yield Prediction of Digital Integrated Circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
23	Kiran Seth, Aravindh Anantaraman, Frank Mueller 0001, Eric Rotenberg	FAST: Frequency-aware static timing analysis.	ACM Trans. Embed. Comput. Syst.	2006	DBLP DOI BibTeX RDF	scheduling, Real-time systems, dynamic voltage scaling, worst-case execution time analysis
23	Ara Patapoutian	Timing metrics for constrained codes.	IEEE Trans. Inf. Theory	2006	DBLP DOI BibTeX RDF
23	José A. Lopez-Salcedo, Gregori Vázquez	Asymptotic equivalence between the unconditional maximum likelihood and the square-law nonlinearity symbol timing estimation.	IEEE Trans. Signal Process.	2006	DBLP DOI BibTeX RDF
23	Hongbin Li 0001, Rensheng Wang, Khaled Amleh	Blind code-timing estimation for CDMA systems with bandlimited chip waveforms in multipath fading channels.	IEEE Trans. Commun.	2006	DBLP DOI BibTeX RDF
23	Yasamin Mostofi, Donald C. Cox	Mathematical analysis of the impact of timing synchronization errors on the performance of an OFDM system.	IEEE Trans. Commun.	2006	DBLP DOI BibTeX RDF
23	Kenneth Eguro, Scott Hauck	Armada: timing-driven pipeline-aware routing for FPGAs.	FPGA	2006	DBLP DOI BibTeX RDF	pipeline FPGA, pipeline routing, reconfigurable computing
23	Lizheng Zhang, Jeng-Liang Tsai, Weijen Chen, Yuhen Hu, Charlie Chung-Ping Chen	Convergence-provable statistical timing analysis with level-sensitive latches and feedback loops.	ASP-DAC	2006	DBLP DOI BibTeX RDF
23	Chanseok Hwang, Massoud Pedram	Timing-driven placement based on monotone cell ordering constraints.	ASP-DAC	2006	DBLP DOI BibTeX RDF
23	Mike Hutton, Yan Lin 0001, Lei He 0001	Placement and Timing for FPGAs Considering Variations.	FPL	2006	DBLP DOI BibTeX RDF
23	Jiyoun Kim, Marios C. Papaefthymiou, José Luis Neves	Parallelizing post-placement timing optimization.	IPDPS	2006	DBLP DOI BibTeX RDF
23	Jörg E. Vollrath, Jürg Schwizer, Marcin Gnat, Ralf Schneider, Bret Johnson	DDR2 DRAM Output Timing Optimization.	MTDT	2006	DBLP DOI BibTeX RDF
23	Alejandro Russo, John Hughes 0001, David A. Naumann, Andrei Sabelfeld	Closing Internal Timing Channels by Transformation.	ASIAN	2006	DBLP DOI BibTeX RDF
23	Sari Onaissi, Farid N. Najm	A linear-time approach for static timing analysis covering all process corners.	ICCAD	2006	DBLP DOI BibTeX RDF
23	Bo Hu	Timing-driven placement for heterogeneous field programmable gate array.	ICCAD	2006	DBLP DOI BibTeX RDF
23	Sean X. Shi, Peng Yu, David Z. Pan	A unified non-rectangular device and circuit simulation model for timing and power.	ICCAD	2006	DBLP DOI BibTeX RDF	physical design, VLSI CAD, device modeling
23	Yue Yu 0002, Shangping Ren, Ophir Frieder	Prediction of Timing Constraint Violation for Real-Time Embedded Systems with Known Transient Hardware Failure Distribution Model.	RTSS	2006	DBLP DOI BibTeX RDF
23	Valavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh, Stephen Dean Brown	Difficulty of predicting interconnect delay in a timing driven FPGA CAD flow.	SLIP	2006	DBLP DOI BibTeX RDF
23	Lijuan Luo, Qiang Zhou 0001, Yici Cai, Xianlong Hong, Yibo Wang	A novel technique integrating buffer insertion into timing driven placement.	ISCAS	2006	DBLP DOI BibTeX RDF
23	Andrew B. Kahng, Bao Liu 0001, Xu Xu 0001	Constructing Current-Based Gate Models Based on Existing Timing Library.	ISQED	2006	DBLP DOI BibTeX RDF
23	Chenyu Huang, William John Misskey, Joe Toth	Combination of Coarse Symbol Timing and Carrier Frequency Offset (CFO) Estimation Techniques for MIMO OFDM Systems.	CCECE	2006	DBLP DOI BibTeX RDF
23	Ramyanshu Datta, Gary D. Carpenter, Kevin J. Nowka, Jacob A. Abraham	A Scheme for On-Chip Timing Characterization.	VTS	2006	DBLP DOI BibTeX RDF
23	Pai Peng, Peng Ning, Douglas S. Reeves	On the Secrecy of Timing-Based Active Watermarking Trace-Back Techniques.	S&P	2006	DBLP DOI BibTeX RDF
23	Siva Embanath, Ramakrishnan Venkata	Exceptional ASIC: Through Automatic Timing Exception Generation (ATEG).	VLSI Design	2006	DBLP DOI BibTeX RDF
23	Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram	Timing-based delay test for screening small delay defects.	DAC	2006	DBLP DOI BibTeX RDF	test generation, delay testing
23	Sujan Pandey, Manfred Glesner	Statistical on-chip communication bus synthesis and voltage scaling under timing yield constraint.	DAC	2006	DBLP DOI BibTeX RDF	communication bus synthesis, voltage scaling
23	Zhi Tian, Georgios B. Giannakis	A GLRT approach to data-aided timing acquisition in UWB radios-Part I: algorithms.	IEEE Trans. Wirel. Commun.	2005	DBLP DOI BibTeX RDF
23	Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski	Delay-fault diagnosis using timing information.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
23	Yong Liu, Tan F. Wong, Ashish Pandharipande	Timing estimation in multiple-antenna systems over Rayleigh flat-fading channels.	IEEE Trans. Signal Process.	2005	DBLP DOI BibTeX RDF
23	Wonzoo Chung, William A. Sethares, C. Richard Johnson Jr.	Timing phase offset recovery based on dispersion minimization.	IEEE Trans. Signal Process.	2005	DBLP DOI BibTeX RDF
23	Liuqing Yang 0001, Georgios B. Giannakis	Timing ultra-wideband signals with dirty templates.	IEEE Trans. Commun.	2005	DBLP DOI BibTeX RDF
23	M. Ümit Uyar, Yu Wang 0012, Samrat S. Batth, Adriana Wise, Mariusz A. Fecko	Timing Fault Models for Systems with Multiple Timers.	TestCom	2005	DBLP DOI BibTeX RDF	Timer Constraints, Fault Modeling, Timed Automata, Conformance Testing, Multiple Faults
23	Sanjit A. Seshia, Randal E. Bryant, Kenneth S. Stevens	Modeling and Verifying Circuits Using Generalized Relative Timing.	ASYNC	2005	DBLP DOI BibTeX RDF
23	Qingzhou (Ben) Wang, John Lillis, Shubhankar Sanyal	An LP-based methodology for improved timing-driven placement.	ASP-DAC	2005	DBLP DOI BibTeX RDF
23	Di Wu 0017, Jiang Hu, Rabi N. Mahapatra	Coupling aware timing optimization and antenna avoidance in layer assignment.	ISPD	2005	DBLP DOI BibTeX RDF	VLSI, interconnect, probabilistic modeling, physical design, crosstalk, design for manufacturability (DFM), antenna effect
23	Hana Chockler, Kathi Fisler	Temporal Modalities for Concisely Capturing Timing Diagrams.	CHARME	2005	DBLP DOI BibTeX RDF
23	David J. Hathaway	Dealing with the spatio-temporal interactions among transient power, supply noise and timing.	SLIP	2005	DBLP DOI BibTeX RDF
23	Sibin Mohan, Frank Mueller 0001, David B. Whalley, Christopher A. Healy	Timing Analysis for Sensor Network Nodes of the Atmega Processor Family.	IEEE Real-Time and Embedded Technology and Applications Symposium	2005	DBLP DOI BibTeX RDF
23	Christian Vogel 0001, Dieter Draxelmayr, Gernot Kubin	Spectral shaping of timing mismatches in time-interleaved analog-to-digital converters.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
23	Octav Chipara, Chenyang Lu 0001, Gruia-Catalin Roman	Efficient Power Management Based on Application Timing Semantics for Wireless Sensor Networks.	ICDCS	2005	DBLP DOI BibTeX RDF
23	Jie Yang 0010, Luigi Capodieci, Dennis Sylvester	Advanced timing analysis based on post-OPC extraction of critical dimensions.	DAC	2005	DBLP DOI BibTeX RDF	process CD, layout, OPC, design flow
23	Hongliang Chang, Vladimir Zolotov, Sambasivan Narayan, Chandu Visweswariah	Parameterized block-based statistical timing analysis with non-gaussian parameters, nonlinear delay functions.	DAC	2005	DBLP DOI BibTeX RDF
23	Chi-Sheng Shih 0001, Jane W.-S. Liu	Acquiring and incorporating state-dependent timing requirements.	Requir. Eng.	2004	DBLP DOI BibTeX RDF	Requirement capture and update, Real-time software architecture, Real-time requirements
23	Jason Cong, Sung Kyu Lim	Retiming-based timing analysis with an application to mincut-based global placement.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
23	Brian Neil Levine, Michael K. Reiter, Chenxi Wang, Matthew K. Wright	Timing Attacks in Low-Latency Mix Systems (Extended Abstract).	Financial Cryptography	2004	DBLP DOI BibTeX RDF
23	Neil C. Audsley, Konstantinos Bletsas	Fixed Priority Timing Analysis of Real-Time Systems with Limited Parallelism.	ECRTS	2004	DBLP DOI BibTeX RDF
23	Mango Chia-Tso Chao, Li-C. Wang, Kwang-Ting Cheng	Pattern Selection for Testing of Deep Sub-Micron Timing Defects.	DATE	2004	DBLP DOI BibTeX RDF
23	Keoncheol Shin, Taewhan Kim	An integrated approach to timing-driven synthesis and placement of arithmetic circuits.	ASP-DAC	2004	DBLP DOI BibTeX RDF
23	Reinhard Wilhelm	Formal Analysis of Processor Timing Models.	SPIN	2004	DBLP DOI BibTeX RDF
23	Vishal Khandelwal, Azadeh Davoodi, Ankur Srivastava 0001	Efficient statistical timing analysis through error budgeting.	ICCAD	2004	DBLP DOI BibTeX RDF
23	Masashi Shimanouchi	Timing Accuracy Enhancement by a New Calibration Scheme for Multi-Gbps ATE.	ITC	2004	DBLP DOI BibTeX RDF
23	Aseem Agarwal, Vladimir Zolotov, David T. Blaauw	Statistical timing analysis using bounds and selective enumeration.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF