Search results for "A-SSCC"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Jian Pang, Korkut Kaan Tokgoz, Shotaro Maki, Zheng Li 0021, Xueting Luo, Ibrahim Abdo, Seitarou Kawai, Hanli Liu, Bangan Liu, Makihiko Katsuragi, Kento Kimura, Atsushi Shirane, Kenichi Okada	A 28.16-Gb/s Area-Efficient 60GHz CMOS Bi-Directional Transceiver for IEEE 802.11ay.	A-SSCC	2018	DBLP DOI BibTeX RDF
1	Yan Zhu 0001, Chi-Hang Chan, Rui Paulo Martins	An 11b 1GS/s Time-Interleaved ADC with Linearity Enhanced T/H.	A-SSCC	2018	DBLP DOI BibTeX RDF
1	Hye-Yeon Yoon, Seung-Jun Hwang, Tae-Hwan Kim	A 655Mbps Successive-Cancellation Decoder for a 1024-bit Polar Code in 180nm CMOS.	A-SSCC	2018	DBLP DOI BibTeX RDF
1	Seizo Onoe	Open the New World of 5G.	A-SSCC	2018	DBLP DOI BibTeX RDF
1	Himanshu Kaul, Mark A. Anders 0001, Sanu Mathew, Vikram B. Suresh, Sudhir Satpathy, Amit Agarwal 0001, Steven Hsu, Ram Krishnamurthy 0001	Ultra-Lightweight 548-1080 Gate 166Gbps/W-12.6Tbps/W SIMON 32/64 Cipher Accelerators for IoT in 14nm Tri-gate CMOS.	A-SSCC	2018	DBLP DOI BibTeX RDF
1	Kevin Zhang 0001	Circuit Design in Nano-Scale CMOS Technologies.	A-SSCC	2018	DBLP DOI BibTeX RDF
1	Yi Zhong, Shaolan Li, Arindam Sanyal, Xiyuan Tang, Linxiao Shen, Siliang Wu, Nan Sun 0001	A Second-Order Purely VCO-Based CT Δ∑ ADC Using a Modified DPLL in 40-nm CMOS.	A-SSCC	2018	DBLP DOI BibTeX RDF
1	Haixin Song, Dang Liu, Woogeun Rhee, Zhihua Wang 0001	A 6-8GHZ 200MHz Bandwidth 9-Channel VWB Transceiver with 8 Frequency-Hopping Subbands.	A-SSCC	2018	DBLP DOI BibTeX RDF
1	Zhengyu Chen 0002, Jie Gu 0001	An Image Recognition Processor with Time-domain Accelerators using Efficient Time Encoding and Non-linear Logic Operation.	A-SSCC	2018	DBLP DOI BibTeX RDF
1	Po-Wei Chiu, Muqing Liu, Qianying Tang, Chris H. Kim	A 2.1 pJ/bit, 8 Gb/s Ultra-Low Power In-Package Serial Link Featuring a Time-based Front-end and a Digital Equalizer.	A-SSCC	2018	DBLP DOI BibTeX RDF
1	Matthias Eberlein, Georgios Panagopoulos, Harald Pretl	A 40nW, Sub-IV Truly 'Digital' Reverse Bandgap Reference Using Bulk-Diodes in 16nm FinFET.	A-SSCC	2018	DBLP DOI BibTeX RDF
1	Kota Tsurumi, Kenta Suzuki, Ken Takeuchi	A 6.8 TOPS/W Energy Efficiency, 1.5µW Power Consumption, Pulse Width Modulation Neuromorphic Circuits for Near-Data Computing with SSD.	A-SSCC	2018	DBLP DOI BibTeX RDF
1	Mitsuru Hiraki, Sugako Otani, Masao Ito, Takuya Mizokami, Masahiro Araki, Hiroyuki Kondo	A Capacitance-to-Digital Converter Integrated in a 32bit Microcontroller for 3D Gesture Sensing.	A-SSCC	2018	DBLP DOI BibTeX RDF
1	Luya Zhang, Ali Ameri, Yi-An Li, Nai-Chung Kuo, Mekhail Anwar, Ali M. Niknejad	A 37.5-45. lGHz Superharmonic-Coupled QVCO with Tunable Phase Accuracy in 28nm Bulk CMOS.	A-SSCC	2018	DBLP DOI BibTeX RDF
1	Yoshisato Yokoyama, Tomohiro Miura, Yukari Ouchi, Daisuke Nakamura, Jiro Ishikawa, Shunya Nagata, Makoto Yabuuchi, Yuichiro Ishii, Koji Nii	40-nm 64-kbit Buffer/Backup SRAM with 330 nW Standby Power at 65°C Using 3.3 V IO MOSs for PMIC less MCU in IoT Applications.	A-SSCC	2018	DBLP DOI BibTeX RDF
1	Val Mikos, Chun-Huat Heng, Arthur Tay, Shih-Cheng Yen, Nicole Shuang Yu Chia, Karen Koh Mui Ling, Dawn May Leng Tan, Wing Lok Au	A Neural Network Accelerator With Integrated Feature Extraction Processor for a Freezing of Gait Detection System.	A-SSCC	2018	DBLP DOI BibTeX RDF
1	Vinod V. Gadde, Hiromitsu Awano, Makoto Ikeda	An Encryption-Authentication Unified A/D Conversion Scheme for IoT Sensor Nodes.	A-SSCC	2018	DBLP DOI BibTeX RDF
1	Hyuntak Jeon, Jun-Suk Bang, Yoontae Jung, Taeju Lee, Yeseul Jeon, Seok-Tae Koh, Jaesuk Choi, Doojin Jang, Soonyoung Hong, Minkyu Je	A 3.9μW, 81.3dB SNDR, DC-coupled, Time-based Neural Recording IC with Degeneration R-DAC for Bidirectional Neural Interface in 180nm CMOS.	A-SSCC	2018	DBLP DOI BibTeX RDF
1	Karim Rawy, Ruchi Sharma, Hong-Joon Yoon, Usman Khan, Sang-Woo Kim, Tony T. Kim	An 88% Efficiency 2.4μW to 15.6μW Triboelectric Nanogenerator Energy Harvesting System Based on a Single-Comparator Control Algorithm.	A-SSCC	2018	DBLP DOI BibTeX RDF
1	Neha Priyadarshini, Chandani Anand, Mukul Sarkar	A WDR CMOS Image Sensor Employing In-pixel Capacitive Variation using a Re-configurable Source Follower for Low Light Applications.	A-SSCC	2018	DBLP DOI BibTeX RDF
1	Yosuke Toyama, Kentaro Yoshioka, Koichiro Ban, Akihide Sai, Kohei Onizuka	A 12.4TOPS/W, 20% Less Gate Count Bidirectional Phase Domain MAC Circuit for DNN Inference Applications.	A-SSCC	2018	DBLP DOI BibTeX RDF
1	Guiqiang Peng, Leibo Liu, Qiushi Wei, Yao Wang, Shouyi Yin, Shaojun Wei	A 2.69 Mbps/mW 1.09 Mbps/kGE Conjugate Gradient-based MMSE Detector for 64-QAM 128×8 Massive MIMO Systems.	A-SSCC	2018	DBLP DOI BibTeX RDF
1	Asuka Maki, Daisuke Miyashita, Kengo Nakata, Fumihiko Tachibana, Tomoya Suzuki, Jun Deguchi	FPGA-based CNN Processor with Filter-Wise-Optimized Bit Precision.	A-SSCC	2018	DBLP DOI BibTeX RDF
1	Chien-An Lai, Chung-Cheng Chou, Chi-Hsiang Weng, Zheng-Jun Lin, Pei-Ling Tseng, Chien-Fan Wang, Chih-Chen Wang, Chin-I Su, Wei-Chi Chen, Yu-Cheng Lin, Tong-Chern Ong, Chi Chang, Yu-Der Chih, Tsung-Yung Jonathan Chang	Logic Process Compatible 40nm 256K×144 Embedded RRAM with Low Voltage Current Limiter and Ambient Compensation Scheme to Improve the Read Window.	A-SSCC	2018	DBLP DOI BibTeX RDF
1	Min-Seong Choo, Han-Gon Ko, Sung-Yong Cho, Kwangho Lee, Deog-Kyoon Jeong	A 10-Gb/s, 0.03-mm2, 1.28-pJ/bit Half-Rate All-Digital Injection-Locked Clock and Data Recovery with Maximum Timing-Margin Tracking Loop.	A-SSCC	2018	DBLP DOI BibTeX RDF
1	Reza Ranjandish, Alexandre Schmid	A 4-channel 5.04 μW 0.325 mm2 Orthogonal Sampling-Based Parallel Neural Recording System.	A-SSCC	2018	DBLP DOI BibTeX RDF
1	Yong-Sik Kwak, Kang-Il Cho, Ho-Jin Kim, Seung-Hoon Lee, Gil-Cho Ahn	A 72.9-dB SNDR 20-MHz BW 2-2 discrete-time sturdy MASH delta-sigma modulator using source-follower-based integrators.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	Chang-Kyo Lee, Junha Lee, Kiho Kim, Jin-Seok Heo, Gil-Hoon Cha, Jin-Hyeok Baek, Daesik Moon, Yoon-Joo Eom, Tae-Sung Kim, Hyunyoon Cho, Young Hoon Son, Seonghwan Kim 0002, Jong-Wook Park, Sewon Eom, Si-Hyeong Cho, Young-Ryeol Choi, Seungseob Lee, Kyoung-Soo Ha, Youngseok Kim, Bo-Tak Lim, Dae-Hee Jung, Eungsung Seo, Kyoung-Ho Kim, Yoon-Gyu Song, Youn-Sik Park, Tae-Young Oh, Seung-Jun Bae, Indal Song, Seok-Hun Hyun, Joon-Young Park, Hyuck-Joon Kwon, Young-Soo Sohn, Jung-Hwan Choi, Kwang-Il Park, Seong-Jin Jang	Dual-loop 2-step ZQ calibration for dedicated power supply voltage in LPDDR4 SDRAM.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	Sheng-Ying Lin, Tsung-Hsien Lin	An area-efficient amplifier-less digitally-controlled li-ion battery charger in 0.35μm CMOS.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	Zhao Zhang 0004, Jincheng Yang, Liyuan Liu, Peng Feng 0001, Jian Liu 0021, Nanjian Wu	A 18-to-23 GHz -253.5dB-FoM sub-harmonically injection-locked ADPLL with ILFD aided adaptive injection timing alignment technique.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	Hae-Woong Yang, Ashkan Roshan-Zamir, Young-Hoon Song, Samuel Palermo	A low-power dual-mode 20-Gb/s NRZ and 28-Gb/s PAM-4 voltage-mode transmitter.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	Yuxuan Luo, Kok-Hin Teng, Yongfu Li 0002, Wei Mao 0002, Chun-Huat Heng, Yong Lian 0001	A 93μW 11Mbps wireless vital signs monitoring SoC with 3-lead ECG, bio-impedance, and body temperature.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	Hassan Saif, Yongmin Lee, Minsun Kim, Hyeonji Lee, Muhammad Bilawal Khan, Yoonmyung Lee	A wide load and voltage range switched-capacitor DC-DC converter with load-dependent configurability for DVS implementation in miniature sensors.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	Brendan Farley, Christophe Erdmann, Bruno Vaz, John McGrath, Edward Cullen, Bob Verbruggen, Roberto Pelliconi, Daire Breathnach, Peng Lim, Ali Boumaalif, Patrick Lynch, Conrado Mesadri, David Melinn, Kwee Peng Yap, Liam Madden	A programmable RFSoC in 16nm FinFET technology for wideband communications.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	Suhwan Cho, Seongrim Choi, Junsik Woo, Ara Kim, Byeong-Gyu Nam	A self-powered always-on vision-based wake-up detector for wearable gesture user interfaces.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	Feng Zhang 0014, Dongyu Fan, Yuan Duan, Jin Li, Cong Fang 0002, Yun Li, Xiaowei Han, Lan Dai, Cheng-Ying Chen, Jinshun Bi, Ming Liu 0022, Meng-Fan Chang	A 130nm 1Mb HfOx embedded RRAM macro using self-adaptive peripheral circuit system techniques for 1.6X work temperature range.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	Chun-Yu Lin 0002, Tun-Ju Wang, Tsung-Hsien Lin	A 1.5-GHz sub-sampling fractional-N PLL for spread-spectrum clock generator in 0.18-μm CMOS.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	Peng Chen 0022, Feifei Zhang, Zhirui Zong, Hao Zheng, Teerachot Siriburanon, Robert Bogdan Staszewski	A 15-μW, 103-fs step, 5-bit capacitor-DAC-based constant-slope digital-to-time converter in 28nm CMOS.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	Ting Liao, Nien-An Lee, Chih-Cheng Hsieh	A CMOS time of flight (TOF) depth image sensor with in-pixel background cancellation and sensitivity improvement using phase shifting readout technique.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	Karim Rawy, Taegeun Yoo, Tony T. Kim	An 88% efficiency MPPT for PV energy harvesting system with novel switch width modulation for output power 100nW to 0.3mW.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	Shao-Qi Chen, Yen-Ting Lin, Yu-Sheng Ma, Wen-Hau Yang, Ke-Horng Chen, Ying-Hsi Lin, Jian-Ru Lin, Tsung-Yen Tsai	A high efficiency and fast transient digital low-dropout assisted switched-capacitor converter for EMI-free Internet of Everything (IoE) systems.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	Junmin Jiang, Liusheng Sun, Xu Zhang, Shing Hin Yuen, Xianbo Li, Wing-Hung Ki, C. Patrick Yue, Kei May Lau	Fully-integrated AMLED micro display system with a hybrid voltage regulator.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	Martin Cochet, Sylvain Clerc, Guenole Lallement, Fady Abouzeid, Philippe Roche, Jean-Luc Autran	A 0.40pJ/cycle 981 μm2 voltage scalable digital frequency generator for SoC clocking.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	Mahesh K. Kumashikar, Shridhar G. Bendi, Srikanth Nimmagadda, Anup Jyoti Deka, Anil Agarwal	14nm Broadwell Xeon® processor family: Design methodologies and optimizations.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	Michele D'Urbino, Chao Chen 0019, Zhao Chen 0001, Zu-yao Chang, Jacco Ponte, Boris Lippe, Michiel A. P. Pertijs	An element-matched band-pass delta-sigma ADC for ultrasound imaging.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	Weitao Li, Fule Li, Jia Liu, Hongyu Li, Zhihua Wang 0001	A 13-bit 160MS/s pipelined subranging-SAR ADC with low-offset dynamic comparator.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	Kuan-Lin Fu, Shen-Iuan Liu	A 56Gbps PAM-4 optical receiver front-end.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	Jens Anders, Sebastian Bader 0003, Markus Dietl, Puneet Sareen, G. Rombach, Sotirios Tambouris, Maurits Ortmanns	A -245 dB FOM 48 fs rms jitter semi-digital PLL with intrinsic temperature compensation in 130 nm CMOS.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	Chiao-Hung Cheng, Li-Chi Lin, Jian-He Lin, Ke-Horng Chen, Ying-Hsi Lin, Jian-Ru Lin, Tsung-Yen Tsai	A DVS-based burst mode with automatic entrance point control technique in DC-DC boost converter for wearable devices and IoT applications.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	Chih-Chan Tu, Feng-Wen Lee, Han-Chun Chen, Yu-Kai Wang, Tsung-Hsien Lin	An area-efficient capacitively-coupled sensor readout circuit with current-splitting OTA and FIR-DAC.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	Chi-Wei Liu, Ming-Jie Chung, Hui-Hsuan Lee, Pei-Chun Liao, Po-Hung Chen	A single-inductor triple-input-triple-output (SITITO) energy harvesting interface with cycle-by-cycle source tracking and adaptive peak-inductor-current control.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	Chia-Fu Lee, Hon-Jarn Lin, Chiu-Wang Lien, Yu-Der Chih, Tsung-Yung Jonathan Chang	A 1.4Mb 40-nm embedded ReRAM macro with 0.07um2 bit cell, 2.7mA/100MHz low-power read and hybrid write verify for high endurance application.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	Anastacia B. Alvarez, Gopalakrishnan Ponnusamy, Massimo Alioto	EQSCALE: Energy-quality scalable feature extraction engine for Sub-mW real-time video processing with 0.55 mm2 area in 40nm CMOS.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	Miguel Gandara, Paridhi Gulati, Nan Sun 0001	A 172dB-FoM pipelined SAR ADC using a regenerative amplifier with self-timed gain control and mixed-signal background calibration.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	Chester Liu, Sung-Gun Cho, Zhengya Zhang	A 2.56mm2 718GOPS configurable spiking convolutional sparse coding processor in 40nm CMOS.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	Wentao Dai, Weiwei Shan, Xinning Liu, Jun Yang 0006	HTD: A light-weight holosymmetrical transition detector based in-situ timing monitoring technique for wide-voltage-range in 40nm CMOS.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	Jaeeun Jang, Minseo Kim, Joonsung Bae, Hoi-Jun Yoo	A 2.79-mW 0.5%-THD CMOS current driver IC for portable electrical impedance tomography system.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	Seokha Hwang, Jaehwan Jung, Daesung Kim, Jeongseok Ha, In-Cheol Park, Youngjoo Lee	An energy-optimized (37840, 34320) symmetric BC-BCH decoder for healthy mobile storages.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	M. Kumarasamy Raja, Zhao Bin, Dan Lei Yan, Hongbao Zhang, Wei Yi Lim, Leo John Chemmanda	A -121dBm sensitivity, 2μJ/bit Rx, 8.8μJ/bit Tx, narrowband transceiver for ARIB STD and IoT.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	Da-Shin Lin, Hao-Ping Hong	A 0.5V BJT-based CMOS thermal sensor in 10-nm FinFET technology.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	Yoshiaki Deguchi, Ken Takeuchi	Word-line batch Vth modulation of TLC NAND flash memories for both write-hot and cold data.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	U. Fat Chio, Sai-Weng Sin, Seng-Pan U, Franco Maloberti, Rui Paulo Martins	A 5-bit 2 GS/s binary-search ADC with charge-steering comparators.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	Yoshisato Yokoyama, Yuichiro Ishii, Haruyuki Okuda, Koji Nii	A dynamic power reduction in synchronous 2RW 8T dual-port SRAM by adjusting wordline pulse timing with same/different row access mode.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	Suneui Park, Heein Yoon, Jaehyouk Choi	An ultra-low phase noise all-digital multi-frequency generator using injection-locked DCOs and time-interleaved calibration.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	Young-Ha Hwang, Jun-Eun Park, Deog-Kyoon Jeong	A compact 87.1-dB DR bandwidth-scalable delta-sigma modulator based on dynamic gain-bandwidth-boosting inverter for audio applications.	A-SSCC	2017	DBLP DOI BibTeX RDF
1		IEEE Asian Solid-State Circuits Conference, A-SSCC 2017, Seoul, Korea (South), November 6-8, 2017	A-SSCC	2017	DBLP BibTeX RDF
1	Wei Wang 0177, Yan Zhu 0001, Chi-Hang Chan, Seng-Pan U, Rui Paulo Martins	A 5.35 mW 10 MHz bandwidth CT third-order ΔΣ modulator with single Opamp achieving 79.6/84.5 dB SNDR/DR in 65 nm CMOS.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	Jinmook Lee, Dongjoo Shin, Hoi-Jun Yoo	A 21mW low-power recurrent neural network accelerator with quantization tables for embedded deep learning applications.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	Chun-Yu Lin 0002, Tun-Ju Wang, Tzu-Hsuan Liu, Tsung-Hsien Lin	An ultra-low power 169-nA 32.768-kHz fractional-N PLL.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	Mitsuhiko Igarashi, Yoshio Takazawa, Yasumasa Tsukamoto, Kan Takeuchi, Koji Shibutani	NBTI/PBTI separated BTI monitor with 4.2x sensitivity by standard cell based unbalanced ring oscillator.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	Saurabh Chaubey, Ramesh Harjani	A smart-offset analog LDO with 0.3V minimum input voltage and 99.1% current efficiency.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	Jihwan Park, Joo-Hyung Chae, Yong-Un Jeong, Jae-Whan Lee, Suhwan Kim	A 2.1Gbps 12-channel transmitter with phase emphasis embedded serializer for UHD intra-panel interface.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	Tao Tang, Wang Ling Goh, Lei Yao, Yuan Gao 0011	A 16-channel TDM analog front-end with enhanced system CMRR for wearable dry EEG recording.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	Amaravati Anvesha, Arijit Raychowdhury	A 65nm 376nA 0.4V linear classifier using time-based matrix-multiplying ADC with non-linearity aware training.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	Masanobu Tsuji	A 762-pW 16.3-ps resolution digital pulse width modulator using zooming phase-interpolator.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	Hikaru Watanabe, Yoshiaki Deguchi, Ken Takeuchi	MLC/3LC NAND flash SSD cache with asymmetric error reduction huffman coding for tiered hierarchical storage.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	Noriyuki Miura, Masanori Takahashi, Kazuki Nagatomo, Makoto Nagata	Chaos, deterministic non-periodic flow, for chip-package-board interactive PUF.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	Shengshuo Lu, Zhengya Zhang, Marios C. Papaefthymiou	A 1.25pJ/bit 0.048mm2 AES core with DPA resistance for IoT devices.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	Nan Qi, Yuhang Kang, Qipeng Lin, Jianxu Ma, Jingbo Shi, Bozhi Yin, Chang Liu, Rui Bai 0001, Shang Hu, Juncheng Wang, Jiangbing Du, Lin Ma 0008, Zuyuan He, Ming Liu 0022, Feng Zhang 0014, Patrick Yin Chiang	A 51Gb/s, 320mW, PAM4 CDR with baud-rate sampling for high-speed optical interconnects.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	Sachin Taneja, Anastacia B. Alvarez, Gopalakrishnan Sadagopan, Massimo Alioto	A fully-synthesizable C-element based PUF featuring temperature variation compensation with native 2.8% BER, 1.02fJ/b at 0.8-1.0V in 40nm.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	Masum Hossain, Aurangozeb, A. K. M. Delwar Hossain, Maruf Mohammad	A 82 mW 28 Gb/s PAM-4 digital sequence decoder with built-in error correction in 28nm FDSOI.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	Van Loi Le, Juhui Li, Alan Chang, Tony T. Kim	An 82% energy-saving change-sensing flip-flop in 40nm CMOS for ultra-low power applications.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	Aikaterini Papadopoulou, Vladimir M. Milovanovic, Borivoje Nikolic	A low-voltage low-offset dual strong-arm latch comparator.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	Guang Zhu, Quan Pan 0002, John Zhuang, Charlie Zhi, C. Patrick Yue	A low-power PAM4 receiver using 1/4-rate sampling decoder with adaptive variable-gain rectification.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	Jinho Han, Youngsu Kwon, Yong Cheol Peter Cho, Hoi-Jun Yoo	A 1GHz fault tolerant processor with dynamic lockstep and self-recovering cache for ADAS SoC complying with ISO26262 in automotive electronics.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	Xinchao Shang, Weiwei Shan, Longxing Shi, Xing Wan, Jun Yang 0006	A 0.44V-1.1V 9-transistor transition-detector and half-path error detection technique for low power applications.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	Shunli Ma, Jili Sheng, Ning Li 0007, Junyan Ren	A 7GHz-bandwidth 31.5 GHz FMCW-PLL with novel twin-VCOs structure in 65nm CMOS.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	Abdel Martinez Alonso, Masaya Miyahara, Akira Matsuzawa	A high-speed DDFS MMIC with frequency, phase and amplitude modulations in 65nm CMOS.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	Taehoon Kim, Suhwan Kim	A 12.1mW, 60dB SNR, 8-channel beamforming embedded SAR ADC for ultrasound imaging systems.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	Yi-An Li, Monte Mar, Borivoje Nikolic, Ali M. Niknejad	On-chip spur and phase noise cancellation techniques.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	Xiyuan Tang, Long Chen 0004, Jeonggoo Song, Nan Sun 0001	A 1.5fJ/conv-step 10b 100kS/s SAR ADC with gain-boosted dynamic comparator.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	Yue Chen, Masoud Babaie, Robert Bogdan Staszewski	A 350-mV 2.4-GHz quadrature oscillator with nearly instantaneous start-up using series LC tanks.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	Jianfu Lin, Zheng Song 0002, Nan Qi, Woogeun Rhee, Baoyong Chi	A 77-GHz mixed-mode FMCW signal generator based on bang-bang phase detector.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	Inhee Lee, Dennis Sylvester, David T. Blaauw	Subthreshold voltage reference with nwell/psub diode leakage compensation for low-power high-temperature systems.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	Chen-Che Kao, Sung-En Hsieh, Chih-Cheng Hsieh	A 0.5 V 12-bit SAR ADC using adaptive timedomain comparator with noise optimization.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	Paul Stärke, Vincent Rieß, Corrado Carta, Frank Ellinger	A 173-200 GHz quadrature voltage-controlled oscillator in 130 nm SiGe BiCMOS.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	Cuei-Ling Hsieh, Hong-Shen Chen, Hou-Ru Pan, Jenny Yi-Chun Liu	A 67 GHz dual injection quadrature VCO with -182.9 dBc/Hz FOM in 90-nm CMOS.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	Anh-Tuan Do, Xin Liu 0015	25 fJ/bit, 5Mb/s, 0.3 V true random number generator with capacitively-coupled chaos system and dual-edge sampling scheme.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	Meng-Hsiung Hung, Yi-Shing Shih, Chin-Fu Li, Wei-Kai Hong, Ming-Yeh Hsu, Chih-Hao Chen, Yu-Lun Chen, Chun-Wei Lin, Yuan-Hung Chung	A reconfigurable dual-band WiFi/BT combo transceiver with integrated 2G/BT SP3T, LNA/PA achieving concurrent receiving and wide dynamic range transmitting in 40nm CMOS.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	Jongmi Lee, Jongwoo Lee, Chilun Lo, Jaehoon Lee 0005, In-Young Lee, Byungki Han, Seunghyun Oh, Thomas Byunghak Cho	A reconfigurable analog baseband transformer for multistandard applications in 14nm FinFET CMOS.	A-SSCC	2017	DBLP DOI BibTeX RDF

Publications at "A-SSCC"( http://dblp.L3S.de/Venues/A-SSCC )