Search results for "D-latch"

Hits ?▲	Authors	Title	Venue	Year	Link
16	Giuseppe Scotti, Alessandro Trifiletti, Gaetano Palumbo	A Novel 0.6V MCML D-Latch Topology exploiting Dynamic Body Bias Threshold Lowering.	ICECS	2018	DBLP DOI BibTeX RDF
16	Abdullah Alshehri 0003, Mohammed Al-Qadasi, Abdullah S. Almansouri, Talal Al-Attar, Hossein Fariborzi	StrongARM Latch Comparator Performance Enhancement by Implementing Clocked Forward Body Biasing.	ICECS	2018	DBLP DOI BibTeX RDF
16	Law Foo Kui, M. Rakib Uddin, Nur Musyiirah, Nurazmina Lingas	Design, Simulation, and Analysis of a Digital Electro-optic SR NOR Latch.	TENCON	2018	DBLP DOI BibTeX RDF
16	Joonyeong Kim, Byung-Kil Han, Dong-Soo Kwon	2D Braille Display Module Using Rotating Latch Structured Voice Coil Actuator.	AsiaHaptics	2018	DBLP DOI BibTeX RDF
16	Hector J. Quintero, Manuel Jiménez Través, Maria J. Avedillo, Juan Núñez 0002	Inverting Versus Non-Inverting Dynamic Logic for Two-Phase Latch-free Nanopipelines.	SMACD	2018	DBLP DOI BibTeX RDF
16	Bodo Selmke, Kilian Zinnecker, Philipp Koppermann, Katja Miller, Johann Heyszl, Georg Sigl	Locked out by Latch-up? An Empirical Study on Laser Fault Injection into Arm Cortex-M Processors.	FDTC	2018	DBLP DOI BibTeX RDF
16	Kamlesh Singh, Omar Alejandro Rodriguez Rosas, Hailong Jiao, Jos Huisken, José Pineda de Gyvez	Multi-Bit Pulsed-Latch Based Low Power Synchronous Circuit Design.	ISCAS	2018	DBLP DOI BibTeX RDF
16	Soheil Ziabakhsh, Ghyslain Gagnon, Gordon W. Roberts	An All-Digital High-Resolution Programmable Time-Difference Amplifier Based on Time Latch.	ISCAS	2018	DBLP DOI BibTeX RDF
16	Min-Su Kim, Ah-Reum Kim, Yong-geol Kim, Chunghee Kim, Dong-Yeop Kim, Jong-Woo Kim, Daeseong Lee, Hyun Lee, Jungyul Pyo, Youngmin Shin, Jae Cheol Son	Contention-Free High-Speed Clock-Gate based on Set/Reset Latch for Wide Voltage Scaling.	ISCAS	2018	DBLP DOI BibTeX RDF
16	Qian He, Aibin Yan, Chaoping Lai, Yinlei Zhang, Chunming Liu, Zhile Chen, Zhen Wu, Jie Cui 0004, Huaguo Liang	Novel low cost and DNU online self-recoverable RHBD latch design for nanoscale CMOS.	ISCAS	2018	DBLP DOI BibTeX RDF
16	Aibin Yan, Zhile Chen, Zhengfeng Huang, Xiangsheng Fang, Maoxiang Yi, Jing Guo	Radiation Hardening by Design of a Novel Double-Node-Upset-Tolerant Latch Combined with Layout Technique.	ITC-Asia	2018	DBLP DOI BibTeX RDF
16	Chien-Tung Liu, Zhe-Wei Chang, Shih-Nung Wei, Jinn-Shyan Wang, Tay-Jyi Lin	A Low-Area, Low-Power, and Low-Leakage Error-Detecting Latch for Timing-Error Resilient System Designs.	SoCC	2018	DBLP DOI BibTeX RDF
16	Yuta Yamamoto, Kazuteru Namba	Construction of Latch Design with Complete Double Node Upset Tolerant Capability Using C-Element.	DFT	2018	DBLP DOI BibTeX RDF
16	Joonseop Sim, Mohsen Imani, Woojin Choi, Yeseong Kim, Tajana Rosing	LUPIS: Latch-up based ultra efficient processing in-memory system.	ISQED	2018	DBLP DOI BibTeX RDF
16	Kamlesh Singh, Hailong Jiao, Jos Huisken, Hamed Fatemi, José Pineda de Gyvez	Low power latch based design with smart retiming.	ISQED	2018	DBLP DOI BibTeX RDF
16	Anant Kulkarni, Brajesh Kumar Kaushik, Zeljko Zilic	Implementation and Analysis of Spin-Torque-Based Reversible D-Latch.	CCECE	2018	DBLP DOI BibTeX RDF
16	Xinchao Shang, Weiwei Shan, Jiaming Xu, Minyi Lu, Yiming Xiang, Longxing Shi, Jun Yang 0006	A 0.46V-1.1V Transition-Detector with In-Situ Timing-Error Detection and Correction Based on Pulsed-Latch Design in AES Accelerator.	A-SSCC	2018	DBLP DOI BibTeX RDF
16	Zhao Huang, Chen Zhao, Quan Wang 0006, Zhenyi Wang	Implementation and Analysis of Improved RO PUFs with Latch Structure.	NaNA	2018	DBLP DOI BibTeX RDF
16	Wei Jin 0004, Seongjong Kim, Weifeng He, Zhigang Mao, Mingoo Seok	Near- and Sub-Vt Pipelines Based on Wide-Pulsed-Latch Design Techniques.	IEEE J. Solid State Circuits	2017	DBLP DOI BibTeX RDF
16	Aibin Yan, Zhengfeng Huang, Maoxiang Yi, Xiumin Xu, Yiming Ouyang, Huaguo Liang	Double-Node-Upset-Resilient Latch Design for Nanoscale CMOS Technology.	IEEE Trans. Very Large Scale Integr. Syst.	2017	DBLP DOI BibTeX RDF
16	Yiping Zhang, Ziou Wang, Canyan Zhu, Lijun Zhang	28-nm Latch-Type Sense Amplifier Modification for Coupling Suppression.	IEEE Trans. Very Large Scale Integr. Syst.	2017	DBLP DOI BibTeX RDF
16	Huaguo Liang, Xin Li, Zhengfeng Huang, Aibin Yan, Xiumin Xu	Highly Robust Double Node Upset Resilient Hardened Latch Design.	IEICE Trans. Electron.	2017	DBLP DOI BibTeX RDF
16	Ghobad Zarrinchian, Morteza Saheb Zamani	Latch-Based Structure: A High Resolution and Self-Reference Technique for Hardware Trojan Detection.	IEEE Trans. Computers	2017	DBLP DOI BibTeX RDF
16	Bilal Habib, Jens-Peter Kaps, Kris Gaj	Implementation of efficient SR-Latch PUF on FPGA and SoC devices.	Microprocess. Microsystems	2017	DBLP DOI BibTeX RDF
16	Aibin Yan, Zhengfeng Huang, Xiangsheng Fang, Yiming Ouyang, Honghui Deng	Single event double-upset fully immune and transient pulse filterable latch design for nanoscale CMOS.	Microelectron. J.	2017	DBLP DOI BibTeX RDF
16	Bing Li 0005, Ning Chen 0006, Ulf Schlichtmann	Statistical Timing Analysis for Latch-Controlled Circuits with Reduced Iterations and Graph Transformations.	CoRR	2017	DBLP BibTeX RDF
16	Haibin Wang, Ao Sheng, Shiqi Wang 0010, Jinshun Bi, Li Chen 0001, Xiaofeng Liu	SEU reduction effectiveness of common centroid layout in differential latch at 130-nm CMOS technology.	Microelectron. Reliab.	2017	DBLP DOI BibTeX RDF
16	Pei Liu, Tian Zhao, Feng Liang, Jizhong Zhao, Peilin Jiang	A power-delay-product efficient and SEU-tolerant latch design.	IEICE Electron. Express	2017	DBLP DOI BibTeX RDF
16	Aibin Yan, Huaguo Liang, Yingchun Lu, Zhengfeng Huang	A transient pulse dually filterable and online self-recoverable latch.	IEICE Electron. Express	2017	DBLP DOI BibTeX RDF
16	Hao Cai, You Wang 0002, Lirida A. B. Naviner, Weisheng Zhao	Novel Pulsed-Latch Replacement in Non-Volatile Flip-Flop Core.	ISVLSI	2017	DBLP DOI BibTeX RDF
16	Hamzeh Ahangari, Ihsen Alouani, Özcan Özturk 0001, Smaïl Niar	Reconfigurable Hardened Latch and Flip-Flop for FPGAs.	ISVLSI	2017	DBLP DOI BibTeX RDF
16	Sarah Azimi, Luca Sterpone	Micro Latch-Up Analysis on Ultra-Nanometer VLSI Technologies: A New Monte Carlo Approach.	ISVLSI	2017	DBLP DOI BibTeX RDF
16	Tomohiro Yoshihara, Haruo Yokota	A Concurrency Control Protocol that Selects Accessible Replicated Pages to Avoid Latch Collisions for B-Trees in Manycore Environments.	DEXA (2)	2017	DBLP DOI BibTeX RDF
16	Jose M. Faleiro, Daniel J. Abadi	Latch-free Synchronization in Database Systems: Silver Bullet or Fool's Gold?	CIDR	2017	DBLP BibTeX RDF
16	Wenqiang Wang, Peiquan Jin, Shouhong Wan, Lihua Yue	LFLogging: A Latch-Free Logging Scheme for PCM-Based Big Data Management Systems.	DASFAA Workshops	2017	DBLP DOI BibTeX RDF
16	Wael M. Elsharkasy, Hasan Erdem Yantir, Amin Khajeh, Ahmed M. Eltawil, Fadi J. Kurdahi	Efficient pulsed-latch implementation for multiport register files: work-in-progress.	CASES	2017	DBLP DOI BibTeX RDF
16	Tomonori Tanaka, Kosuke Furuichi, Hiromu Uemura, Ryosuke Noguchi, Natsuyuki Koda, Koki Arauchi, Daichi Omoto, Hiromi Inaba, Keiji Kishine, Shinsuke Nakano, Masafumi Nogawa, Hideyuki Nosaka	25-Gb/s clock and data recovery IC using latch-load combined with CML buffer circuit for delay generation with 65-nm CMOS.	ISCAS	2017	DBLP DOI BibTeX RDF
16	Darjn Esposito, Antonio G. M. Strollo, Massimo Alioto	Power-precision scalable latch memories.	ISCAS	2017	DBLP DOI BibTeX RDF
16	Robert Schmidt 0003, Alberto García Ortiz, Görschwin Fey	Temporal redundancy latch-based architecture for soft error mitigation.	IOLTS	2017	DBLP DOI BibTeX RDF
16	Yongming Ding, Wei Jin 0004, Guanghui He, Weifeng He	Short path padding with multiple-Vt cells for wide-pulsed-latch based circuits at ultra-low voltage.	ASICON	2017	DBLP DOI BibTeX RDF
16	Saki Tajima, Nozomu Togawa, Masao Yanagisawa, Youhua Shi	Soft error tolerant latch designs with low power consumption (invited paper).	ASICON	2017	DBLP DOI BibTeX RDF
16	Monalisa Das, Alak Majumder, Abir J. Mondal, Bidyut K. Bhattacharyya	A 90nm Novel MUX-Dual Latch Design Approach for Gigascale Serializer Application.	iNIS	2017	DBLP DOI BibTeX RDF
16	Aibin Yan, Zhengfeng Huang, Maoxiang Yi, Jie Cui 0004, Huaguo Liang	HLDTL: High-performance, low-cost, and double node upset tolerant latch design.	VTS	2017	DBLP DOI BibTeX RDF
16	Kao-Chi Lee, Kai-Chiang Wu, Chih-Ying Tsai, Mango Chia-Tso Chao	Fast WAT test structure for measuring Vt variance based on latch-based comparators.	VTS	2017	DBLP DOI BibTeX RDF
16	Venkatesh Mani Tripathi, Sandeep Mishra, Jyotishman Saikia, Anup Dandapat	A Low-Voltage 13T Latch-Type Sense Amplifier with Regenerative Feedback for Ultra Speed Memory Access.	VLSID	2017	DBLP DOI BibTeX RDF
16	Manish Gupta, Abhinav Kranti	Suppressing Single Transistor Latch Effect in Energy Efficient Steep Switching Junctionless MOSFETs.	VLSID	2017	DBLP DOI BibTeX RDF
16	Aikaterini Papadopoulou, Vladimir M. Milovanovic, Borivoje Nikolic	A low-voltage low-offset dual strong-arm latch comparator.	A-SSCC	2017	DBLP DOI BibTeX RDF
16	Vivek Tyagi, Mohammad S. Hashmi, Ganesh Raj, Vikas Rana	A 10 MHz, 42 ppm/ °C, 69 μW PVT Compensated Latch Based Oscillator in BCD9S Technology for PCM.	VDAT	2017	DBLP DOI BibTeX RDF
16	Hsiao-Lun Wang, Minghe Zhang, Peter A. Beerel	Retiming of Two-Phase Latch-Based Resilient Circuits.	DAC	2017	DBLP DOI BibTeX RDF
16	Naoya Torii, Dai Yamamoto, Masahiko Takenaka, Tsutomu Matsumoto	Experimental Evaluation on the Resistance of Latch PUFs Implemented on ASIC against FIB-Based Invasive Attacks.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2016	DBLP DOI BibTeX RDF
16	Abdel Martinez Alonso, Masaya Miyahara, Akira Matsuzawa	A 10-bit 6.8-GS/s Direct Digital Frequency Synthesizer Employing Complementary Dual-Phase Latch-Based Architecture.	IEICE Trans. Electron.	2016	DBLP DOI BibTeX RDF
16	Anjan Kumar Pudi N. S, Maryam Shojaei Baghini	Robust Soft Error Tolerant CMOS Latch Configurations.	IEEE Trans. Computers	2016	DBLP DOI BibTeX RDF
16	Christopher Parker, Matthew Daiter, Kareem Omar, Gil Levi, Tal Hassner	The CUDA LATCH Binary Descriptor: Because Sometimes Faster Means Better.	CoRR	2016	DBLP BibTeX RDF
16	Jin-Fa Lin, Ming-Yan Tsai, Kun-Sheng Li, Yun-Rong Jiang, Yu-Shiang Cheng	Low Power SR-Latch Based Flip-Flop Design Using 21 Transistors.	J. Low Power Electron.	2016	DBLP DOI BibTeX RDF
16	Mirko Scholz, Shih-Hung Chen, Geert Hellings, Dimitri Linten	Impact of on- and off-chip protection on the transient-induced latch-up sensitivity of CMOS IC.	Microelectron. Reliab.	2016	DBLP DOI BibTeX RDF
16	Shuang Fan, Bingxu Ning, Zhiyuan Hu, Zhengxuan Zhang, Dawei Bi, Chao Peng, Lei Song, Lihua Dai	Bias dependence of TID induced single transistor latch for 0.13 μm partially depleted SOI input/output NMOSFETs.	Microelectron. Reliab.	2016	DBLP DOI BibTeX RDF
16	Aibin Yan, Huaguo Liang, Zhengfeng Huang, Cuiyun Jiang, Yiming Ouyang, Xuejun Li	An SEU resilient, SET filterable and cost effective latch in presence of PVT variations.	Microelectron. Reliab.	2016	DBLP DOI BibTeX RDF
16	Ramy N. Tadros, Weizhe Hua, Matheus T. Moreira, Ney Laert Vilar Calazans, Peter A. Beerel	A Low-Power Low-Area Error-Detecting Latch for Resilient Architectures in 28-nm FDSOI.	IEEE Trans. Circuits Syst. II Express Briefs	2016	DBLP DOI BibTeX RDF
16	Naoya Torii, Dai Yamamoto, Tsutomu Matsumoto	Evaluation of Latch-based Physical Random Number Generator Implementation on 40 nm ASICs.	TrustED@CCS	2016	DBLP DOI BibTeX RDF
16	Leïla Khanfir, Jaouhar Mouine	A new latch comparator with tunable hysteresis.	ICM	2016	DBLP DOI BibTeX RDF
16	Aibin Yan, Zhengfeng Huang, Xiangsheng Fang, Xiaolin Xu, Huaguo Liang	Novel Low Cost and Double Node Upset Tolerant Latch Design for Nanoscale CMOS Technology.	ATS	2016	DBLP DOI BibTeX RDF
16	Jotham Vaddaboina Manoranjan, Kenneth S. Stevens	Reconfigurable circuit for implementation of family of 4-phase latch protocols.	FPL	2016	DBLP DOI BibTeX RDF
16	Akanksha Singh, Ayushi Marwah, Shyam Akashe	Novel Gating Technique in D-Latch for Low Power Application.	ICTCS	2016	DBLP DOI BibTeX RDF
16	Marc Pons 0001, Thanh-Chau Le, Claude Arm, Daniel Séverac, Jean-Luc Nagel, Marc-Nicolas Morgan, Stéphane Emery	Sub-threshold latch-based icyflex2 32-bit processor with wide supply range operation.	ESSCIRC	2016	DBLP DOI BibTeX RDF
16	Chih-Cheng Hsu, Mark Po-Hung Lin, Masanori Hashimoto	Latch Clustering for Minimizing Detection-to-Boosting Latency Toward Low-Power Resilient Circuits.	SLIP	2016	DBLP DOI BibTeX RDF
16	Weizhe Hua, Ramy N. Tadros, Peter A. Beerel	Low Area, Low Power, Robust, Highly Sensitive Error Detecting Latch for Resilient Architectures.	ISLPED	2016	DBLP DOI BibTeX RDF
16	Abhishek Roy 0002, Benton H. Calhoun	Exploring circuit robustness to power supply variation in low-voltage latch and register-based digital systems.	ISCAS	2016	DBLP DOI BibTeX RDF
16	Poorna Marthi, Nazir Hossain, Jean-François Millithaler, Martin Margala	A new level sensitive D Latch using Ballistic nanodevices.	ISCAS	2016	DBLP DOI BibTeX RDF
16	Naoya Torii, Dai Yamamoto, Tsutomu Matsumoto	Evaluation of Latch-Based PUFs Implemented on 40 nm ASICs.	CANDAR	2016	DBLP DOI BibTeX RDF
16	Adam Watkins, Spyros Tragoudas	A Highly Robust Double Node Upset Tolerant latch.	DFT	2016	DBLP DOI BibTeX RDF
16	Hiroki Ueno, Kazuteru Namba	Construction of a soft error (SEU) hardened Latch with high critical charge.	DFT	2016	DBLP DOI BibTeX RDF
16	Amir Ardakani, Shahriar Baradaran Shokouhi	A secure and area-efficient FPGA-based SR-Latch PUF.	IST	2016	DBLP DOI BibTeX RDF
16	Gil Levi, Tal Hassner	LATCH: Learned arrangements of three patch codes.	WACV	2016	DBLP DOI BibTeX RDF
16	Christopher Parker, Matthew Daiter, Kareem Omar, Gil Levi, Tal Hassner	The CUDA LATCH Binary Descriptor: Because Sometimes Faster Means Better.	ECCV Workshops (3)	2016	DBLP DOI BibTeX RDF
16	Yiping Zhang, Ziou Wang, Canyan Zhu, Lijun Zhang, Aiming Ji, Lingfeng Mao 0001	28nm latch type sense amplifier coupling effect analysis.	ISIC	2016	DBLP DOI BibTeX RDF
16	Wei Jin 0004, Seongjong Kim, Weifeng He, Zhigang Mao, Mingoo Seok	A 0.35V 1.3pJ/cycle 20MHz 8-bit 8-tap FIR core based on wide-pulsed-latch pipelines.	A-SSCC	2016	DBLP DOI BibTeX RDF
16	Disha Arora, Anil Kumar Gundu, Mohammad S. Hashmi	A high speed low voltage latch type sense amplifier for non-volatile memory.	VDAT	2016	DBLP DOI BibTeX RDF
16	A. Purushothaman	Analysis of regeneration time constant of dynamic latch using Adomian Decomposition method.	VDAT	2016	DBLP DOI BibTeX RDF
16	Jong-In Kim, Dong-Ryeol Oh, Dong-Shin Jo, Ba-Ro-Saim Sung, Seung-Tak Ryu	A 65 nm CMOS 7b 2 GS/s 20.7 mW Flash ADC With Cascaded Latch Interpolation.	IEEE J. Solid State Circuits	2015	DBLP DOI BibTeX RDF
16	Aibin Yan, Huaguo Liang, Zhengfeng Huang, Cuiyun Jiang, Maoxiang Yi	A Self-Recoverable, Frequency-Aware and Cost-Effective Robust Latch Design for Nanoscale CMOS Technology.	IEICE Trans. Electron.	2015	DBLP DOI BibTeX RDF
16	Ramin Rajaei, Mahmoud Tabandeh, Mahdi Fazeli	Single Event Multiple Upset (SEMU) Tolerant Latch Designs in Presence of Process and Temperature Variations.	J. Circuits Syst. Comput.	2015	DBLP DOI BibTeX RDF
16	Zhengfeng Huang, Huaguo Liang, Sybille Hellebrand	A High Performance SEU Tolerant Latch.	J. Electron. Test.	2015	DBLP DOI BibTeX RDF
16	Yuanqing Li, Haibin Wang, Suying Yao, Xi Yan, Zhiyuan Gao, Jiangtao Xu	Double Node Upsets Hardened Latch Circuits.	J. Electron. Test.	2015	DBLP DOI BibTeX RDF
16	Gil Levi, Tal Hassner	LATCH: Learned Arrangements of Three Patch Codes.	CoRR	2015	DBLP BibTeX RDF
16	Qi Jiang, Huihui Yuan, Yang Wang, Xiangliang Jin	Design and analyze of transient-induced latch-up in RS485 transceiver with on-chip TVS.	Microelectron. Reliab.	2015	DBLP DOI BibTeX RDF
16	Chunhua Qi, Liyi Xiao, Jing Guo 0004, Tianqi Wang	Low cost and highly reliable radiation hardened latch design in 65 nm CMOS technology.	Microelectron. Reliab.	2015	DBLP DOI BibTeX RDF
16	Yonghong Tao, Andreas Hierlemann, Yong Lian 0001	A Frequency-Domain Analysis of Latch Comparator Offset due to Load Capacitor Mismatch.	IEEE Trans. Circuits Syst. II Express Briefs	2015	DBLP DOI BibTeX RDF
16	Byungkyu Song, Taehui Na, Jisu Kim, Jung Pill Kim, Seung-Hyuk Kang, Seong-Ook Jung	Latch Offset Cancellation Sense Amplifier for Deep Submicrometer STT-RAM.	IEEE Trans. Circuits Syst. I Regul. Pap.	2015	DBLP DOI BibTeX RDF
16	Nikolaos Eftaxiopoulos, Nicholas Axelos, Georgios Zervakis 0001, Kostas Tsoumanis, Kiamal Z. Pekmestzi	Delta DICE: A Double Node Upset resilient latch.	MWSCAS	2015	DBLP DOI BibTeX RDF
16	Nikolaos Eftaxiopoulos, Nicholas Axelos, Kiamal Z. Pekmestzi	DONUT: A Double Node Upset Tolerant Latch.	ISVLSI	2015	DBLP DOI BibTeX RDF
16	Anush Bekal, Rohit Joshi, Manish Goswami, Babu R. Singh, Ashok Srivatsava	An Improved Dynamic Latch Based Comparator for 8-Bit Asynchronous SAR ADC.	ISVLSI	2015	DBLP DOI BibTeX RDF
16	Taiki Uemura, Takashi Kato, Hideya Matsuyama, Masanori Hashimoto	Soft error immune latch design for 20 nm bulk CMOS.	IRPS	2015	DBLP DOI BibTeX RDF
16	Tingting Pang, Wang Kang 0001, Yi Ran, Youguang Zhang, Weifeng Lv, Weisheng Zhao	Nonvolatile radiation hardened DICE latch.	NVMTS	2015	DBLP DOI BibTeX RDF
16	Bilal Habib, Jens-Peter Kaps, Kris Gaj	Efficient SR-Latch PUF.	ARC	2015	DBLP DOI BibTeX RDF
16	Katerina Katsarou, Yiorgos Tsiatouhas	Soft error immune latch under SEU related double-node charge collection.	IOLTS	2015	DBLP DOI BibTeX RDF
16	Tse-Ching Wu, Chien-Ju Chen, Yin-Nien Chen, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang	Evaluation of energy-efficient latch circuits with hybrid tunneling FET and FinFET devices for ultra-low-voltage applications.	SoCC	2015	DBLP DOI BibTeX RDF
16	Abdel Martinez Alonso, Masaya Miyahara, Akira Matsuzawa	A novel direct digital frequency synthesizer employing complementary dual-phase latch-based architecture.	ASICON	2015	DBLP DOI BibTeX RDF
16	Saki Tajima, Youhua Shi, Nozomu Togawa, Masao Yanagisawa	A low-power soft error tolerant latch scheme.	ASICON	2015	DBLP DOI BibTeX RDF
16	Arvind Kumar Sharma, Yogendra Sharma, Sudeb Dasgupta, Bulusu Anand	Efficient static D-latch standard cell characterization using a novel setup time model.	ISQED	2015	DBLP DOI BibTeX RDF
16	Jae-Won Jang, Swaroop Ghosh	Design and analysis of novel SRAM PUFs with embedded latch for robustness.	ISQED	2015	DBLP DOI BibTeX RDF