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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 382 occurrences of 260 keywords
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Results
Found 861 publication records. Showing 859 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
16 | Giuseppe Scotti, Alessandro Trifiletti, Gaetano Palumbo |
A Novel 0.6V MCML D-Latch Topology exploiting Dynamic Body Bias Threshold Lowering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 25th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2018, Bordeaux, France, December 9-12, 2018, pp. 233-236, 2018, IEEE, 978-1-5386-9562-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Abdullah Alshehri 0003, Mohammed Al-Qadasi, Abdullah S. Almansouri, Talal Al-Attar, Hossein Fariborzi |
StrongARM Latch Comparator Performance Enhancement by Implementing Clocked Forward Body Biasing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 25th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2018, Bordeaux, France, December 9-12, 2018, pp. 229-232, 2018, IEEE, 978-1-5386-9562-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Law Foo Kui, M. Rakib Uddin, Nur Musyiirah, Nurazmina Lingas |
Design, Simulation, and Analysis of a Digital Electro-optic SR NOR Latch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
TENCON ![In: TENCON 2018 - 2018 IEEE Region 10 Conference, Jeju, South Korea, October 28-31, 2018, pp. 2422-2425, 2018, IEEE, 978-1-5386-5457-6. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Joonyeong Kim, Byung-Kil Han, Dong-Soo Kwon |
2D Braille Display Module Using Rotating Latch Structured Voice Coil Actuator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AsiaHaptics ![In: Haptic Interaction - Perception, Devices and Algorithms, AsiaHaptics 2018, Incheon, Korea, 14-16 November 2018, pp. 223-225, 2018, Springer, 978-981-13-3193-0. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Hector J. Quintero, Manuel Jiménez Través, Maria J. Avedillo, Juan Núñez 0002 |
Inverting Versus Non-Inverting Dynamic Logic for Two-Phase Latch-free Nanopipelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SMACD ![In: 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2018, Prague, Czech Republic, July 2-5, 2018, pp. 81-84, 2018, IEEE, 978-1-5386-5153-7. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Bodo Selmke, Kilian Zinnecker, Philipp Koppermann, Katja Miller, Johann Heyszl, Georg Sigl |
Locked out by Latch-up? An Empirical Study on Laser Fault Injection into Arm Cortex-M Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDTC ![In: 2018 Workshop on Fault Diagnosis and Tolerance in Cryptography, FDTC 2018, Amsterdam, The Netherlands, September 13, 2018, pp. 7-14, 2018, IEEE Computer Society, 978-1-5386-8197-8. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Kamlesh Singh, Omar Alejandro Rodriguez Rosas, Hailong Jiao, Jos Huisken, José Pineda de Gyvez |
Multi-Bit Pulsed-Latch Based Low Power Synchronous Circuit Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2018, 27-30 May 2018, Florence, Italy, pp. 1-5, 2018, IEEE, 978-1-5386-4881-0. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Soheil Ziabakhsh, Ghyslain Gagnon, Gordon W. Roberts |
An All-Digital High-Resolution Programmable Time-Difference Amplifier Based on Time Latch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2018, 27-30 May 2018, Florence, Italy, pp. 1-5, 2018, IEEE, 978-1-5386-4881-0. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Min-Su Kim, Ah-Reum Kim, Yong-geol Kim, Chunghee Kim, Dong-Yeop Kim, Jong-Woo Kim, Daeseong Lee, Hyun Lee, Jungyul Pyo, Youngmin Shin, Jae Cheol Son |
Contention-Free High-Speed Clock-Gate based on Set/Reset Latch for Wide Voltage Scaling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2018, 27-30 May 2018, Florence, Italy, pp. 1-5, 2018, IEEE, 978-1-5386-4881-0. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Qian He, Aibin Yan, Chaoping Lai, Yinlei Zhang, Chunming Liu, Zhile Chen, Zhen Wu, Jie Cui 0004, Huaguo Liang |
Novel low cost and DNU online self-recoverable RHBD latch design for nanoscale CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2018, 27-30 May 2018, Florence, Italy, pp. 1-5, 2018, IEEE, 978-1-5386-4881-0. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Aibin Yan, Zhile Chen, Zhengfeng Huang, Xiangsheng Fang, Maoxiang Yi, Jing Guo |
Radiation Hardening by Design of a Novel Double-Node-Upset-Tolerant Latch Combined with Layout Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC-Asia ![In: IEEE International Test Conference in Asia, ITC-Asia 2018, Harbin, China, August 15-17, 2018, pp. 49-54, 2018, IEEE, 978-1-5386-5180-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Chien-Tung Liu, Zhe-Wei Chang, Shih-Nung Wei, Jinn-Shyan Wang, Tay-Jyi Lin |
A Low-Area, Low-Power, and Low-Leakage Error-Detecting Latch for Timing-Error Resilient System Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: 31st IEEE International System-on-Chip Conference, SOCC 2018, Arlington, VA, USA, September 4-7, 2018, pp. 1-6, 2018, IEEE, 978-1-5386-1491-4. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Yuta Yamamoto, Kazuteru Namba |
Construction of Latch Design with Complete Double Node Upset Tolerant Capability Using C-Element. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2018, Chicago, IL, USA, October 8-10, 2018, pp. 1-6, 2018, IEEE Computer Society, 978-1-5386-8398-9. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Joonseop Sim, Mohsen Imani, Woojin Choi, Yeseong Kim, Tajana Rosing |
LUPIS: Latch-up based ultra efficient processing in-memory system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 19th International Symposium on Quality Electronic Design, ISQED 2018, Santa Clara, CA, USA, March 13-14, 2018, pp. 55-60, 2018, IEEE, 978-1-5386-1214-9. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Kamlesh Singh, Hailong Jiao, Jos Huisken, Hamed Fatemi, José Pineda de Gyvez |
Low power latch based design with smart retiming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 19th International Symposium on Quality Electronic Design, ISQED 2018, Santa Clara, CA, USA, March 13-14, 2018, pp. 329-334, 2018, IEEE, 978-1-5386-1214-9. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Anant Kulkarni, Brajesh Kumar Kaushik, Zeljko Zilic |
Implementation and Analysis of Spin-Torque-Based Reversible D-Latch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCECE ![In: 2018 IEEE Canadian Conference on Electrical & Computer Engineering, CCECE 2018, Quebec, QC, Canada, May 13-16, 2018, pp. 1-4, 2018, IEEE, 978-1-5386-2410-4. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Xinchao Shang, Weiwei Shan, Jiaming Xu, Minyi Lu, Yiming Xiang, Longxing Shi, Jun Yang 0006 |
A 0.46V-1.1V Transition-Detector with In-Situ Timing-Error Detection and Correction Based on Pulsed-Latch Design in AES Accelerator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
A-SSCC ![In: IEEE Asian Solid-State Circuits Conference, A-SSCC 2018, Tainan, Taiwan, November 5-7, 2018, pp. 1-4, 2018, IEEE, 978-1-5386-6413-1. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Zhao Huang, Chen Zhao, Quan Wang 0006, Zhenyi Wang |
Implementation and Analysis of Improved RO PUFs with Latch Structure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NaNA ![In: International Conference on Networking and Network Applications, NaNA 2018, Xi'an, China, October 12-15, 2018, pp. 318-323, 2018, IEEE, 978-1-5386-8303-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Wei Jin 0004, Seongjong Kim, Weifeng He, Zhigang Mao, Mingoo Seok |
Near- and Sub-Vt Pipelines Based on Wide-Pulsed-Latch Design Techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 52(9), pp. 2475-2487, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Aibin Yan, Zhengfeng Huang, Maoxiang Yi, Xiumin Xu, Yiming Ouyang, Huaguo Liang |
Double-Node-Upset-Resilient Latch Design for Nanoscale CMOS Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 25(6), pp. 1978-1982, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Yiping Zhang, Ziou Wang, Canyan Zhu, Lijun Zhang |
28-nm Latch-Type Sense Amplifier Modification for Coupling Suppression. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 25(5), pp. 1767-1773, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Huaguo Liang, Xin Li, Zhengfeng Huang, Aibin Yan, Xiumin Xu |
Highly Robust Double Node Upset Resilient Hardened Latch Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 100-C(5), pp. 496-503, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Ghobad Zarrinchian, Morteza Saheb Zamani |
Latch-Based Structure: A High Resolution and Self-Reference Technique for Hardware Trojan Detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 66(1), pp. 100-113, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Bilal Habib, Jens-Peter Kaps, Kris Gaj |
Implementation of efficient SR-Latch PUF on FPGA and SoC devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 53, pp. 92-105, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Aibin Yan, Zhengfeng Huang, Xiangsheng Fang, Yiming Ouyang, Honghui Deng |
Single event double-upset fully immune and transient pulse filterable latch design for nanoscale CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 61, pp. 43-50, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Bing Li 0005, Ning Chen 0006, Ulf Schlichtmann |
Statistical Timing Analysis for Latch-Controlled Circuits with Reduced Iterations and Graph Transformations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1705.04980, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP BibTeX RDF |
|
16 | Haibin Wang, Ao Sheng, Shiqi Wang 0010, Jinshun Bi, Li Chen 0001, Xiaofeng Liu |
SEU reduction effectiveness of common centroid layout in differential latch at 130-nm CMOS technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 72, pp. 39-44, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Pei Liu, Tian Zhao, Feng Liang, Jizhong Zhao, Peilin Jiang |
A power-delay-product efficient and SEU-tolerant latch design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 14(23), pp. 20170972, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Aibin Yan, Huaguo Liang, Yingchun Lu, Zhengfeng Huang |
A transient pulse dually filterable and online self-recoverable latch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 14(2), pp. 20160911, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Hao Cai, You Wang 0002, Lirida A. B. Naviner, Weisheng Zhao |
Novel Pulsed-Latch Replacement in Non-Volatile Flip-Flop Core. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017, Bochum, Germany, July 3-5, 2017, pp. 57-61, 2017, IEEE Computer Society, 978-1-5090-6762-6. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Hamzeh Ahangari, Ihsen Alouani, Özcan Özturk 0001, Smaïl Niar |
Reconfigurable Hardened Latch and Flip-Flop for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017, Bochum, Germany, July 3-5, 2017, pp. 433-438, 2017, IEEE Computer Society, 978-1-5090-6762-6. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Sarah Azimi, Luca Sterpone |
Micro Latch-Up Analysis on Ultra-Nanometer VLSI Technologies: A New Monte Carlo Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017, Bochum, Germany, July 3-5, 2017, pp. 338-343, 2017, IEEE Computer Society, 978-1-5090-6762-6. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Tomohiro Yoshihara, Haruo Yokota |
A Concurrency Control Protocol that Selects Accessible Replicated Pages to Avoid Latch Collisions for B-Trees in Manycore Environments. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DEXA (2) ![In: Database and Expert Systems Applications - 28th International Conference, DEXA 2017, Lyon, France, August 28-31, 2017, Proceedings, Part II, pp. 172-189, 2017, Springer, 978-3-319-64470-7. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Jose M. Faleiro, Daniel J. Abadi |
Latch-free Synchronization in Database Systems: Silver Bullet or Fool's Gold? ![Search on Bibsonomy](Pics/bibsonomy.png) |
CIDR ![In: 8th Biennial Conference on Innovative Data Systems Research, CIDR 2017, Chaminade, CA, USA, January 8-11, 2017, Online Proceedings, pp. 9-, 2017, www.cidrdb.org. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP BibTeX RDF |
|
16 | Wenqiang Wang, Peiquan Jin, Shouhong Wan, Lihua Yue |
LFLogging: A Latch-Free Logging Scheme for PCM-Based Big Data Management Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DASFAA Workshops ![In: Database Systems for Advanced Applications - DASFAA 2017 International Workshops: BDMS, BDQM, SeCoP, and DMMOOC, Suzhou, China, March 27-30, 2017, Proceedings, pp. 90-102, 2017, Springer, 978-3-319-55704-5. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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16 | Wael M. Elsharkasy, Hasan Erdem Yantir, Amin Khajeh, Ahmed M. Eltawil, Fadi J. Kurdahi |
Efficient pulsed-latch implementation for multiport register files: work-in-progress. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2017 International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2017, Seoul, Republic of Korea, October 15-20, 2017, pp. 5:1-5:2, 2017, ACM, 978-1-4503-5184-3. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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16 | Tomonori Tanaka, Kosuke Furuichi, Hiromu Uemura, Ryosuke Noguchi, Natsuyuki Koda, Koki Arauchi, Daichi Omoto, Hiromi Inaba, Keiji Kishine, Shinsuke Nakano, Masafumi Nogawa, Hideyuki Nosaka |
25-Gb/s clock and data recovery IC using latch-load combined with CML buffer circuit for delay generation with 65-nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2017, Baltimore, MD, USA, May 28-31, 2017, pp. 1-4, 2017, IEEE, 978-1-4673-6853-7. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Darjn Esposito, Antonio G. M. Strollo, Massimo Alioto |
Power-precision scalable latch memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2017, Baltimore, MD, USA, May 28-31, 2017, pp. 1-4, 2017, IEEE, 978-1-4673-6853-7. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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16 | Robert Schmidt 0003, Alberto García Ortiz, Görschwin Fey |
Temporal redundancy latch-based architecture for soft error mitigation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 23rd IEEE International Symposium on On-Line Testing and Robust System Design, IOLTS 2017, Thessaloniki, Greece, July 3-5, 2017, pp. 240-243, 2017, IEEE, 978-1-5386-0352-9. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Yongming Ding, Wei Jin 0004, Guanghui He, Weifeng He |
Short path padding with multiple-Vt cells for wide-pulsed-latch based circuits at ultra-low voltage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASICON ![In: 12th IEEE International Conference on ASIC, ASICON 2017, Guiyang, China, October 25-28, 2017, pp. 985-988, 2017, IEEE, 978-1-5090-6625-4. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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16 | Saki Tajima, Nozomu Togawa, Masao Yanagisawa, Youhua Shi |
Soft error tolerant latch designs with low power consumption (invited paper). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASICON ![In: 12th IEEE International Conference on ASIC, ASICON 2017, Guiyang, China, October 25-28, 2017, pp. 52-55, 2017, IEEE, 978-1-5090-6625-4. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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16 | Monalisa Das, Alak Majumder, Abir J. Mondal, Bidyut K. Bhattacharyya |
A 90nm Novel MUX-Dual Latch Design Approach for Gigascale Serializer Application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
iNIS ![In: IEEE International Symposium on Nanoelectronic and Information Systems, iNIS 2017, Bhopal, India, December 18-20, 2017, pp. 210-214, 2017, IEEE, 978-1-5386-1356-6. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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16 | Aibin Yan, Zhengfeng Huang, Maoxiang Yi, Jie Cui 0004, Huaguo Liang |
HLDTL: High-performance, low-cost, and double node upset tolerant latch design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 35th IEEE VLSI Test Symposium, VTS 2017, Las Vegas, NV, USA, April 9-12, 2017, pp. 1-6, 2017, IEEE Computer Society, 978-1-5090-4482-5. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Kao-Chi Lee, Kai-Chiang Wu, Chih-Ying Tsai, Mango Chia-Tso Chao |
Fast WAT test structure for measuring Vt variance based on latch-based comparators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 35th IEEE VLSI Test Symposium, VTS 2017, Las Vegas, NV, USA, April 9-12, 2017, pp. 1-6, 2017, IEEE Computer Society, 978-1-5090-4482-5. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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16 | Venkatesh Mani Tripathi, Sandeep Mishra, Jyotishman Saikia, Anup Dandapat |
A Low-Voltage 13T Latch-Type Sense Amplifier with Regenerative Feedback for Ultra Speed Memory Access. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSID ![In: 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, VLSID 2017, Hyderabad, India, January 7-11, 2017, pp. 341-346, 2017, IEEE Computer Society, 978-1-5090-5740-5. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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16 | Manish Gupta, Abhinav Kranti |
Suppressing Single Transistor Latch Effect in Energy Efficient Steep Switching Junctionless MOSFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSID ![In: 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, VLSID 2017, Hyderabad, India, January 7-11, 2017, pp. 441-446, 2017, IEEE Computer Society, 978-1-5090-5740-5. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Aikaterini Papadopoulou, Vladimir M. Milovanovic, Borivoje Nikolic |
A low-voltage low-offset dual strong-arm latch comparator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
A-SSCC ![In: IEEE Asian Solid-State Circuits Conference, A-SSCC 2017, Seoul, Korea (South), November 6-8, 2017, pp. 281-284, 2017, IEEE, 978-1-5386-3178-2. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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16 | Vivek Tyagi, Mohammad S. Hashmi, Ganesh Raj, Vikas Rana |
A 10 MHz, 42 ppm/ °C, 69 μW PVT Compensated Latch Based Oscillator in BCD9S Technology for PCM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: VLSI Design and Test - 21st International Symposium, VDAT 2017, Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers, pp. 631-645, 2017, Springer, 978-981-10-7469-1. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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16 | Hsiao-Lun Wang, Minghe Zhang, Peter A. Beerel |
Retiming of Two-Phase Latch-Based Resilient Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 54th Annual Design Automation Conference, DAC 2017, Austin, TX, USA, June 18-22, 2017, pp. 70:1-70:6, 2017, ACM, 978-1-4503-4927-7. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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16 | Naoya Torii, Dai Yamamoto, Masahiko Takenaka, Tsutomu Matsumoto |
Experimental Evaluation on the Resistance of Latch PUFs Implemented on ASIC against FIB-Based Invasive Attacks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(1), pp. 118-129, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
16 | Abdel Martinez Alonso, Masaya Miyahara, Akira Matsuzawa |
A 10-bit 6.8-GS/s Direct Digital Frequency Synthesizer Employing Complementary Dual-Phase Latch-Based Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 99-C(10), pp. 1200-1210, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
16 | Anjan Kumar Pudi N. S, Maryam Shojaei Baghini |
Robust Soft Error Tolerant CMOS Latch Configurations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 65(9), pp. 2820-2834, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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16 | Christopher Parker, Matthew Daiter, Kareem Omar, Gil Levi, Tal Hassner |
The CUDA LATCH Binary Descriptor: Because Sometimes Faster Means Better. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1609.03986, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP BibTeX RDF |
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16 | Jin-Fa Lin, Ming-Yan Tsai, Kun-Sheng Li, Yun-Rong Jiang, Yu-Shiang Cheng |
Low Power SR-Latch Based Flip-Flop Design Using 21 Transistors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Low Power Electron. ![In: J. Low Power Electron. 12(2), pp. 112-116, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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16 | Mirko Scholz, Shih-Hung Chen, Geert Hellings, Dimitri Linten |
Impact of on- and off-chip protection on the transient-induced latch-up sensitivity of CMOS IC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 57, pp. 53-58, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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16 | Shuang Fan, Bingxu Ning, Zhiyuan Hu, Zhengxuan Zhang, Dawei Bi, Chao Peng, Lei Song, Lihua Dai |
Bias dependence of TID induced single transistor latch for 0.13 μm partially depleted SOI input/output NMOSFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 56, pp. 1-9, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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16 | Aibin Yan, Huaguo Liang, Zhengfeng Huang, Cuiyun Jiang, Yiming Ouyang, Xuejun Li |
An SEU resilient, SET filterable and cost effective latch in presence of PVT variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 63, pp. 239-250, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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16 | Ramy N. Tadros, Weizhe Hua, Matheus T. Moreira, Ney Laert Vilar Calazans, Peter A. Beerel |
A Low-Power Low-Area Error-Detecting Latch for Resilient Architectures in 28-nm FDSOI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 63-II(9), pp. 858-862, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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16 | Naoya Torii, Dai Yamamoto, Tsutomu Matsumoto |
Evaluation of Latch-based Physical Random Number Generator Implementation on 40 nm ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
TrustED@CCS ![In: Proceedings of the 6th International Workshop on Trustworthy Embedded Devices, TrustED@CCS 16, Vienna, Austria, October 28, 2016, pp. 23-30, 2016, ACM, 978-1-4503-4567-5. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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16 | Leïla Khanfir, Jaouhar Mouine |
A new latch comparator with tunable hysteresis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICM ![In: 28th International Conference on Microelectronics, ICM 2016, Giza, Egypt, December 17-20, 2016, pp. 261-264, 2016, IEEE, 978-1-5090-5721-4. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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16 | Aibin Yan, Zhengfeng Huang, Xiangsheng Fang, Xiaolin Xu, Huaguo Liang |
Novel Low Cost and Double Node Upset Tolerant Latch Design for Nanoscale CMOS Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ATS ![In: 25th IEEE Asian Test Symposium, ATS 2016, Hiroshima, Japan, November 21-24, 2016, pp. 252-256, 2016, IEEE Computer Society, 978-1-5090-3809-1. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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16 | Jotham Vaddaboina Manoranjan, Kenneth S. Stevens |
Reconfigurable circuit for implementation of family of 4-phase latch protocols. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 26th International Conference on Field Programmable Logic and Applications, FPL 2016, Lausanne, Switzerland, August 29 - September 2, 2016, pp. 1-4, 2016, IEEE, 978-2-8399-1844-2. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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16 | Akanksha Singh, Ayushi Marwah, Shyam Akashe |
Novel Gating Technique in D-Latch for Low Power Application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICTCS ![In: ICTCS, pp. 91:1-91:5, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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16 | Marc Pons 0001, Thanh-Chau Le, Claude Arm, Daniel Séverac, Jean-Luc Nagel, Marc-Nicolas Morgan, Stéphane Emery |
Sub-threshold latch-based icyflex2 32-bit processor with wide supply range operation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSCIRC ![In: ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, Lausanne, Switzerland, September 12-15, 2016, pp. 41-44, 2016, IEEE, 978-1-5090-2972-3. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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16 | Chih-Cheng Hsu, Mark Po-Hung Lin, Masanori Hashimoto |
Latch Clustering for Minimizing Detection-to-Boosting Latency Toward Low-Power Resilient Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: Proceedings of the 18th System Level Interconnect Prediction Workshop, SLIP 2016, Austin, TX, USA, June 4, 2016, pp. 2:1-2:6, 2016, ACM, 978-1-4503-4430-2. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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16 | Weizhe Hua, Ramy N. Tadros, Peter A. Beerel |
Low Area, Low Power, Robust, Highly Sensitive Error Detecting Latch for Resilient Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2016 International Symposium on Low Power Electronics and Design, ISLPED 2016, San Francisco Airport, CA, USA, August 08 - 10, 2016, pp. 16-21, 2016, ACM, 978-1-4503-4185-1. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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16 | Abhishek Roy 0002, Benton H. Calhoun |
Exploring circuit robustness to power supply variation in low-voltage latch and register-based digital systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2016, Montréal, QC, Canada, May 22-25, 2016, pp. 273-276, 2016, IEEE, 978-1-4799-5341-7. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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16 | Poorna Marthi, Nazir Hossain, Jean-François Millithaler, Martin Margala |
A new level sensitive D Latch using Ballistic nanodevices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2016, Montréal, QC, Canada, May 22-25, 2016, pp. 1882-1885, 2016, IEEE, 978-1-4799-5341-7. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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16 | Naoya Torii, Dai Yamamoto, Tsutomu Matsumoto |
Evaluation of Latch-Based PUFs Implemented on 40 nm ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CANDAR ![In: Fourth International Symposium on Computing and Networking, CANDAR 2016, Hiroshima, Japan, November 22-25, 2016, pp. 642-648, 2016, IEEE Computer Society, 978-1-5090-2655-5. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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16 | Adam Watkins, Spyros Tragoudas |
A Highly Robust Double Node Upset Tolerant latch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2016, Storrs, CT, USA, September 19-20, 2016, pp. 15-20, 2016, IEEE Computer Society, 978-1-5090-3623-3. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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16 | Hiroki Ueno, Kazuteru Namba |
Construction of a soft error (SEU) hardened Latch with high critical charge. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2016, Storrs, CT, USA, September 19-20, 2016, pp. 27-30, 2016, IEEE Computer Society, 978-1-5090-3623-3. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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16 | Amir Ardakani, Shahriar Baradaran Shokouhi |
A secure and area-efficient FPGA-based SR-Latch PUF. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IST ![In: 8th International Symposium on Telecommunications, IST 2016, Tehran, Iran, September 27-28, 2016, pp. 94-99, 2016, IEEE, 978-1-5090-3435-2. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
16 | Gil Levi, Tal Hassner |
LATCH: Learned arrangements of three patch codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WACV ![In: 2016 IEEE Winter Conference on Applications of Computer Vision, WACV 2016, Lake Placid, NY, USA, March 7-10, 2016, pp. 1-9, 2016, IEEE Computer Society, 978-1-5090-0641-0. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
16 | Christopher Parker, Matthew Daiter, Kareem Omar, Gil Levi, Tal Hassner |
The CUDA LATCH Binary Descriptor: Because Sometimes Faster Means Better. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECCV Workshops (3) ![In: Computer Vision - ECCV 2016 Workshops - Amsterdam, The Netherlands, October 8-10 and 15-16, 2016, Proceedings, Part III, pp. 685-697, 2016, 978-3-319-49408-1. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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16 | Yiping Zhang, Ziou Wang, Canyan Zhu, Lijun Zhang, Aiming Ji, Lingfeng Mao 0001 |
28nm latch type sense amplifier coupling effect analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISIC ![In: International Symposium on Integrated Circuits, ISIC 2016, Singapore, December 12-14, 2016, pp. 1-4, 2016, IEEE, 978-1-4673-9019-4. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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16 | Wei Jin 0004, Seongjong Kim, Weifeng He, Zhigang Mao, Mingoo Seok |
A 0.35V 1.3pJ/cycle 20MHz 8-bit 8-tap FIR core based on wide-pulsed-latch pipelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
A-SSCC ![In: IEEE Asian Solid-State Circuits Conference, A-SSCC 2016, Toyama, Japan, November 7-9, 2016, pp. 129-132, 2016, IEEE, 978-1-5090-3699-8. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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16 | Disha Arora, Anil Kumar Gundu, Mohammad S. Hashmi |
A high speed low voltage latch type sense amplifier for non-volatile memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: 20th International Symposium on VLSI Design and Test, VDAT 2016, Guwahati, India, May 24-27, 2016, pp. 1-5, 2016, IEEE, 978-1-5090-1422-4. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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16 | A. Purushothaman |
Analysis of regeneration time constant of dynamic latch using Adomian Decomposition method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: 20th International Symposium on VLSI Design and Test, VDAT 2016, Guwahati, India, May 24-27, 2016, pp. 1-6, 2016, IEEE, 978-1-5090-1422-4. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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16 | Jong-In Kim, Dong-Ryeol Oh, Dong-Shin Jo, Ba-Ro-Saim Sung, Seung-Tak Ryu |
A 65 nm CMOS 7b 2 GS/s 20.7 mW Flash ADC With Cascaded Latch Interpolation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 50(10), pp. 2319-2330, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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16 | Aibin Yan, Huaguo Liang, Zhengfeng Huang, Cuiyun Jiang, Maoxiang Yi |
A Self-Recoverable, Frequency-Aware and Cost-Effective Robust Latch Design for Nanoscale CMOS Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 98-C(12), pp. 1171-1178, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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16 | Ramin Rajaei, Mahmoud Tabandeh, Mahdi Fazeli |
Single Event Multiple Upset (SEMU) Tolerant Latch Designs in Presence of Process and Temperature Variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 24(1), pp. 1550007:1-1550007:30, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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16 | Zhengfeng Huang, Huaguo Liang, Sybille Hellebrand |
A High Performance SEU Tolerant Latch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 31(4), pp. 349-359, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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16 | Yuanqing Li, Haibin Wang, Suying Yao, Xi Yan, Zhiyuan Gao, Jiangtao Xu |
Double Node Upsets Hardened Latch Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 31(5-6), pp. 537-548, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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16 | Gil Levi, Tal Hassner |
LATCH: Learned Arrangements of Three Patch Codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1501.03719, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP BibTeX RDF |
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16 | Qi Jiang, Huihui Yuan, Yang Wang, Xiangliang Jin |
Design and analyze of transient-induced latch-up in RS485 transceiver with on-chip TVS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 55(3-4), pp. 637-644, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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16 | Chunhua Qi, Liyi Xiao, Jing Guo 0004, Tianqi Wang |
Low cost and highly reliable radiation hardened latch design in 65 nm CMOS technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 55(6), pp. 863-872, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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16 | Yonghong Tao, Andreas Hierlemann, Yong Lian 0001 |
A Frequency-Domain Analysis of Latch Comparator Offset due to Load Capacitor Mismatch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 62-II(6), pp. 527-532, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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16 | Byungkyu Song, Taehui Na, Jisu Kim, Jung Pill Kim, Seung-Hyuk Kang, Seong-Ook Jung |
Latch Offset Cancellation Sense Amplifier for Deep Submicrometer STT-RAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(7), pp. 1776-1784, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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16 | Nikolaos Eftaxiopoulos, Nicholas Axelos, Georgios Zervakis 0001, Kostas Tsoumanis, Kiamal Z. Pekmestzi |
Delta DICE: A Double Node Upset resilient latch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MWSCAS ![In: IEEE 58th International Midwest Symposium on Circuits and Systems, MWSCAS 2015, Fort Collins, CO, USA, August 2-5, 2015, pp. 1-4, 2015, IEEE, 978-1-4673-6558-1. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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16 | Nikolaos Eftaxiopoulos, Nicholas Axelos, Kiamal Z. Pekmestzi |
DONUT: A Double Node Upset Tolerant Latch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2015 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2015, Montpellier, France, July 8-10, 2015, pp. 509-514, 2015, IEEE Computer Society, 978-1-4799-8719-1. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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16 | Anush Bekal, Rohit Joshi, Manish Goswami, Babu R. Singh, Ashok Srivatsava |
An Improved Dynamic Latch Based Comparator for 8-Bit Asynchronous SAR ADC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2015 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2015, Montpellier, France, July 8-10, 2015, pp. 178-182, 2015, IEEE Computer Society, 978-1-4799-8719-1. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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16 | Taiki Uemura, Takashi Kato, Hideya Matsuyama, Masanori Hashimoto |
Soft error immune latch design for 20 nm bulk CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IRPS ![In: IEEE International Reliability Physics Symposium, IRPS 2015, Monterey, CA, USA, April 19-23, 2015, pp. 4, 2015, IEEE, 978-1-4673-7362-3. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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16 | Tingting Pang, Wang Kang 0001, Yi Ran, Youguang Zhang, Weifeng Lv, Weisheng Zhao |
Nonvolatile radiation hardened DICE latch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NVMTS ![In: 15th Non-Volatile Memory Technology Symposium, NVMTS 2015, Beijing, China, October 12-14, 2015, pp. 1-4, 2015, IEEE, 978-1-5090-2126-0. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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16 | Bilal Habib, Jens-Peter Kaps, Kris Gaj |
Efficient SR-Latch PUF. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARC ![In: Applied Reconfigurable Computing - 11th International Symposium, ARC 2015, Bochum, Germany, April 13-17, 2015, Proceedings, pp. 205-216, 2015, Springer, 978-3-319-16213-3. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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16 | Katerina Katsarou, Yiorgos Tsiatouhas |
Soft error immune latch under SEU related double-node charge collection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 21st IEEE International On-Line Testing Symposium, IOLTS 2015, Halkidiki, Greece, July 6-8, 2015, pp. 46-49, 2015, IEEE, 978-1-4673-7905-2. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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16 | Tse-Ching Wu, Chien-Ju Chen, Yin-Nien Chen, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang |
Evaluation of energy-efficient latch circuits with hybrid tunneling FET and FinFET devices for ultra-low-voltage applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: 28th IEEE International System-on-Chip Conference, SOCC 2015, Beijing, China, September 8-11, 2015, pp. 339-344, 2015, IEEE, 978-1-4673-9094-1. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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16 | Abdel Martinez Alonso, Masaya Miyahara, Akira Matsuzawa |
A novel direct digital frequency synthesizer employing complementary dual-phase latch-based architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASICON ![In: 2015 IEEE 11th International Conference on ASIC, ASICON 2015, Chengdu, China, November 3-6, 2015, pp. 1-4, 2015, IEEE, 978-1-4799-8483-1. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
16 | Saki Tajima, Youhua Shi, Nozomu Togawa, Masao Yanagisawa |
A low-power soft error tolerant latch scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASICON ![In: 2015 IEEE 11th International Conference on ASIC, ASICON 2015, Chengdu, China, November 3-6, 2015, pp. 1-4, 2015, IEEE, 978-1-4799-8483-1. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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16 | Arvind Kumar Sharma, Yogendra Sharma, Sudeb Dasgupta, Bulusu Anand |
Efficient static D-latch standard cell characterization using a novel setup time model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: Sixteenth International Symposium on Quality Electronic Design, ISQED 2015, Santa Clara, CA, USA, March 2-4, 2015, pp. 371-378, 2015, IEEE, 978-1-4799-7581-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
16 | Jae-Won Jang, Swaroop Ghosh |
Design and analysis of novel SRAM PUFs with embedded latch for robustness. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: Sixteenth International Symposium on Quality Electronic Design, ISQED 2015, Santa Clara, CA, USA, March 2-4, 2015, pp. 298-302, 2015, IEEE, 978-1-4799-7581-5. The full citation details ...](Pics/full.jpeg) |
2015 |
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