| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Yu-Ming Yang, Iris Hui-Ru Jiang, Sung-Ting Ho |
PushPull: short path padding for timing error resilient circuits.  |
ISPD  |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Rimon Ikeno, Takashi Maruyama, Satoshi Komatsu, Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada |
A structured routing architecture and its design methodology suitable for high-throughput electron beam direct writing with character projection. |
ISPD |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Hamid Shojaei, Azadeh Davoodi, Jeffrey T. Linderoth |
Planning for local net congestion in global routing. |
ISPD |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Wen-Hao Liu, Cheng-Kok Koh, Yih-Lang Li |
Case study for placement solutions in ispd11 and dac12 routability-driven placement contests. |
ISPD |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Shao-Yun Fang, Chung-Wei Lin, Guang-Wan Liao, Yao-Wen Chang |
Simultaneous OPC- and CMP-aware routing based on accurate closed-form modeling. |
ISPD |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Logan M. Rakai, Amin Farshidi, Laleh Behjat, David T. Westwick |
Buffer sizing for clock networks using robust geometric programming considering variations in buffer sizes. |
ISPD |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Hung-Ming Chen |
On the way to practical tools for beyond die codesign and integration. |
ISPD |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Narayan Srinivasa |
A compiler for scalable placement and routing of brain-like architectures. |
ISPD |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Kan Wang, Huaxi Wang, Sheqin Dong |
Escape routing of mixed-pattern signals based on staggered-pin-array PCBs. |
ISPD |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Florentin Dartu, Qiuyang Wu |
To do or not to do hierarchical timing? |
ISPD |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Cheng-Kok Koh, Cliff C. N. Sze (eds.) |
International Symposium on Physical Design, ISPD'13, Stateline, NV, USA, March 24-27, 2013 |
ISPD |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Shyam Ramji |
Challenges in managing timing and wiring contracts during hierarchical floorplanning and design closure. |
ISPD |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Jordi Cortadella, Javier de San Pedro, Nikita Nikitin, Jordi Petit |
Physical-aware system-level design for tiled hierarchical chip multiprocessors. |
ISPD |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Chang-Cheng Tsai, Yiyu Shi 0001, Guojie Luo, Iris Hui-Ru Jiang |
FF-bond: multi-bit flip-flop bonding at placement. |
ISPD |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Yang Song, Hao Yu 0001, Sai Manoj Pudukotai Dinakarrao, Guoyong Shi |
SRAM dynamic stability verification by reachability analysis with consideration of threshold voltage variation. |
ISPD |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Robert Fischbach, Johann Knechtel, Jens Lienig |
Utilizing 2D and 3D rectilinear blocks for efficient IP reuse and floorplanning of 3D-integrated systems. |
ISPD |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Liam Madden |
Heterogeneous 3-d stacking, can we have the best of both (technology) worlds? |
ISPD |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Ruchir Puri |
Opportunities and challenges for high performance microprocessor designs and design automation. |
ISPD |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Cliff C. N. Sze, Laleh Behjat, Nikhil Jayakumar, Atul Walimbe, Gregory Ford, Mark Zwolinski, Harish Dangat, Giriraj Kakol |
ISPD 2013 expert designer/user session (eds). |
ISPD |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Vidyamani Parkhe |
Variability aware hierarchical implementation of big chips. |
ISPD |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiang Qiu, Malgorzata Marek-Sadowska, Wojciech Maly |
Designing VeSFET-based ICs with CMOS-oriented EDA infrastructure. |
ISPD |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Yoji Kajitani |
Coding the objects in place and route CAD. |
ISPD |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Jianchang Ao, Sheqin Dong, Song Chen 0001, Satoshi Goto |
Delay-driven layer assignment in global routing under multi-tier interconnect structure. |
ISPD |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Li-C. Wang |
Data mining in design and test processes: basic principles and promises. |
ISPD |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Muhammet Mustafa Ozdal, Chirayu Amin, Andrey Ayupov, Steven M. Burns, Gustavo R. Wilke, Cheng Zhuo |
The ISPD-2012 discrete cell sizing contest and benchmark suite. |
ISPD |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Janet L. Olson |
Synthesis for advanced nodes: an industry perspective. |
ISPD |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Myung-Chul Kim, Natarajan Viswanathan, Charles J. Alpert, Igor L. Markov, Shyam Ramji |
MAPLE: multilevel adaptive placement for mixed-size designs. |
ISPD |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Kwang-Ting (Tim) Cheng, Dmitri B. Strukov |
3D CMOS-memristor hybrid circuits: devices, integration, architecture, and applications. |
ISPD |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Cheng-Wu Lin, Cheng-Chung Lu, Jai-Ming Lin, Soon-Jyh Chang |
Routability-driven placement algorithm for analog integrated circuits. |
ISPD |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Kalliopi Tsota, Cheng-Kok Koh, Venkataramanan Balakrishnan |
A size scaling approach for mixed-size placement. |
ISPD |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Zigang Xiao, Yuelin Du, Hongbo Zhang 0001, Martin D. F. Wong |
A polynomial time exact algorithm for self-aligned double patterning layout decomposition. |
ISPD |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Burn J. Lin |
Lithography till the end of Moore's law. |
ISPD |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Wen-Hao Liu, Yih-Lang Li |
Optimizing the antenna area and separators in layer assignment of multi-layer global routing. |
ISPD |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Fang Gong, Sina Basir-Kazeruni, Lara Dolecek, Lei He 0001 |
A fast estimation of SRAM failure rate using probability collectives. |
ISPD |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Patrick Groeneveld |
Reality-driven physical synthesis. |
ISPD |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Bing Shi, Ankur Srivastava 0001 |
TSV-constrained micro-channel infrastructure design for cooling stacked 3D-ICs. |
ISPD |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Ming-Chao Lee, Yiyu Shi 0001, Yu-Guang Chen, Diana Marculescu, Shih-Chieh Chang |
Efficient on-line module-level wake-up scheduling for high performance multi-module designs. |
ISPD |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Shao-Yun Fang, Wei-Yu Chen, Yao-Wen Chang |
Graph-based subfield scheduling for electron-beam photomask fabrication. |
ISPD |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Samuel I. Ward, Myung-Chul Kim, Natarajan Viswanathan, Zhuo Li 0001, Charles J. Alpert, Earl E. Swartzlander Jr., David Z. Pan |
Keep it straight: teaching placement how to better handle designs with datapaths. |
ISPD |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Jhih-Rong Gao, David Z. Pan |
Flexible self-aligned double patterning aware detailed routing with prescribed layout planning. |
ISPD |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrew B. Kahng, Seokhyeong Kang |
Construction of realistic gate sizing benchmarks with known optimal solutions. |
ISPD |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Gregory Shklover, Ben Emanuel |
Simultaneous clock and data gate sizing algorithm with common global objective. |
ISPD |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Chih-Long Chang, Iris Hui-Ru Jiang, Yu-Ming Yang, Evan Y.-W. Tsai, Aki S.-H. Chen |
Novel pulsed-latch replacement based on time borrowing and spiral clustering. |
ISPD |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Jackey Z. Yan, Chris Chu |
Optimal slack-driven block shaping algorithm in fixed-outline floorplanning. |
ISPD |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Tsung-Wei Huang, Jia-Wen Chang, Tsung-Yi Ho |
Integrated fluidic-chip co-design methodology for digital microfluidic biochips. |
ISPD |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Shuai Li, Cheng-Kok Koh |
Mixed integer programming models for detailed placement. |
ISPD |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Shayak Banerjee, Kanak B. Agarwal, Sani R. Nassif |
Design-aware lithography. |
ISPD |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Yeh-Chi Chang, Chun-Kai Wang, Hung-Ming Chen |
On construction low power and robust clock tree via slew budgeting. |
ISPD |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Venky Ramachandran |
Construction of minimal functional skew clock trees. |
ISPD |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Tong Gao, Prashant Saxena |
On pioneering nanometer-era routing problems. |
ISPD |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Renshen Wang, Nimish Shah |
Scalable hierarchical floorplanning for fast physical prototyping of systems-on-chip. |
ISPD |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Jiang Hu, Cheng-Kok Koh (eds.) |
International Symposium on Physical Design, ISPD'12, Napa, CA, USA, March 25-28, 2012 |
ISPD |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Jason Cong, Bin Liu 0006, Guojie Luo, Raghu Prabhakar |
Towards layout-friendly high-level synthesis. |
ISPD |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Alexander Korobkov |
Power-grid (PG) analysis challenges for large microprocessor designs: (our experience with oracle sparc processor designs). |
ISPD |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | C. L. Liu 0001 |
I attended the nineteenth design automation conference. |
ISPD |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Chung-Kuan Cheng, Peng Du, Andrew B. Kahng, Shih-Hung Weng |
Low-power gated bus synthesis for 3d ic via rectilinear shortest-path steiner graph. |
ISPD |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Martin D. F. Wong |
On simulated annealing in EDA. |
ISPD |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Jason Cong |
Transformation from ad hoc EDA to algorithmic EDA. |
ISPD |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Chung-Kuan Cheng |
Placement and beyond in honor of Ernest S. Kuh. |
ISPD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Wojciech Maly |
Vertical slit transistor based integrated circuits (veSTICs): feasibility study. |
ISPD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Chung-Kuan Cheng, Peng Du, Andrew B. Kahng, Grantham K. H. Pang, Yuanzhe Wang, Ngai Wong |
More realistic power grid verification based on hierarchical current and power constraints. |
ISPD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Samuel I. Ward, David A. Papa, Zhuo Li 0001, Cliff N. Sze, Charles J. Alpert, Earl E. Swartzlander Jr. |
Quantifying academic placer performance on custom designs. |
ISPD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Yao-Wen Chang, Jiang Hu (eds.) |
Proceedings of the 2011 International Symposium on Physical Design, ISPD 2011, Santa Barbara, California, USA, March 27-30, 2011 |
ISPD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Johann Knechtel, Igor L. Markov, Jens Lienig |
Assembling 2D blocks into 3D chips. |
ISPD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Vivek Singh |
Litho and design: moore close than ever. |
ISPD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Tsung-Hsien Lee, Yen-Jung Chang, Ting-Chi Wang |
An enhanced global router with consideration of general layer directives. |
ISPD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Yang Zhao 0001, Krishnendu Chakrabarty |
Co-optimization of droplet routing and pin assignment in disposable digital microfluidic biochips. |
ISPD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Yi-Le Huang, Jiang Hu, Weiping Shi |
Lagrangian relaxation for gate implementation selection. |
ISPD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Robert Patti |
Advances in 3D integrated circuits. |
ISPD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Fang Gong, Hao Yu 0001, Lei He 0001 |
Stochastic analog circuit behavior modeling by point estimation method. |
ISPD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Kun Yuan, David Z. Pan |
E-beam lithography stencil planning and optimization with overlapped characters. |
ISPD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Shao-Huan Wang, Yu-Yi Liang, Tien-Yu Kuo, Wai-Kei Mak |
Power-driven flip-flop merging and relocation. |
ISPD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Xi Chen, Jiang Hu, Ning Xu 0006 |
Regularity-constrained floorplanning for multi-core processors. |
ISPD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Tarun Mittal, Cheng-Kok Koh |
Cross link insertion for improving tolerance to variations in clock network synthesis. |
ISPD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Natarajan Viswanathan, Charles J. Alpert, Cliff C. N. Sze, Zhuo Li 0001, Gi-Joon Nam, Jarrod A. Roy |
The ISPD-2011 routability-driven placement contest and benchmark suite. |
ISPD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Tanay Karnik, Dinesh Somasekhar, Shekhar Borkar |
3DICs for tera-scale computing: a case study. |
ISPD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Jianchao Lu, Xiaomi Mao, Baris Taskin |
Timing slack aware incremental register placement with non-uniform grid generation for clock mesh synthesis. |
ISPD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Shashank Bujimalla, Cheng-Kok Koh |
Synthesis of low power clock trees for handling power-supply variations. |
ISPD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Ren-Song Tsay |
From academic ideas to practical physical design tools. |
ISPD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Massoud Pedram |
Robust design of power-efficient VLSI circuits. |
ISPD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Alexander Volkov |
Impact of manufacturing on routing methodology at 32/22 nm. |
ISPD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Jin-Tai Yan, Zhi-Wei Chen |
Obstacle-aware length-matching bus routing. |
ISPD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Iris Hui-Ru Jiang, Chih-Long Chang, Yu-Ming Yang, Evan Y.-W. Tsai, Lancer S.-F. Chen |
INTEGRA: fast multi-bit flip-flop clustering for clock power saving based on interval graphs. |
ISPD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Ernest S. Kuh |
Professor Ernest Kuh's talk. |
ISPD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Yanheng Zhang, Chris Chu |
RegularRoute: an efficient detailed router with regular routing patterns. |
ISPD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Malgorzata Marek-Sadowska |
On old and new routing problems. |
ISPD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Haitong Tian, Wai-Chung Tang, Evangeline F. Y. Young, Cliff C. N. Sze |
Grid-to-ports clock routing for high performance microprocessor designs. |
ISPD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Dongjin Lee, Igor L. Markov |
Obstacle-aware clock-tree shaping during placement. |
ISPD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Tung-Chieh Chen |
Automated placement for custom digital designs. |
ISPD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Jackey Z. Yan, Chris Chu, Wai-Kei Mak |
SafeChoice: a novel clustering algorithm for wirelength-driven placement. |
ISPD |
2010 |
DBLP DOI BibTeX RDF |
vlsi placement, physical design, hypergraph clustering |
| 1 | Jin Hu, Jarrod A. Roy, Igor L. Markov |
Completing high-quality global routes. |
ISPD |
2010 |
DBLP DOI BibTeX RDF |
global routing |
| 1 | Tsung-Wei Huang, Tsung-Yi Ho |
A two-stage ILP-based droplet routing algorithm for pin-constrained digital microfluidic biochips. |
ISPD |
2010 |
DBLP DOI BibTeX RDF |
routing, ilp, microfluidic, biochip |
| 1 | Yaoguang Wei, Sachin S. Sapatnekar |
Dummy fill optimization for enhanced manufacturability. |
ISPD |
2010 |
DBLP DOI BibTeX RDF |
routing, design for manufacturability, chemical-mechanical polishing, dummy fill |
| 1 | Hua Xiang 0001, Haoxing Ren, Louise Trevillyan, Lakshmi N. Reddy, Ruchir Puri, Minsik Cho |
Logical and physical restructuring of fan-in trees. |
ISPD |
2010 |
DBLP DOI BibTeX RDF |
symmetric-function fan-in tree, restructure, commutative |
| 1 | Yue Xu, Chris Chu |
A matching based decomposer for double patterning lithography. |
ISPD |
2010 |
DBLP DOI BibTeX RDF |
doubel patterning lithography, planar graph, matching algorithm |
| 1 | Huang-Yu Chen, Szu-Jui Chou, Yao-Wen Chang |
Density gradient minimization with coupling-constrained dummy fill for CMP control. |
ISPD |
2010 |
DBLP DOI BibTeX RDF |
density gradient, manufacturability, chemical-mechanical polishing, dummy fill |
| 1 | Michael Eick, Martin Strasser, Helmut E. Graeb, Ulf Schlichtmann |
Automatic generation of hierarchical placement rules for analog integrated circuits. |
ISPD |
2010 |
DBLP DOI BibTeX RDF |
hierarchical placement rules, constraints, placement, analog integrated circuits |
| 1 | Venkata Rajesh Mekala, Yifang Liu, Xiaoji Ye, Jiang Hu, Peng Li 0001 |
Accurate clock mesh sizing via sequential quadraticprogramming. |
ISPD |
2010 |
DBLP DOI BibTeX RDF |
optimization, sequential quadratic programming |
| 1 | Yufu Zhang, Bing Shi, Ankur Srivastava 0001 |
A statistical framework for designing on-chip thermal sensing infrastructure in nano-scale systems. |
ISPD |
2010 |
DBLP DOI BibTeX RDF |
estimation, statistical, temperature, sensor placement |
| 1 | Ashutosh Chakraborty, David Z. Pan |
Skew management of NBTI impacted gated clock trees. |
ISPD |
2010 |
DBLP DOI BibTeX RDF |
clock skew, clock gating, NBTI |
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