Search results for "NoC"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
21	Jingcao Hu, Radu Marculescu	Energy- and performance-aware mapping for regular NoC architectures.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
21	Holger Blume, Thorsten von Sydow, Daniel Becker 0001, Tobias G. Noll	Modeling NoC Architectures by Means of Deterministic and Stochastic Petri Nets.	SAMOS	2005	DBLP DOI BibTeX RDF
21	Yves Vanderperren, Wim Dehaene	UML 2 and SysML: An Approach to Deal with Complexity in SoC/NoC Design.	DATE	2005	DBLP DOI BibTeX RDF
21	Partha Pratim Pande, Cristian Grecu, Michael Jones, André Ivanov, Res Saleh	Effect of traffic localization on energy dissipation in NoC-based interconnect.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
21	Arkadiy Morgenshtein, Israel Cidon, Ran Ginosar, Avinoam Kolodny	Low-leakage repeaters for NoC interconnects.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
21	Daniel Andreasson, Shashi Kumar	Slack-time aware routing in NoC systems.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
21	Praveen Bhojwani, Rabi N. Mahapatra, Eun Jung Kim 0001, Thomas Chen	A Heuristic for Peak Power Constrained Design of Network-on-Chip (NoC) Based Multimode Systems.	VLSI Design	2005	DBLP DOI BibTeX RDF
21	Ashok Narasimhan, Shantanu Divekar, Praveen Elakkumanan, Ramalingam Sridhar	A Low-Power Current-Mode Clock Distribution Scheme for Multi-GHz NoC-Based SoCs.	VLSI Design	2005	DBLP DOI BibTeX RDF
21	Jongman Kim, Dongkook Park, Chrysostomos Nicopoulos, Narayanan Vijaykrishnan, Chita R. Das	Design and analysis of an NoC architecture from performance, reliability and energy perspective.	ANCS	2005	DBLP DOI BibTeX RDF	reliability, networks-on-chip, adaptive routing
21	Chan-Eun Rhee, Han-You Jeong, Soonhoi Ha	Many-to-Many Core-Switch Mapping in 2-D Mesh NoC Architectures.	ICCD	2004	DBLP DOI BibTeX RDF
21	Jingcao Hu, Radu Marculescu	Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures.	DATE	2003	DBLP DOI BibTeX RDF
17	Young-Jin Yoon, Nicola Concer, Michele Petracca, Luca P. Carloni	Virtual channels vs. multiple physical networks: a comparative analysis.	DAC	2010	DBLP DOI BibTeX RDF	channel slicing, network-on-chip, virtual channel
17	Marcus Vinícius Carvalho da Silva, Nadia Nedjah, Luiza de Macedo Mourelle	Application Synthesis for MPSoCs Implementation Using Multiobjective Optimization.	IWANN (1)	2009	DBLP DOI BibTeX RDF
17	Reetuparna Das, Onur Mutlu, Thomas Moscibroda, Chita R. Das	Application-aware prioritization mechanisms for on-chip networks.	MICRO	2009	DBLP DOI BibTeX RDF	multi-core, packet scheduling, memory systems, arbitration, prioritization, on-chip networks
17	Taehoon Kim, Sungwoo Tak	A real-time hardware-software codesign technique of network protocols to provide QoS.	ICHIT	2009	DBLP DOI BibTeX RDF	QoS communications architecture, real-time scheduling, network protocols, hardware-software codesign
17	Yi Xu, Yu Du, Bo Zhao 0007, Xiuyi Zhou, Youtao Zhang, Jun Yang 0002	A low-radix and low-diameter 3D interconnection network design.	HPCA	2009	DBLP DOI BibTeX RDF
17	Björn Osterloh, Harald Michalik, Björn Fiethe	SoCWire: A Robust and Fault Tolerant Network-on-Chip Approach for a Dynamic Reconfigurable System-on-Chip in FPGAs.	ARCS	2009	DBLP DOI BibTeX RDF	SoCWire, dynamic reconfigurable system, Sytem-on-Chip, Network-on-Chip, SRAM-based FPGA, VMC
17	Marcelo Daniel Berejuck, César Albenes Zeferino	Adding mechanisms for QoS to a network-on-chip.	SBCCI	2009	DBLP DOI BibTeX RDF	FPGA, systems-on-chip, networks-on-chip
17	Fahime Moein-darbari, Ahmad Khademzadeh, Golnar Gharooni-fard	Evaluating the Performance of a Chaos Genetic Algorithm for Solving the Network on Chip Mapping Problem.	CSE (2)	2009	DBLP DOI BibTeX RDF
17	Dietmar Tutsch, Miroslaw Malek	Comparison of network-on-chip topologies for multicore systems considering multicast and local traffic.	SimuTools	2009	DBLP DOI BibTeX RDF	simulation, performance, multicast, network-on-chip, multicore processor
17	Tom van den Broek, Julien Schmaltz	Towards a formally verified network-on-chip.	FMCAD	2009	DBLP DOI BibTeX RDF
17	Daniel U. Becker, William J. Dally	Allocator implementations for network-on-chip routers.	SC	2009	DBLP DOI BibTeX RDF
17	David Fick, Andrew DeOrio, Jin Hu, Valeria Bertacco, David T. Blaauw, Dennis Sylvester	Vicis: a reliable network for unreliable silicon.	DAC	2009	DBLP DOI BibTeX RDF	hard faults, fault tolerance, built-in-self-test, Network-on-Chip, reconfiguration, torus, N-modular redundancy
17	Zhonghai Lu, Axel Jantsch	TDM Virtual-Circuit Configuration for Network-on-Chip.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
17	Anthony Leroy, Dragomir Milojevic, Diederik Verkest, Frédéric Robert, Francky Catthoor	Concepts and Implementation of Spatial Division Multiplexing for Guaranteed Throughput in Networks-on-Chip.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF
17	Assaf Shacham, Keren Bergman, Luca P. Carloni	Photonic Networks-on-Chip for Future Generations of Chip Multiprocessors.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF
17	Chen-Ling Chou, Ümit Y. Ogras, Radu Marculescu	Energy- and Performance-Aware Incremental Mapping for Networks on Chip With Multiple Voltage Levels.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
17	Randeep Bhatia, Nicole Immorlica, Tracy Kimbrel, Vahab S. Mirrokni, Joseph Naor, Baruch Schieber	Traffic Engineering of Management Flows by Link Augmentations on Confluent Trees.	Theory Comput. Syst.	2008	DBLP DOI BibTeX RDF	Confluent flows, Management flows, Dynamic programming, Combinatorial optimization, Network management, Traffic engineering
17	Kuei-Chung Chang, Jih-Sheng Shen, Tien-Fu Chen	Tailoring circuit-switched network-on-chip to application-specific system-on-chip by two optimization schemes.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	low power, systems on chips, networks on chip, interconnection, Application specific
17	Yatin Vasant Hoskote, Radu Marculescu, Li-Shiuan Peh	Guest Editors' Introduction: Tackling Key Problems in NoCs.	IEEE Des. Test Comput.	2008	DBLP DOI BibTeX RDF
17	Po-Tsang Huang, Wei-Li Fang, Yin-Ling Wang, Wei Hwang	Low Power and Reliable Interconnection with Self-Corrected Green Coding Scheme for Network-on-Chip.	NOCS	2008	DBLP DOI BibTeX RDF	interconnnection, reliability, low power, network-on-chip
17	Min Zhang 0012, Chiu-sing Choy	Low-Cost VC Allocator Design for Virtual Channel Wormhole Routers in Networks-on-Chip.	NOCS	2008	DBLP DOI BibTeX RDF
17	Mikkel Bystrup Stensgaard, Jens Sparsø	ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology.	NOCS	2008	DBLP DOI BibTeX RDF	Communication, System-on-Chip, Network-on-Chip, Reconfigurable, Application-specific
17	Andreas Hansson 0001, Maarten Wiggers, Arno Moonen, Kees Goossens, Marco Bekooij	Applying Dataflow Analysis to Dimension Buffers for Guaranteed Performance in Networks on Chip.	NOCS	2008	DBLP DOI BibTeX RDF	Cyclo-Static Dataflow, System on Chip, Network on Chip, Real-Time Performance
17	Bin Li 0018, Li-Shiuan Peh, Priyadarsan Patra	Impact of Process and Temperature Variations on Network-on-Chip Design Exploration.	NOCS	2008	DBLP DOI BibTeX RDF
17	Antonio Deledda, Claudio Mucci, Arseni Vitkovski, Philippe Bonnot 0001, Arnaud Grasset, Philippe Millet, Matthias Kühnle, Florian Ries, Michael Hübner 0001, Jürgen Becker 0001, Massimo Coppola, Lorenzo Pieralisi, Riccardo Locatelli, Giuseppe Maruccia, Fabio Campi, Tommaso DeMarco	Design of a HW/SW Communication Infrastructure for a Heterogeneous Reconfigurable Processor.	DATE	2008	DBLP DOI BibTeX RDF
17	Mohammad Hosseinabady, Mohammad Reza Kakoee, Jimson Mathew, Dhiraj K. Pradhan	De Bruijn Graph as a Low Latency Scalable Architecture for Energy Efficient Massive NoCs.	DATE	2008	DBLP DOI BibTeX RDF
17	Mohammad Abdullah Al Faruque, Jörg Henkel	Minimizing Virtual Channel Buffer for Routers in On-chip Communication Architectures.	DATE	2008	DBLP DOI BibTeX RDF
17	Feng Yuan, Lin Huang 0002, Qiang Xu 0001	Re-Examining the Use of Network-on-Chip as Test Access Mechanism.	DATE	2008	DBLP DOI BibTeX RDF
17	Samuel Rodrigo, José Flich, José Duato, Mark Hummel	Efficient unicast and multicast support for CMPs.	MICRO	2008	DBLP DOI BibTeX RDF
17	Shan Yan, Bill Lin 0001	Application-specific Network-on-Chip architecture synthesis based on set partitions and Steiner Trees.	ASP-DAC	2008	DBLP DOI BibTeX RDF
17	Nader Bagherzadeh, Masaru Matsuura	Performance Impact of Task-to-Task Communication Protocol in Network-on-Chip.	ITNG	2008	DBLP DOI BibTeX RDF	System-on-Chip, Network-on Chip, communication protocol
17	Mohammad Sadegh Talebi, Fahimeh Jafari, Ahmad Khonsari, Mohammad Hossien Yaghmaee	Proportionally-fair best effort flow control in network-on-chip architectures.	IPDPS	2008	DBLP DOI BibTeX RDF
17	Huaxi Gu, Jiang Xu 0001, Zheng Wang	ODOR: a microresonator-based high-performance low-cost router for optical networks-on-Chip.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	microresonator, low power, network on chip, optical interconnect, router architecture, loss
17	Sanna Määttä, Leandro Soares Indrusiak, Luciano Ost, Leandro Möller, Jari Nurmi, Manfred Glesner, Fernando Moraes 0001	Validation of executable application models mapped onto network-on-chip platforms.	SIES	2008	DBLP DOI BibTeX RDF
17	Christian Paukovits, Hermann Kopetz	Concepts of Switching in the Time-Triggered Network-on-Chip.	RTCSA	2008	DBLP DOI BibTeX RDF
17	Igor Loi, Subhasish Mitra, Thomas H. Lee, Shinobu Fujita, Luca Benini	A low-overhead fault tolerance scheme for TSV-based 3D network on chip links.	ICCAD	2008	DBLP DOI BibTeX RDF
17	Jason Cong, Karthik Gururaj, Guoling Han, Adam Kaplan, Mishali Naik, Glenn Reinman	MC-Sim: an efficient simulation tool for MPSoC designs.	ICCAD	2008	DBLP DOI BibTeX RDF
17	Fahimeh Jafari, Mohammad Hossien Yaghmaee, Mohammad Sadegh Talebi, Ahmad Khonsari	Max-Min-Fair Best Effort Flow Control in Network-on-Chip Architectures.	ICCS (1)	2008	DBLP DOI BibTeX RDF	Network-on-Chip, flow control, Max-Min fairness
17	Ahmad Khonsari, Mohammad R. Aghajani, Arash Tavakkol, Mohammad Sadegh Talebi	Mathematical analysis of buffer sizing for Network-on-Chips under multimedia traffic.	ICCD	2008	DBLP DOI BibTeX RDF
17	Reza Sabbaghi-Nadooshan, Mehdi Modarressi, Hamid Sarbazi-Azad	The 2D DBM: An attractive alternative to the simple 2D mesh topology for on-chip networks.	ICCD	2008	DBLP DOI BibTeX RDF
17	Amir Hosseini, Tamer Ragheb, Yehia Massoud	A fault-aware dynamic routing algorithm for on-chip networks.	ISCAS	2008	DBLP DOI BibTeX RDF
17	Mingsong Lv, Ying Guo, Nan Guan, Qingxu Deng	RTNoC: A Simulation Tool for Real-Time Communication Scheduling on Networks-on-Chips.	CSSE (4)	2008	DBLP DOI BibTeX RDF
17	Slavisa Jovanovic, Camel Tanougast, Serge Weber	A new high-performance scalable dynamic interconnection for FPGA-based reconfigurable systems.	ASAP	2008	DBLP DOI BibTeX RDF
17	Abbas Eslami Kiasari, Shaahin Hessabi, Hamid Sarbazi-Azad	PERMAP: A performance-aware mapping for application-specific SoCs.	ASAP	2008	DBLP DOI BibTeX RDF
17	Alexander D. Rast, Shufan Yang, Muhammad Mukaram Khan, Stephen B. Furber	Virtual synaptic interconnect using an asynchronous network-on-chip.	IJCNN	2008	DBLP DOI BibTeX RDF
17	Mahmoud Moadeli, Alireza Shahrabi, Wim Vanderbauwhede, Mohamed Ould-Khaoua	Modeling Differentiated Services-Based QoS in Wormhole-Routed NoCs.	AINA	2008	DBLP DOI BibTeX RDF	Perfromance modelling, QoS, Network on Chip, Wormhole
17	Hans G. Kerkhoff, Jarkko J. M. Huijts	Testing of a Highly Reconfigurable Processor Core for Dependable Data Streaming Applications.	DELTA	2008	DBLP DOI BibTeX RDF	reconfigurable multi-processor-cores SoC, embedded system test, dependable SoCs, ATPG, Design-for-Test, self-repair
17	Fahimeh Jafari, Mohammad Sadegh Talebi, Ahmad Khonsari, Mohammad Hossien Yaghmaee	A Novel Congestion Control Scheme in Network-on-Chip Based on Best Effort Delay-Sum Optimization.	ISPAN	2008	DBLP DOI BibTeX RDF	Congestion control, Network-on-Chip, iterative algorithm
17	Antonio Pullini, Federico Angiolini, Srinivasan Murali, David Atienza, Giovanni De Micheli, Luca Benini	Bringing NoCs to 65 nm.	IEEE Micro	2007	DBLP DOI BibTeX RDF	network on chip, low-power design, power management, multicore architectures, on-chip interconnection networks, design aids, deep submicron design
17	Cristian Grecu, André Ivanov, Partha Pratim Pande, Axel Jantsch, Erno Salminen, Ümit Y. Ogras, Radu Marculescu	Towards Open Network-on-Chip Benchmarks.	NOCS	2007	DBLP DOI BibTeX RDF	performance evaluation, metrics, benchmarks, networks-on-chip
17	Jeffrey D. Hoffman, David Arditti Ilitzky, Anthony Chun, Aliaksei Chapyzhenka	Architecture of the Scalable Communications Core.	NOCS	2007	DBLP DOI BibTeX RDF
17	Brett Feero, Partha Pratim Pande	Performance Evaluation for Three-Dimensional Networks-On-Chip.	ISVLSI	2007	DBLP DOI BibTeX RDF
17	Jeffrey D. Hoffman, David Arditti Ilitzky, Anthony Chun, Aliaksei Chapyzhenka	Overview of the Scalable Communications Core.	ISVLSI	2007	DBLP DOI BibTeX RDF
17	Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny	Routing table minimization for irregular mesh NoCs.	DATE	2007	DBLP DOI BibTeX RDF
17	Kim Petersén, Johnny Öberg	Toward a scalable test methodology for 2D-mesh Network-on-Chips.	DATE	2007	DBLP DOI BibTeX RDF
17	Paolo Meloni, Giovanni Busonera, Salvatore Carta, Luigi Raffo	On the impact of serialization on the cache performances in Network-on-Chip based MPSoCs.	DSD	2007	DBLP DOI BibTeX RDF
17	Mohammad Reza Kakoee, Mohammad Hossein Neishaburi, Masoud Daneshtalab, Saeed Safari, Zainalabedin Navabi	On-Chip Verification of NoCs Using Assertion Processors.	DSD	2007	DBLP DOI BibTeX RDF
17	Timo Schönwald, Jochen Zimmermann, Oliver Bringmann 0001, Wolfgang Rosenstiel	Fully Adaptive Fault-Tolerant Routing Algorithm for Network-on-Chip Architectures.	DSD	2007	DBLP DOI BibTeX RDF
17	Sung-Tze Wu, Chih-Hao Chao, I-Chyn Wey, An-Yeu Wu	Dynamic Channel Flow Control of Networks-on-Chip Systems for High Buffer Efficiency.	SiPS	2007	DBLP DOI BibTeX RDF
17	Florian Thoma, Matthias Kühnle, Philippe Bonnot 0001, Elena Moscu Panainte, Koen Bertels, Sebastian Goller, Axel Schneider, Stéphane Guyetant, Eberhard Schüler, Klaus D. Müller-Glaser, Jürgen Becker 0001	MORPHEUS: Heterogeneous Reconfigurable Computing.	FPL	2007	DBLP DOI BibTeX RDF
17	Christian Schuck, Stefan Lamparth, Jürgen Becker 0001	artNoC - A Novel Multi-Functional Router Architecture for Organic Computing.	FPL	2007	DBLP DOI BibTeX RDF
17	Guoqiang Yang, Mei Yang, Yulu Yang, Yingtao Jiang	On the Physicl Layout of PRDT-Based NoCs.	ITNG	2007	DBLP DOI BibTeX RDF
17	Rabindra Ku Jena, Gopal Ku Sharma	A Multi-Objective Evolutionary Algorithm Based Optimization Model for Network-on-Chip Synthesis.	ITNG	2007	DBLP DOI BibTeX RDF
17	Pascal T. Wolkotte, Philip K. F. Hölzenspies, Gerard J. M. Smit	Using an FPGA for Fast Bit Accurate SoC Simulation.	IPDPS	2007	DBLP DOI BibTeX RDF
17	Andreas Hansson 0001, Martijn Coenen, Kees Goossens	Channel trees: reducing latency by sharing time slots in time-multiplexed networks on chip.	CODES+ISSS	2007	DBLP DOI BibTeX RDF	quality-of-service, system-on-chip, network-on-chip, time-division-multiplexing
17	Feihui Li, Guangyu Chen, Mahmut T. Kandemir, Ibrahim Kolcu	Profile-driven energy reduction in network-on-chips.	PLDI	2007	DBLP DOI BibTeX RDF	routing, compiler, Network-on-Chip, power
17	Reza Moraveji, Hamid Sarbazi-Azad, Maghsoud Abbaspour	Optimal Placement of Frequently Accessed IPs in Mesh NoCs.	Asia-Pacific Computer Systems Architecture Conference	2007	DBLP DOI BibTeX RDF	Latency model, IPs/Cores mapping, System on chip, Network on chip, Mesh, Power model
17	César A. M. Marcon, Edson I. Moreno, Ney Laert Vilar Calazans, Fernando Gehm Moraes	Evaluation of Algorithms for Low Energy Mapping onto NoCs.	ISCAS	2007	DBLP DOI BibTeX RDF
17	Baojun Qiao, Feng Shi 0009, Weixing Ji	THIN: A New Hierarchical Interconnection Network-on-Chip for SOC.	ICA3PP	2007	DBLP DOI BibTeX RDF	multicast, System-on-Chip, Network-on-Chip, network topology
17	Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda	Safety Evaluation of NanoFabrics.	DFT	2007	DBLP DOI BibTeX RDF
17	Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano	Tightly-Coupled Multi-Layer Topologies for 3-D NoCs.	ICPP	2007	DBLP DOI BibTeX RDF
17	Ümit Y. Ogras, Radu Marculescu, Puru Choudhary, Diana Marculescu	Voltage-Frequency Island Partitioning for GALS-based Networks-on-Chip.	DAC	2007	DBLP DOI BibTeX RDF
17	Erno Salminen, Tero Kangas, Timo D. Hämäläinen, Jouni Riihimäki, Vesa Lahtinen, Kimmo Kuusilinna	HIBI Communication Network for System-on-Chip.	J. VLSI Signal Process.	2006	DBLP DOI BibTeX RDF	hierarchical bus, system-on-chip, network-on-chip, wrapper
17	Dongkook Park, Chrysostomos Nicopoulos, Jongman Kim, Narayanan Vijaykrishnan, Chita R. Das	Exploring Fault-Tolerant Network-on-Chip Architectures.	DSN	2006	DBLP DOI BibTeX RDF
17	José Carlos S. Palma, Leandro Soares Indrusiak, Fernando Gehm Moraes, Alberto García Ortiz, Manfred Glesner, Ricardo A. L. Reis	Adaptive Coding in Networks-on-Chip: Transition Activity Reduction Versus Power Overhead of the Codec Circuitry.	PATMOS	2006	DBLP DOI BibTeX RDF
17	Ming Li, Wen-Ben Jone, Qing-An Zeng	An Efficient Wrapper Scan Chain Configuration Method for Network-on-Chip Testing.	ISVLSI	2006	DBLP DOI BibTeX RDF
17	José Carlos S. Palma, Ricardo A. L. Reis, Leandro Soares Indrusiak, Alberto García Ortiz, Manfred Glesner, Fernando Gehm Moraes	Evaluating the Impact of Data Encoding Techniques on the Power Consumption in Networks-on-Chip.	ISVLSI	2006	DBLP DOI BibTeX RDF
17	Hsin-Chou Chi, Chia-Ming Wu	An Efficient Scheduler for Circuit-Switched Network-on-Chip Architectures.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
17	Chunsheng Liu, Vikram Iyengar	Test scheduling with thermal optimization for network-on-chip systems using variable-rate on-chip clocking.	DATE	2006	DBLP DOI BibTeX RDF
17	Krishnan Srinivasan, Karam S. Chatha	A low complexity heuristic for design of custom network-on-chip architectures.	DATE	2006	DBLP DOI BibTeX RDF
17	Chrysostomos Nicopoulos, Dongkook Park, Jongman Kim, Narayanan Vijaykrishnan, Mazin S. Yousif, Chita R. Das	ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers.	MICRO	2006	DBLP DOI BibTeX RDF
17	Po-Tsang Huang, Wei Hwang	2-level FIFO architecture design for switch fabrics in network-on-chip.	ISCAS	2006	DBLP DOI BibTeX RDF
17	Cristian Grecu, Partha Pratim Pande, André Ivanov, Res Saleh	BIST for Network-on-Chip Interconnect Infrastructures.	VTS	2006	DBLP DOI BibTeX RDF	interconnect infrastructure, unicast test, multicast test, built-in self-test, network-on-chip
17	Ümit Y. Ogras, Radu Marculescu	Prediction-based flow control for network-on-chip traffic.	DAC	2006	DBLP DOI BibTeX RDF	congestion control, networks-on-chip, flow control, multi-processor systems
17	Srinivasan Murali, David Atienza, Luca Benini, Giovanni De Micheli	A multi-path routing strategy with guaranteed in-order packet delivery and fault-tolerance for networks on chip.	DAC	2006	DBLP DOI BibTeX RDF	re-order buffers, fault-tolerance, routing, systems on chip, networks on chip, flow control, multi-path
17	Rajesh K. Gupta 0001	On-chip networks.	IEEE Des. Test Comput.	2005	DBLP DOI BibTeX RDF	integration, SoCs, networks on chips, on-chip interconnects
17	César A. M. Marcon, José Carlos S. Palma, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Altamiro Amadeu Susin, Ricardo Augusto da Luz Reis	Modeling the Traffic Effect for the Application Cores Mapping Problem onto NoCs.	VLSI-SoC	2005	DBLP DOI BibTeX RDF
17	Philippe Martin 0005	Design of a Virtual Component Neutral Network-on-Chip Transaction Layer.	DATE	2005	DBLP DOI BibTeX RDF
17	Stergios Stergiou, Federico Angiolini, Salvatore Carta, Luigi Raffo, Davide Bertozzi, Giovanni De Micheli	xpipes Lite: A Synthesis Oriented Design Library For Networks on Chips.	DATE	2005	DBLP DOI BibTeX RDF