Search results for "RISC"

Hits ?▲	Authors	Title	Venue	Year	Link
13	William Fornaciari, Federico Reghenzani, Giovanni Agosta, Davide Zoni, Andrea Galimberti, Francesco Conti 0001, Yvan Tortorella, Emanuele Parisi, Francesco Barchi, Andrea Bartolini, Andrea Acquaviva, Daniele Gregori, Salvatore Cognetta, Carlo Ciancarelli, Antonio Leboffe, Paolo Serri, Alessio Burrello, Daniele Jahier Pagliari, Gianvito Urgese, Maurizio Martina, Guido Masera, Rosario Di Carlo, Antonio Sciarappa	RISC-V Processor Technologies for Aerospace Applications in the ISOLDE Project.	SAMOS	2023	DBLP DOI BibTeX RDF
13	Sven Gesper, Fabian Stuckmann, Lucy Wöbbekind, Guillermo Payá Vayá	PATARA: Extension of a Verification Framework for RISC-V Instruction Set Implementations.	SAMOS	2023	DBLP DOI BibTeX RDF
13	Malte Hawich, Nico Rumpeltin, Malte Rücker, Tobias Stuckenberg, Holger Blume	High Performance Instruction Fetch Structure within a RISC-V Processor for Use in Harsh Environments.	SAMOS	2023	DBLP DOI BibTeX RDF
13	Czea Sie Chuah, Christian Appold, Tim Leinmüller	Formal Verification of Security Properties on RISC-V Processors.	MEMOCODE	2023	DBLP BibTeX RDF
13	Fabrice Lozachmeur, Arnaud Tisserand	A RISC-V Instruction Set Extension for Flexible Hardware/Software Protection of Cryptosystems Masked at High Orders.	MWSCAS	2023	DBLP DOI BibTeX RDF
13	Yan He, Xiangning Chen	Survey and Comparison of Pipeline of Some RISC and CISC System Architectures.	ICCCS	2023	DBLP DOI BibTeX RDF
13	Tianchen He, Xiangning Chen, Guokang Wang	Research on Open Source Processor and Analysis of Current Development Dilemma Based on RISC-V.	ICCCS	2023	DBLP DOI BibTeX RDF
13	Qingguan Gao, Kaisheng Sun, Jiankuo Dong, Fangyu Zheng, Jingqiang Lin, Yongjun Ren, Zhe Liu 0001	V-Curve25519: Efficient Implementation of Curve25519 on RISC-V Architecture.	Inscrypt (2)	2023	DBLP DOI BibTeX RDF
13	Alessandro Nadalini, Georg Rutishauser, Alessio Burrello, Nazareno Bruschi, Angelo Garofalo, Luca Benini, Francesco Conti 0001, Davide Rossi	A 3 TOPS/W RISC-V Parallel Cluster for Inference of Fine-Grain Mixed-Precision Quantized Neural Networks.	ISVLSI	2023	DBLP DOI BibTeX RDF
13	Suman Deb, Anupam Chattopadhyay, Avi Mendelson	A RISC-V SoC with Hardware Trojans: Case Study on Trojan-ing the On-Chip Protocol Conversion.	VLSI-SoC	2023	DBLP DOI BibTeX RDF
13	Chun-Jen Tsai, Chun Wei Chao, Sheng-Di Hong	Integrated Dynamic Memory Manager for a RISC-V Processor.	VLSI-SoC	2023	DBLP DOI BibTeX RDF
13	Negin Safari, Amirmahdi Joudi, Maryam Rajabalipanah, Zahra Jahanpeima, Hasan Sadeghzadeh, Zainalabedin Navabi	HIRMA: High-Performance Implementation for RISC-V Microcontroller Applications.	EWDTS	2023	DBLP DOI BibTeX RDF
13	Nguyen The Binh, Binh Kieu-Do-Nguyen, Trong-Thuc Hoang, Cong-Kha Pham, Cuong Pham-Quoc	FPGA-Based Secured and Efficient Lightweight IoT Edge Devices with Customized RISC-V.	RIVF	2023	DBLP DOI BibTeX RDF
13	Marco Bertuletti, Yichao Zhang, Alessandro Vanelli-Coralli, Luca Benini	Efficient Parallelization of 5G-PUSCH on a Scalable RISC-V Many-Core Processor.	DATE	2023	DBLP DOI BibTeX RDF
13	Niklas Bruns, Vladimir Herdt, Rolf Drechsler	Processor Verification using Symbolic Execution: A RISC-V Case-Study.	DATE	2023	DBLP DOI BibTeX RDF
13	Luca Valente, Yvan Tortorella, Mattia Sinigaglia, Giuseppe Tagliavini, Alessandro Capotondi, Luca Benini, Davide Rossi	HULK-V: a Heterogeneous Ultra-low-power Linux capable RISC-V SoC.	DATE	2023	DBLP DOI BibTeX RDF
13	Sébastien Pillement, Maria Mendez Real, J. Pottier, T. Nieddu, Bertrand Le Gal, Sébastien Faucou, Jean-Luc Béchennec, Mikaël Briday, Sylvain Girbal, Jimmy Le Rhun, Olivier Gilles, Daniel Gracia Pérez, A. Sintzoff, J. R. Coulon	Securing a RISC-V architecture: A dynamic approach.	DATE	2023	DBLP DOI BibTeX RDF
13	Jina Park, Eunjin Choi, Kyungwon Lee, Jae-Jin Lee, Kyuseung Han, Woojoo Lee	Developing an Ultra-low Power RISC-V Processor for Anomaly Detection.	DATE	2023	DBLP DOI BibTeX RDF
13	Huimin Li 0004, Nele Mentens, Stjepan Picek	Maximizing the Potential of Custom RISC-V Vector Extensions for Speeding up SHA-3 Hash Functions.	DATE	2023	DBLP DOI BibTeX RDF
13	Anthony Zgheib, Olivier Potin, Jean-Baptiste Rigaud, Jean-Max Dutertre	A CCFI Verification Scheme Based on the RISC-V Trace Encoder.	COSADE	2023	DBLP DOI BibTeX RDF
13	Gianmarco Ottavi, Florian Zaruba, Luca Benini, Davide Rossi	Reducing Load-Use Dependency-Induced Performance Penalty in the Open-Source RISC-V CVA6 CPU.	DSD	2023	DBLP DOI BibTeX RDF
13	Ramon Canal, Cristiano Pegoraro Chenet, Aggelos Arelakis, José-María Arnau, Josep Lluís Berral, Aaron Call, Stefano Di Carlo, Juan José Costa, Dimitris Gizopoulos, Vasileios Karakostas, Francesco Lubrano, Konstantinos Nikas, Yiannis Nikolakopoulos, Beatriz Otero, George Papadimitriou 0001, Ioannis Papaefstathiou, Dionisios N. Pnevmatikatos, Daniel Raho, Alvise Rigo, Eva Rodríguez, Alessandro Savino, Alberto Scionti, Nikolaos Tampouratzis, Alex Torregrosa	VITAMIN-V: Virtual Environment and Tool-Boxing for Trustworthy Development of RISC-V Based Cloud Services.	DSD	2023	DBLP DOI BibTeX RDF
13	Mehrdad Poorhosseini, Kim Grüttner	A RISC-V based platform supporting mixed timing-critical and high performance workloads.	DSD	2023	DBLP DOI BibTeX RDF
13	Weiyan Zhang, Mehran Goli, Muhammad Hassan 0002, Rolf Drechsler	Efficient ML-Based Performance Estimation Approach Across Different Microarchitectures for RISC-V Processors.	DSD	2023	DBLP DOI BibTeX RDF
13	Michelangelo Barocci, Vittorio Fra, Enrico Macii, Gianvito Urgese	Review of open neuromorphic architectures and a first integration in the RISC-V PULP platform.	MCSoC	2023	DBLP DOI BibTeX RDF
13	Akihiro Saiki, Yu Omori, Keiji Kimura	Parallel Verification in RISC-V Secure Boot.	MCSoC	2023	DBLP DOI BibTeX RDF
13	Bastien Hubert, Omar Hammami	Multi-objective Optimisation of RISC-V CV32A6 for ML application.	MCSoC	2023	DBLP DOI BibTeX RDF
13	Kenji Kise	An open-source and GUI-capable RISC-V computer system on a low-end FPGA board.	MCSoC	2023	DBLP DOI BibTeX RDF
13	Yuji Yamada, Nesrine Berjab, Tomohiro Yoneda, Kenji Kise	A remote partial-reconfigurable SoC with a RISC-V soft processor targeting low-end FPGAs.	MCSoC	2023	DBLP DOI BibTeX RDF
13	Ruxandra Balucea, Paul Irofti	Software Mitigation of RISC-V Spectre Attacks.	SecITC	2023	DBLP DOI BibTeX RDF
13	Bruno E. Forlin, Wouter van Huffelen, Carlo Cazzaniga, Paolo Rech, Nikolaos Alachiotis 0001, Marco Ottavi	An unprotected RISC-V Soft-core processor on an SRAM FPGA: Is it as bad as it sounds?	ETS	2023	DBLP DOI BibTeX RDF
13	Tobias Faller, Nikolaos Ioannis Deligiannis, Markus Schwörer, Matteo Sonza Reorda, Bernd Becker 0001	Constraint-Based Automatic SBST Generation for RISC-V Processor Families.	ETS	2023	DBLP DOI BibTeX RDF
13	Marti Alonso, David Andreu 0003, Ramon Canal, Stefano Di Carlo, Cristiano Pegoraro Chenet, Juanjo Costa, Andreu Girones, Dimitris Gizopoulos, Vasileios Karakostas, Beatriz Otero, George Papadimitriou 0001, Eva Rodríguez, Alessandro Savino	Validation, Verification, and Testing (VVT) of future RISC-V powered cloud infrastructures: the Vitamin-V Horizon Europe Project perspective.	ETS	2023	DBLP DOI BibTeX RDF
13	Jens Anders, Pablo Andreu, Bernd Becker 0001, Steffen Becker 0001, Riccardo Cantoro, Nikolaos Ioannis Deligiannis, Nourhan Elhamawy, Tobias Faller, Carles Hernández 0001, Nele Mentens, Mahnaz Namazi Rizi, Ilia Polian, Abolfazl Sajadi, Matthias Sauer 0002, Denis Schwachhofer, Matteo Sonza Reorda, Todor Stefanov, Ilya Tuzov, Stefan Wagner 0001, Nusa Zidaric	A Survey of Recent Developments in Testability, Safety and Security of RISC-V Processors.	ETS	2023	DBLP DOI BibTeX RDF
13	Yue Gao, Wei Qian, Enfang Cui	RISC-V ISA Extension Toolchain Supports: A Survey.	CNIOT	2023	DBLP DOI BibTeX RDF
13	Yulong Chen, YanJie Pei, Xiang Lu, Mengyao Shi	Point Multiplication ZigZag: An Optimized Co-Processor Architecture Design for SM2/3 Based on RISC-V.	ICC	2023	DBLP DOI BibTeX RDF
13	Mohammadhossein Askarihemmat, Sean Wagner, Olexa Bilaniuk, Yassine Hariri, Yvon Savaria, Jean-Pierre David	BARVINN: Arbitrary Precision DNN Accelerator Controlled by a RISC-V CPU.	ASP-DAC	2023	DBLP DOI BibTeX RDF
13	Zicheng He, Ao Shen, Qiufeng Li, Quan Cheng, Hao Yu 0001	Agile Hardware and Software Co-Design for RISC-V-Based Multi-Precision Deep Learning Microprocessor.	ASP-DAC	2023	DBLP DOI BibTeX RDF
13	Johannes Geier, Lukas Auer, Daniel Mueller-Gritschneder, Uzair Sharif, Ulf Schlichtmann	CompaSeC: A Compiler-Assisted Security Countermeasure to Address Instruction Skip Fault Attacks on RISC-V.	ASP-DAC	2023	DBLP DOI BibTeX RDF
13	Sajjad Parvin, Mehran Goli, Frank Sill Torres, Rolf Drechsler	Trojan-D2: Post-Layout Design and Detection of Stealthy Hardware Trojans - A RISC-V Case Study.	ASP-DAC	2023	DBLP DOI BibTeX RDF
13	Konstantina Miteloudi, Joppe W. Bos, Olivier Bronchain, Björn Fay, Joost Renes	PQ.V.ALU.E: Post-quantum RISC-V Custom ALU Extensions on Dilithium and Kyber.	CARDIS	2023	DBLP DOI BibTeX RDF
13	Shibo Tang, Jiacheng Zhu, Yifei Gao, Jing Zhou, Dejun Mu, Wei Hu 0008	Verifying RISC-V Privilege Transition Integrity Through Symbolic Execution.	ATS	2023	DBLP DOI BibTeX RDF
13	Lingjuan Wu, Yifei Gao, Jiacheng Zhu, Yu Tai, Wei Hu 0008	Security Verification of RISC-V System Based on ISA Level Information Flow Tracking.	ATS	2023	DBLP DOI BibTeX RDF
13	Ed Saribatir, Niko Zurstraßen, Dietmar Hildenbrand, Florian Stock, Atilio Morillo Piña, Frederic von Wegner, Zheng Yan, Shiping Wen 0001, Matthew Arnold	Game Physics Engine Using Optimised Geometric Algebra RISC-V Vector Extensions Code Using Fourier Series Data.	CGI (4)	2023	DBLP DOI BibTeX RDF
13	Lars Luchterhandt, Tom Nellius, Robert Beck, Rainer Dömer, Pascal Kneuper, Wolfgang Mueller, Babak Sadiye	Towards a Rocket Chip Based Implementation of the RISC-V GPC Architecture.	MBMV	2023	DBLP BibTeX RDF
13	Haosong Zhao, Rui Su, Rui Lin, Jiankuo Dong, Donglong Chen	Efficient Arithmetic for Polynomial Multiplication in Post-quantum Lattice-Based Cryptosystem on RISC-V Platform.	ACNS Workshops	2023	DBLP DOI BibTeX RDF
13	Kumudha Narasimhan, Mehdi Goli 0001	Accelerating Neural Networks Using Open Standard Software on RISC-V.	ISC Workshops	2023	DBLP DOI BibTeX RDF
13	Gopinath Mahale, Tejas Limbasiya, Muhammad Asad Aleem, Luis A. Plana, Aleksandar Duricic, Alireza Monemi, Xabier Abancens, Teresa Cervero, John D. Davis	Optimizations for Very Long and Sparse Vector Operations on a RISC-V VPU: A Work-in-Progress.	ISC Workshops	2023	DBLP DOI BibTeX RDF
13	Joseph K. L. Lee, Maurice Jamieson, Nick Brown 0002	Backporting RISC-V Vector Assembly.	ISC Workshops	2023	DBLP DOI BibTeX RDF
13	Josie E. Rodriguez Condia, Nikolaos Ioannis Deligiannis, Jacopo Sini, Riccardo Cantoro, Matteo Sonza Reorda	Functional Testing with STLs: A Step Towards Reliable RISC-V-based HPC Commodity Clusters.	ISC Workshops	2023	DBLP DOI BibTeX RDF
13	Luc Berger-Vergiat, Suma George Cardwell, Ben Feinberg, Simon D. Hammond, Clayton Hughes, Michael J. Levenhagen, Kevin T. Pedretti	Evaluation of HPC Workloads Running on Open-Source RISC-V Hardware.	ISC Workshops	2023	DBLP DOI BibTeX RDF
13	Markus Fritscher, Alessandro Veronesi, Andrea Baroni, Jianan Wen, Thorsten Spätling, Mamathamba Kalishettyhalli Mahadevaiah, Norbert Herfurth, Eduardo Perez, Markus Ulbricht 0002, Marc Reichenbach, Amelie Hagelauer, Milos Krstic	Prototyping Reconfigurable RRAM-Based AI Accelerators Using the RISC-V Ecosystem and Digital Twins.	ISC Workshops	2023	DBLP DOI BibTeX RDF
13	Filippo Mantovani, Pablo Vizcaino, Fabio Banchelli, Marta Garcia-Gasulla, Roger Ferrer, Georgios Ieronymakis, Nikolaos Dimou, Vassilis Papaefstathiou, Jesús Labarta	Software Development Vehicles to Enable Extended and Early Co-design: A RISC-V and HPC Case of Study.	ISC Workshops	2023	DBLP DOI BibTeX RDF
13	Gonzalo Gomez-Sanchez, Aaron Call, Xavier Teruel, Lorena Alonso, Ignasi Moran, Miguel Angel Perez, David Torrents, Josep Lluís Berral	Challenges and Opportunities for RISC-V Architectures Towards Genomics-Based Workloads.	ISC Workshops	2023	DBLP DOI BibTeX RDF
13	Xiang Zhao, Xianyi Zhang, Yiwei Zhang	Optimization of the FFT Algorithm on RISC-V CPUs.	ISC Workshops	2023	DBLP DOI BibTeX RDF
13	Alexandre Rodrigues 0006, Leonel Sousa, Aleksandar Ilic	Performance Modelling-Driven Optimization of RISC-V Hardware for Efficient SpMV.	ISC Workshops	2023	DBLP DOI BibTeX RDF
13	Joseph K. L. Lee, Maurice Jamieson, Nick Brown 0002, Ricardo Jesus	Test-Driving RISC-V Vector Hardware for HPC.	ISC Workshops	2023	DBLP DOI BibTeX RDF
13	Xiaofeng Zou, Yuanxi Peng, Qing Zhang	Design and Implementation of a Compiler Supporting RISC-V Custom Cryptographic and Vector Instructions.	CSAE	2023	DBLP DOI BibTeX RDF
13	John Alistair Kressel, Guillermo Callaghan, Cosmin Gorgovan, Mikel Luján	Evaluating the Impact of Optimizations for Dynamic Binary Modification on 64-bit RISC-V.	ISPASS	2023	DBLP DOI BibTeX RDF
13	Stefan Stoyanov, Nikolay Kakanakov, Maria Marinova	Secure Heterogeneous Architecture based on RISC-V and root-of-trust.	CompSysTech	2023	DBLP DOI BibTeX RDF
13	Carlos Gabriel de Araujo Gewehr, Fernando Gehm Moraes	Improving the Efficiency of Cryptography Algorithms on Resource-Constrained Embedded Systems via RISC-V Instruction Set Extensions.	SBCCI	2023	DBLP DOI BibTeX RDF
13	Willian Analdo Nunes, Marcos Luiggi Lemos Sartori, Matheus Trevisan Moreira, Fernando Gehm Moraes, Ney Laert Vilar Calazans	Validating an Automated Asynchronous Synthesis Environment with a Challenging Design: RISC-V.	SBCCI	2023	DBLP DOI BibTeX RDF
13	Eric Bavier, Nicholas Knight, Hugues de Lassus Saint-Genies, Eric Love	Vectorized Nonlinear Functions with the RISC-V Vector Extension.	ARITH	2023	DBLP DOI BibTeX RDF
13	Keyvan Farhang Razi, Alexandre Schmid	Programmable Seizure Detector Using a 32-bit RISC Processor for Implantable Medical Devices.	LASCAS	2023	DBLP DOI BibTeX RDF
13	Jonathan Saussereau, Christophe Jégo, Camille Leroux, Jean-Baptiste Bégueret	Design and Implementation of a RISC-V core with a Flexible Pipeline for Design Space Exploration.	ICECS	2023	DBLP DOI BibTeX RDF
13	Michael Rogenmoser, Luca Benini	Trikarenos: A Fault-Tolerant RISC-V-based Microcontroller for CubeSats in 28nm.	ICECS	2023	DBLP DOI BibTeX RDF
13	Samuel Riedel, Matheus A. Cavalcante, Manos Frouzakis, Domenic Wüthrich, Enis Mustafa, Arlind Billa, Luca Benini	MinPool: A 16-core NUMA-L1 Memory RISC-V Processor Cluster for Always-on Image Processing in 65nm CMOS.	ICECS	2023	DBLP DOI BibTeX RDF
13	Ahmet Çelik, Fatih Yilmaz, Mehmet Anil Korkmaz, Berna Ors	Implementation of CRYSTALS-Kyber Post-Quantum Algorithm Using RISC-V Processor.	ICECS	2023	DBLP DOI BibTeX RDF
13	Alexander Underwood, James E. Stine	Design Exploration of Magnitude Comparators for RISC-V System-on-Chip Architectures.	ACSSC	2023	DBLP DOI BibTeX RDF
13	Kevin Kim, David Money Harris, Kip Macsai-Goren	Design and Synthesis of RISC-V Bit Manipulation Extensions.	ACSSC	2023	DBLP DOI BibTeX RDF
13	David Beauchemin, Richard Khoury	RISC: Generating Realistic Synthetic Bilingual Insurance Contract.	Canadian AI	2023	DBLP DOI BibTeX RDF
13	Quentin Ducasse, Pascal Cotret, Loïc Lagadec	JIT Compiler Security through Low-Cost RISC-V Extension.	IPDPS Workshops	2023	DBLP DOI BibTeX RDF
13	Mao-Hsu Yen, Tzu-Feng Lin, Cheng-Hao Tsou, Yan-Wei Yu, Yih-Hsia Lin, Yuan-Fu Ku, Chien-Ting Kao	FPGA Design of RISC-V MCU Collaborative Industrial Printer Control System.	ICKII	2023	DBLP DOI BibTeX RDF
13	Mao-Hsu Yen, Cheng-Hao Tsou, Tzu-Feng Lin, Yih-Hsia Lin, Yuan-Fu Ku, Chien-Ting Kao	VLSI Implementation of RISC-V MCU with a variable stage pipeline.	ICKII	2023	DBLP DOI BibTeX RDF
13	Moritz Scherer, Manuel Eggimann, Alfio Di Mauro, Arpan Suravi Prasad, Francesco Conti 0001, Davide Rossi, Jorge Tomás Gómez, Ziyun Li, Syed Shakib Sarwar, Zhao Wang, Barbara De Salvo, Luca Benini	Siracusa: A Low-Power On-Sensor RISC-V SoC for Extended Reality Visual Processing in 16nm CMOS.	ESSCIRC	2023	DBLP DOI BibTeX RDF
13	Stefano Di Matteo, Luca Zulberti, Federico Cosimo Lapenna, Pietro Nannipieri, Luca Crocetti, Luca Fanucci, Sergio Saponara	A PUF-Based Secure Boot for RISC-V Architectures.	ApplePies	2023	DBLP DOI BibTeX RDF
13	Marcello Barbirotta, Marco Angioli, Antonio Mastrandrea, Abdallah Cheikh, Saeid Jamili, Francesco Menichelli, Mauro Olivieri	Single Event Transient Reliability Analysis on a Fault-Tolerant RISC-V Microprocessor Design.	ApplePies	2023	DBLP DOI BibTeX RDF
13	Damiano Angeloni, Lorenzo Canese, Gian Carlo Cardarilli, Luca Di Nunzio, Marco Re, Sergio Spanò	A RISC-V Hardware Accelerator for Q-Learning Algorithm.	ApplePies	2023	DBLP DOI BibTeX RDF
13	David Kebo Houngninou	FLIP: A RISC-V Visual Computer Architecture Simulator for K-12.	SIGCSE (2)	2023	DBLP DOI BibTeX RDF
13	Joël Porquet-Lupine, Hikari N. Sakai, Abhi Sohal	rvcodec.js: An Educational Converter for RISC-V Instructions.	SIGCSE (2)	2023	DBLP DOI BibTeX RDF
13	Sören Tempel, Tobias Brandt, Christoph Lüth	Versatile and Flexible Modelling of the RISC-V Instruction Set Architecture.	TFP	2023	DBLP DOI BibTeX RDF
13	Haoxiang Zhou, Haiqiao Hong, Dingbang Liu, Hang Liu, Yu Xia, Kai Li, Jun Liu, Shaobo Luo, Wei Mao 0002, Hao Yu 0001	RISC-V based Fully-Parallel SRAM Computing-in-Memory Accelerator with High Hardware Utilization and Data Reuse Rate.	AICAS	2023	DBLP DOI BibTeX RDF
13	Valentin Volokitin, Evgeny Kozinov, Valentina Kustikova, Alexey Liniov, Iosif B. Meyerov	Case Study for Running Memory-Bound Kernels on RISC-V CPUs.	PaCT	2023	DBLP DOI BibTeX RDF
13	Yuta Nojiri, Nobuyuki Yamasaki	A Design of Multithreaded RISC-V Processor for Real-Time System.	CANDARW	2023	DBLP DOI BibTeX RDF
13	Riku Takayama, Jubee Tada	An Implementation of an Instruction Controlled Cache Replacement Policy on a RISC-V Processor.	CANDARW	2023	DBLP DOI BibTeX RDF
13	Aleksi Korsman, Verneri Hirvonen, Otto Simola, Antti Tarkka, Marko Kosunen, Jussi Ryynänen	End-to-End Multi-Target Verification Environment for a RISC-V Microprocessor.	SMACD	2023	DBLP DOI BibTeX RDF
13	João Cassiano V. Fernandes, Helbert da Rocha, António Espírito-Santo 0001	Encryption and Authentication in Smart Transducers Implemented in RISC-V Softcore Processors.	ICIT	2023	DBLP DOI BibTeX RDF
13	Guoxiang Guo, Yuanyuan Qi, Minhao Zhu, Yang Wang 0006, Jerome Yen	The Potential of RISC-V Platform in Financial Computing on Option Pricing and Energy Efficiency.	SMC	2023	DBLP DOI BibTeX RDF
13	Naina Gupta 0001, Arpan Jati, Anupam Chattopadhyay	CRYSTALS-Dilithium on RISC-V Processor: Lightweight Secure Boot Using Post-Quantum Digital Signature.	ICCAD	2023	DBLP DOI BibTeX RDF
13	Théo Dupuis, Yoan Fournier, MohammadHossein AskariHemmat, Nizar El Zarif, François Leduc-Primeau, Jean-Pierre David, Yvon Savaria	Sparq: A Custom RISC-V Vector Processor for Efficient Sub-Byte Quantized Inference.	NEWCAS	2023	DBLP DOI BibTeX RDF
13	Michal Borowski, Chandrajit Pal, Sangeet Saha, Ludovico Poli, Xiaojun Zhai, Klaus D. McDonald-Maier	Anomaly Behaviour tracing of CHERI-RISC V using Hardware-Software Co-design.	NEWCAS	2023	DBLP DOI BibTeX RDF
13	Sören Tempel, Tobias Brandt, Christoph Lüth, Rolf Drechsler	Minimally Invasive Generation of RISC-V Instruction Set Simulators from Formal ISA Models.	FDL	2023	DBLP DOI BibTeX RDF
13	Milan Funck, Sallar Ahmadi-Pour, Vladimir Herdt, Rolf Drechsler	Identification of ISA-Level Mutation-Classes for Qualification of RISC-V Formal Verification.	FDL	2023	DBLP DOI BibTeX RDF
13	Yu Wang, Jinting Wu, Haodong Zheng, Zhenyu Ning, Boyuan He, Fengwei Zhang	Raft: Hardware-assisted Dynamic Information Flow Tracking for Runtime Protection on RISC-V.	RAID	2023	DBLP DOI BibTeX RDF
13	Yi-Kai Chen, Jia-Yu Li, Wai-Chi Fang	An Edge AI Accelerator of LRCN Model with RISC-V Platform for EEG-based Emotion Real-time Detection System.	BioCAS	2023	DBLP DOI BibTeX RDF
13	Abel Beyene, Zhongpan Wu, Karim Hammad, Ebrahim Ghafar-Zadeh, Sebastian Magierowski	RISC-V Multicore for Miniature DNA Sequencers.	BioCAS	2023	DBLP DOI BibTeX RDF
13	Marek Jahnke, Lucas Bublitz, Ulf Kulau	Performance Evaluation of PicoRV32 RISC-V Softcore for Resource-Constrained Devices.	NorCAS	2023	DBLP DOI BibTeX RDF
13	Fei Gao 0016, Ting-Jung Chang, Ang Li, Marcelo Orenes-Vera, Davide Giri, Paul J. Jackson, August Ning, Georgios Tziantzioulis, Joseph Zuckerman, Jinzheng Tu 0001, Kaifeng Xu, Grigory Chirkov, Gabriele Tombesi, Jonathan Balkind, Margaret Martonosi, Luca P. Carloni, David Wentzlaff	DECADES: A 67mm2, 1.46TOPS, 55 Giga Cache-Coherent 64-bit RISC-V Instructions per second, Heterogeneous Manycore SoC with 109 Tiles including Accelerators, Intelligent Storage, and eFPGA in 12nm FinFET.	CICC	2023	DBLP DOI BibTeX RDF
13	Ján Mach, Lukás Kohútka, Pavel Cicák	A New RISC-V CPU for Safety-Critical Systems.	MECO	2023	DBLP DOI BibTeX RDF
13	Luca Cuomo, Claudio Scordino, Alessandro Ottaviano, Nils Wistoff, Robert Balas, Luca Benini, Errico Guidieri, Ida Maria Savino	Towards a RISC-V Open Platform for Next-generation Automotive ECUs.	MECO	2023	DBLP DOI BibTeX RDF