Search results for "RLC"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
11	Waqar Zia, Klaus Diepold, Thomas Stockhammer	Complexity Constrained Robust Video Transmission for Hand-Held Devices.	ICIP (4)	2007	DBLP DOI BibTeX RDF
11	Saurabh K. Tiwary, Joel R. Phillips	WAVSTAN: waveform based variational static timing analysis.	DATE	2007	DBLP DOI BibTeX RDF
11	Brajesh Kumar Kaushik, Sankar Sarkar, Rajendra Prasad Agarwal, Ramesh C. Joshi	Crosstalk Analysis of an Inductively and Capacitively Coupled Interconnect Driven by a CMOS Gate.	ICIT	2007	DBLP DOI BibTeX RDF
11	Zhaohui Gan, Zhenkun Yang, Gaobin Li, Min Jiang	Automatic Synthesis of Practical Passive Filters Using Clonal Selection Principle-Based Gene Expression Programming.	ICES	2007	DBLP DOI BibTeX RDF
11	Pawel Fabijanski, Ryszard Lagoda	Digital Model of Series Resonant Converter with Piezoelectric Ceramic Transducers and Fuzzy Logic Control.	ICANNGA (1)	2007	DBLP DOI BibTeX RDF
11	Yung-Ta Li, Zhaojun Bai, Yangfeng Su, Xuan Zeng 0001	Parameterized model order reduction via a two-directional Arnoldi process.	ICCAD	2007	DBLP DOI BibTeX RDF
11	Arthur Nieuwoudt, Yehia Massoud	Assessing the Implications of Process Variations on Future Carbon Nanotube Bundle Interconnect Solutions.	ISQED	2007	DBLP DOI BibTeX RDF
11	Shoou-Jinn Chang, Hao-Sheng Hou, Yan-Kuin Su	Automated passive filter synthesis using a novel tree representation and genetic programming.	IEEE Trans. Evol. Comput.	2006	DBLP DOI BibTeX RDF
11	Arijit Raychowdhury, Kaushik Roy 0001	Modeling of metallic carbon-nanotube interconnects for circuit simulations and a comparison with Cu interconnects for scaled technologies.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
11	Zhao Li, C.-J. Richard Shi	A Quasi-Newton Preconditioned Newton-Krylov Method for Robust and Efficient Time-Domain Simulation of Integrated Circuits With Strong Parasitic Couplings.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
11	Janet Meiling Wang, Jun Li 0066, Satish K. Yanamanamanda, Lakshmi Kalpana Vakati, Kishore Kumar Muchherla	Modeling the Driver Load in the Presence of Process Variations.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
11	James D. Ma, Rob A. Rutenbar	Fast Interval-Valued Statistical Modeling of Interconnect and Effective Capacitance.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
11	Vaibhava Goel, Shankar Kumar, William Byrne	Corrections to "Segmental minimum Bayes-risk decoding for automatic speech recognition".	IEEE Trans. Speech Audio Process.	2006	DBLP DOI BibTeX RDF
11	Shang-Fang Tsai, Shanq-Jang Ruan	DS2IS: Dictionary-based Segmented Signal Inversion Scheme for Low Power Dynamic Bus Design.	ICIT	2006	DBLP DOI BibTeX RDF
11	Takayuki Watanabe, Yuichi Tanji, Hidemasa Kubota, Hideki Asai	Parallel-distributed time-domain circuit simulation of power distribution networks with frequency-dependent parameters.	ASP-DAC	2006	DBLP DOI BibTeX RDF
11	Zhao Li, C.-J. Richard Shi	A quasi-newton preconditioned Newton-Krylov method for robust and efficient time-domain simulation of integrated circuits with strong parasitic couplings.	ASP-DAC	2006	DBLP DOI BibTeX RDF
11	Shanq-Jang Ruan, Edwin Naroska, Chun-Chih Chen	Optimal partitioned fault-tolerant bus layout for reducing power in nanometer designs.	ISPD	2006	DBLP DOI BibTeX RDF	fault-tolerant, reliability, low power, coupling capacitance
11	Nahi H. Abdul Ghani, Farid N. Najm	Handling inductance in early power grid verification.	ICCAD	2006	DBLP DOI BibTeX RDF
11	Magnus G. J. Lind, Guy Albert Dumont, William G. Dunford	Analysis of a circuit exhibiting ferroresonance.	ISCAS	2006	DBLP DOI BibTeX RDF
11	Di Mu, Tian Xia, Hao Zheng 0001	Data Dependent Jitter Characterization Based on Fourier Analysis.	DFT	2006	DBLP DOI BibTeX RDF
11	Min Chen 0024, Yu Cao 0001	Analysis of Pulse Signaling for Low-Power On-Chip Global Bus Design.	ISQED	2006	DBLP DOI BibTeX RDF
11	Zhuo Feng, Peng Li 0001, Jiang Hu	Efficient Model Update for General Link-Insertion Networks.	ISQED	2006	DBLP DOI BibTeX RDF
11	Andrew B. Kahng, Bao Liu 0001, Sheldon X.-D. Tan	SMM: Scalable Analysis of Power Delivery Networks by Stochastic Moment Matching.	ISQED	2006	DBLP DOI BibTeX RDF
11	Ruey-Lue Wang, Shih-Chih Chen, Hsiang-Chen Kuo, Chien-Hsuan Liu	A 0.18-µm CMOS UWB Low Noise Amplifier for Full-Band (3.1-10.6GHz) Application.	APCCAS	2006	DBLP DOI BibTeX RDF
11	Yici Cai, Xin Zhao, Qiang Zhou 0001, Xianlong Hong	Shielding Area Optimization Under the Solution of Interconnect Crosstalk.	J. Comput. Sci. Technol.	2005	DBLP DOI BibTeX RDF	middle shield insertion, crosstalk, inductive coupling
11	James D. Z. Ma, Rob A. Rutenbar	Fast interval-valued statistical interconnect modeling and reduction.	ISPD	2005	DBLP DOI BibTeX RDF	interval-valued statistical interconnect analysis, manufacturing variation, affine arithmetic
11	Kai Zheng 0003, Zhen Liu 0018, Bin Liu 0001	High Performance Embedded Route Lookup Coprocessor for Network Processors.	ICCNMC	2005	DBLP DOI BibTeX RDF
11	Kai-Sheng Lu, Xiao-Yu Feng, Guo-Zhang Gao	The separability, reducibility and controllability of RLCM networks over F(z).	ISCAS (1)	2005	DBLP DOI BibTeX RDF
11	Hideo Nakano, Hirohiko Honda, Hideaki Okazaki	Canards in a slow-fast continuous piecewise linear vector field.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
11	Ruifeng Sun, Jaejin Park, Frank O'Mahony, C. Patrick Yue	A low-power, 20-Gb/s continuous-time adaptive passive equalizer.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
11	Youngsoo Shin, Hyung-Ock Kim	Analysis of power consumption in VLSI global interconnects.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
11	Hao-Sheng Hou, Shoou-Jinn Chang, Yan-Kuin Su	Economical passive filter synthesis using genetic programming based on tree representation.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
11	Mustapha Hedabou, Pierre Pinel, Lucien Bénéteau	Countermeasures for Preventing Comb Method Against SCA Attacks.	ISPEC	2005	DBLP DOI BibTeX RDF	comb method, pre-computed table, memory space, side channel attacks, Elliptic curve, scalar multiplication
11	Mustapha Hedabou	Efficient Countermeasures for Thwarting the SCA Attacks on the Frobenius Based Methods.	IMACC	2005	DBLP DOI BibTeX RDF	?–adic method, precomputed table, Side Channel Attacks, Elliptic curve, scalar multiplication, Frobenius map
11	Haihua Su, David Widiger, Chandramouli V. Kashyap, Frank Liu 0001, Byron Krauter	A noise-driven effective capacitance method with fast embedded noise rule calculation for functional noise analysis.	DAC	2005	DBLP DOI BibTeX RDF	glitch propagation, noise analysis, effective capacitance
11	Yungseon Eo, Seongkyun Shin, William R. Eisenstadt, Jongin Shim	A decoupling technique for efficient timing analysis of VLSI interconnects with dynamic circuit switching.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
11	Kevin M. Lepak, Min Xu, Jun Chen 0008, Lei He 0001	Simultaneous shield insertion and net ordering for capacitive and inductive coupling minimization.	ACM Trans. Design Autom. Electr. Syst.	2004	DBLP DOI BibTeX RDF	VLSI physical design automation and on-chip inductance, net ordering, noise minimization, signal integrity, shielding
11	Ji-An Zhao, Bo Li 0001, Chi-Wah Kok, Ishfaq Ahmad	MPEG-4 Video Transmission over Wireless Networks: A Link Level Performance Study.	Wirel. Networks	2004	DBLP DOI BibTeX RDF	DBMAP with marked transitions, HMM channel, PH-type distribution, DBMAP/PH/1 priority queue
11	Howard Chen 0001, Daniel L. Ostapko	Modeling Temporal and Spatial Power Supply Voltage Variation for Timing Analysis.	PATMOS	2004	DBLP DOI BibTeX RDF
11	Alain Lopez, Denis Deschacht	Comparison between Different Data Buses Configurations.	ISVLSI	2004	DBLP DOI BibTeX RDF
11	Hao Ji, Qingjian Yu, Wayne Wei-Ming Dai	SPICE compatible circuit models for partial reluctance K.	ASP-DAC	2004	DBLP DOI BibTeX RDF
11	Paulo Sérgio B. do Nascimento, Paulo Romero Martins Maciel, Manoel Eusébio de Lima, Remy Eskinazi Sant'Anna, Abel Guilhermino Silva-Filho	A partial reconfigurable architecture for controllers based on Petri nets.	SBCCI	2004	DBLP DOI BibTeX RDF	virtual hardware, FPGAs, Petri nets, partial reconfiguration, programmable logic controller (PLC)
11	Arijit Raychowdhury, Kaushik Roy 0001	A circuit model for carbon nanotube interconnects: comparative study with Cu interconnects for scaled technologies.	ICCAD	2004	DBLP DOI BibTeX RDF
11	Janet Meiling Wang, Praveen Ghanta, Sarma B. K. Vrudhula	Stochastic analysis of interconnect performance in the presence of process variations.	ICCAD	2004	DBLP DOI BibTeX RDF
11	Michael D. Powell, T. N. Vijaykumar	Exploiting Resonant Behavior to Reduce Inductive Noise.	ISCA	2004	DBLP DOI BibTeX RDF
11	Yu Cao 0001, Chenming Hu, Xuejue Huang, Andrew B. Kahng, Igor L. Markov, Michael Oliver, Dirk Stroobandt, Dennis Sylvester	Improved a priori interconnect predictions and technology extrapolation in the GTX system.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
11	M. A. Azadpour, T. S. Kalkur	A clock interconnect extractor for multigigahertz frequencies incorporating inductance effect.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
11	Gregorio Cappuccino	Operating Region Modelling of Deep-submicron CMOS Buffers Driving Global Scope Inductive Interconnects.	DSD	2003	DBLP DOI BibTeX RDF
11	Sergey Gorinsky, Sugat Jain, Harrick M. Vin, Yongguang Zhang	Robustness to inflated subscription in multicast congestion control.	SIGCOMM	2003	DBLP DOI BibTeX RDF	misbehaving receivers, multicast, robustness, congestion control, fair bandwidth allocation
11	William O. McCallister, Chih-Cheng Hung	Image Segmentation Using Dynamic Run-Length Coding Technique.	SCIA	2003	DBLP DOI BibTeX RDF
11	Sheldon X.-D. Tan	A General S-Domain Hierarchical Network Reduction Algorithm.	ICCAD	2003	DBLP DOI BibTeX RDF
11	Bernard N. Sheehan	Branch Merge Reduction of RLCM Networks.	ICCAD	2003	DBLP DOI BibTeX RDF	transmission-line modeling, Gaussian elimination, model order reduction, Parasitic extraction
11	Christos Bouras, Apostolos Gkamas	Comparing Performance of SRAMT-LE Vs. Other Layered Encoding Schemes Regarding TCP Friendliness.	HSNMC	2003	DBLP DOI BibTeX RDF
11	Haitian Hu, David T. Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao 0001, Rajendran Panda, Sachin S. Sapatnekar	Table look-up based compact modeling for on-chip interconnect timing and noise analysis.	ISCAS (4)	2003	DBLP DOI BibTeX RDF
11	Amorn Jiraseree-amornkun, Nobuo Fujii, Wanlop Surakampontorn	Realization of electronically tunable ladder filters using multi-output current controlled conveyors.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
11	Herng-Jer Lee, Chia-Chi Chu, Wu-Shiung Feng	Interconnect modeling and sensitivity analysis using adjoint networks reduction technique.	ISCAS (4)	2003	DBLP DOI BibTeX RDF
11	J. Y. Son, K. R. Kang, D. Lee, S. H. Kang, Y. H. Lee, D. W. Han	Router-Assisted TCP-Friendly Traffic Control for Layered Multicast.	ICOIN	2003	DBLP DOI BibTeX RDF
11	Kai Wang 0011, Malgorzata Marek-Sadowska	On-chip power supply network optimization using multigrid-based technique.	DAC	2003	DBLP DOI BibTeX RDF	congestion-aware, multigrid, power supply noise
11	Emad Gad, Michel S. Nakhla	Model order reduction of nonuniform transmission lines using integrated congruence transform.	DAC	2003	DBLP DOI BibTeX RDF	integrated congruence transform, nonuniform transmission lines, circuit simulation, signal integrity, model-order reduction, high-speed circuits
11	Xin Li 0001, Peng Li 0001, Yang Xu 0017, Lawrence T. Pileggi	Analog and RF circuit macromodels for system-level analysis.	DAC	2003	DBLP DOI BibTeX RDF	analog/RF circuits, macromodel
11	Kevin T. Tang, Eby G. Friedman	Simultaneous switching noise in on-chip CMOS power distribution networks.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
11	Kaushik Gala, David T. Blaauw, Vladimir Zolotov, Pravin M. Vaidya, Anil Joshi	Inductance model and analysis methodology for high-speed on-chip interconnect.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
11	Emrah Acar, Florentin Dartu, Lawrence T. Pileggi	TETA: transistor-level waveform evaluation for timing analysis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
11	Gregorio Cappuccino, Giuseppe Cocorullo	Operating Region Modelling and Timing Analysis of CMOS Gates Driving Transmission Lines.	PATMOS	2002	DBLP DOI BibTeX RDF
11	David Goren, Michael Zelikson, Tiberiu C. Galambos, Rachel Gordin, Betty Livshitz, Alon Amir, Anatoly Sherman, Israel A. Wagner	An Interconnect-Aware Methodology for Analog and Mixed Signal Design, Based on High Bandwidth (Over 40 Ghz) On-Chip Transmission Line Approach .	DATE	2002	DBLP DOI BibTeX RDF
11	Alfredo Sanz, José I. García-Nicolás, Isidoro Urriza	Implementing Converters in FPLD.	FPL	2002	DBLP DOI BibTeX RDF
11	Guoan Zhong, Cheng-Kok Koh, Kaushik Roy 0001	On-chip interconnect modeling by wire duplication.	ICCAD	2002	DBLP DOI BibTeX RDF
11	Hui Zheng, Lawrence T. Pileggi	Robust and passive model order reduction for circuits containing susceptance elements.	ICCAD	2002	DBLP DOI BibTeX RDF
11	Yigang He, Jinguang Jiang, Yichuang Sun	CMOS R-MOSFET-C fourth-order Bessel filter with accurate group delay.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
11	Amir Attarha, Mehrdad Nourani	Test Pattern Generation for Signal Integrity Faults on Long Interconnects.	VTS	2002	DBLP DOI BibTeX RDF
11	Morteza Analoui, Mohammad Hossein Rezvani	Performance enhancement of logical link control using channel quality in GPRS.	APCCAS (1)	2002	DBLP DOI BibTeX RDF
11	Amir Attarha, Mehrdad Nourani	Signal integrity fault analysis using reduced-order modeling.	DAC	2002	DBLP DOI BibTeX RDF	integrity fault, locality factor, test pattern generation, signal integrity, reduced-order model
11	Vivek K. Shanbhag, K. Gopinath, Markku Turunen, Ari Ahtiainen, Matti Luukkainen	EASN: Integrating ASN.1 and Model Checking.	CAV	2001	DBLP DOI BibTeX RDF
11	Vivek K. Shanbhag, K. Gopinath	A SPIN-Based Model Checker for Telecommunication Protocols.	SPIN	2001	DBLP DOI BibTeX RDF
11	James D. Z. Ma, Lei He 0001	Simultaneous signal and power routing under K model.	SLIP	2001	DBLP DOI BibTeX RDF	net ordering, on-chip inductance, shield insertion, interconnect estimation, interconnect design
11	Shabbir H. Batterywala, H. Narayanan	Spectral Algorithm To Compute And Synthesize Reduced Order Passive Models For Arbitrary Rc Multiports.	VLSI Design	2001	DBLP DOI BibTeX RDF
11	Koichi Yano, Steven McCanne	A window-based congestion control for reliable multicast based on TCP dynamics.	ACM Multimedia	2000	DBLP DOI BibTeX RDF	TCP/IP
11	Shen Lin, Norman Chang, O. Sam Nakagawa	Quick On-Chip Self- and Mutual-Inductance Screen.	ISQED	2000	DBLP DOI BibTeX RDF	inductance screening, significant frequency, inductive coupling and inductive modeling, signal integrity
11	Takashi Hisakado, Kohshi Okumura	Steady states prediction in nonlinear circuit by wavelet transform.	ISCAS (6)	1999	DBLP DOI BibTeX RDF
11	Roland W. Freund, Peter Feldmann	Reduced-Order Modeling of Large Linear Passive Multi-Terminal Circuits Using Matrix-Pade Approximation.	DATE	1998	DBLP DOI BibTeX RDF	linear passive multi-terminal circuit, matrix-Pade approximants, Lanczos-type process, interconnect analysis, simulation, synthesis, transfer function
11	Payam Heydari, Massoud Pedram	Calculation of ramp response of lossy transmission lines using two-port network functions.	ISPD	1998	DBLP DOI BibTeX RDF
11	Yehea I. Ismail, Eby G. Friedman, José Luis Neves	Power dissipated by CMOS gates driving lossless transmission lines.	ISLPED	1998	DBLP DOI BibTeX RDF
11	Yehea I. Ismail, Eby G. Friedman, José Luis Neves	Dynamic and Short-Circuit Power of CMOS Gates Driving Lossless Transmission Lines.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	Lossless Transmission Lines, VLSI, Dynamic, Power, CMOS, Inductance, Short-circuit
11	Keith Nabors, Tze-Ting Fang, Hung-Wen Chang, Kenneth S. Kundert	Lumped Interconnect Models Via Gaussian Quadrature.	DAC	1997	DBLP DOI BibTeX RDF
11	Saed G. Younis, Thomas F. Knight Jr.	Non-dissipative rail drivers for adiabatic circuits.	ARVLSI	1995	DBLP DOI BibTeX RDF	driver circuits, distributed parameter networks, lumped parameter networks, passive networks, nondissipative rail drivers, adiabatic circuits, CMOS charge recovery logic, energy dissipation per operation, SCRL circuits, rail waveform generation, rail driver circuit, multiple harmonics, harmonic rail driver, passive reactive components, trimmed transmission line segments, CMOS logic circuits, CMOS circuits, harmonics
11	Jaijeet S. Roychowdhury, A. Richard Newton, Donald O. Pederson	Algorithms for the transient simulation of lossy interconnect.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
11	Demos F. Anastasakis, Nanda Gopal, Seok-Yoon Kim, Lawrence T. Pillage	Enhancing the stability of asymptotic waveform evaluation for digital interconnect circuit applications.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
11	Seok-Yoon Kim, Nanda Gopal, Lawrence T. Pillage	Time-domain macromodels for VLSI interconnect analysis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
11	Changsheng Ying, Jun Gu	Automated pin grid array package routing on multilayer ceramic substrates.	IEEE Trans. Very Large Scale Integr. Syst.	1993	DBLP DOI BibTeX RDF
11	Tak K. Tang, Michel S. Nakhla	Analysis of high-speed VLSI interconnects using the asymptotic waveform evaluation technique.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
11	Sergio Greco, Carlo Zaniolo	Optimization of Linear Logic Programs Using Counting Methods.	EDBT	1992	DBLP DOI BibTeX RDF
11	Lawrence T. Pillage, Xueqing Huang, Ronald A. Rohrer	AWEsim: Asymptotic Waveform Evaluation for Timing Analysis.	DAC	1989	DBLP DOI BibTeX RDF