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GrowBag graphs for keyword ? (Num. hits/coverage)
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Results
Found 1565 publication records. Showing 1565 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
16 | Marco Caldari, Massimo Conti, Massimo Coppola, Stephane Curaba, Lorenzo Pieralisi, Claudio Turchetti |
Transaction-Level Models for AMBA Bus Architecture Using SystemC 2.0. |
DATE |
2003 |
DBLP DOI BibTeX RDF |
|
16 | Yunsi Fei, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha |
Energy Estimation for Extensible Processors. |
DATE |
2003 |
DBLP DOI BibTeX RDF |
|
16 | Andreas Zeller |
Isolating Cause-Effect Chains with AskIgo. |
IWPC |
2003 |
DBLP DOI BibTeX RDF |
|
16 | Gérard Berry, Michael Kishinevsky, Satnam Singh |
System Level Design and Verification Using a Synchronous Language. |
ICCAD |
2003 |
DBLP DOI BibTeX RDF |
|
16 | Christophe Lohr, Ludovic Apvrille, Pierre de Saqui-Sannes, Jean-Pierre Courtiat |
New Operators for the TURTLE Real-Time UML Profile. |
FMOODS |
2003 |
DBLP DOI BibTeX RDF |
|
16 | Gary Feierbach, Vijay Gupta |
True Coverage: A Goal of Verification. |
ISQED |
2003 |
DBLP DOI BibTeX RDF |
toggle coverage, true coverage, diagnostic strategy, VLSI, Coverage, fault simulation, design verification, stuck faults |
16 | Ramesh Karri, Kaijie Wu 0001 |
Algorithm level re-computing using implementation diversity: a register transfer level concurrent error detection technique. |
IEEE Trans. Very Large Scale Integr. Syst. |
2002 |
DBLP DOI BibTeX RDF |
|
16 | Josef Strnadel, Zdenek Kotásek |
Testability Improvements Based on the Combination of Analytical and Evolutionary Approaches at RT Level. |
DSD |
2002 |
DBLP DOI BibTeX RDF |
|
16 | Andreas Zeller |
Isolating cause-effect chains from computer programs. |
SIGSOFT FSE |
2002 |
DBLP DOI BibTeX RDF |
testing, program comprehension, tracing, automated debugging |
16 | Sasha Novakovsky, Shy Shyman, Ziyad Hanna |
High capacity and automatic functional extraction tool for industrial VLSI circuit designs. |
ICCAD |
2002 |
DBLP DOI BibTeX RDF |
Formal Equivalence Verification (FEV), Hardware Description Languages (HDL), Switch Level Analysis, functional abstraction, satisfiability procedures, synthesis, Design For Testability (DFT), logic simulation, Binary Decision Diagrams (BDDs) |
16 | Chao Huang, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha |
High-level synthesis of distributed logic-memory architectures. |
ICCAD |
2002 |
DBLP DOI BibTeX RDF |
|
16 | Ivan Blunno, Luciano Lavagno |
Designing an Asynchronous Microcontroller Using Pipefitter. |
ICCD |
2002 |
DBLP DOI BibTeX RDF |
|
16 | Jerry C.-Y. Kao, C.-F. Su, Allen C.-H. Wu |
High-performance FIR generation based on a timing-driven architecture and component selection method. |
ISCAS (4) |
2002 |
DBLP DOI BibTeX RDF |
|
16 | A. Castelnuovo, Alessandro Fin, Franco Fummi, F. Sforza |
Emulation-Based Design Errors Identification. |
DFT |
2002 |
DBLP DOI BibTeX RDF |
|
16 | Narayanan Krishnamurthy, Jayanta Bhadra, Magdy S. Abadir, Jacob A. Abraham |
Is State Mapping Essential for Equivalence Checking Custom Memories in Scan-Based Designs? |
VTS |
2002 |
DBLP DOI BibTeX RDF |
|
16 | Prithviraj Banerjee, Malay Haldar, Anshuman Nayak, Victor Kim, Debabrata Bagchi, Satrajit Pal, Nikhil Tripathi |
A Behavioral Synthesis Tool for Exploiting Fine Grain Parallelism in FPGAs. |
IWDC |
2002 |
DBLP DOI BibTeX RDF |
|
16 | Srivaths Ravi 0001, Ganesh Lakshminarayana, Niraj K. Jha |
TAO: regular expression-based register-transfer level testability analysis and optimization. |
IEEE Trans. Very Large Scale Integr. Syst. |
2001 |
DBLP DOI BibTeX RDF |
|
16 | Srivaths Ravi 0001, Ganesh Lakshminarayana, Niraj K. Jha |
Testing of core-based systems-on-a-chip. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2001 |
DBLP DOI BibTeX RDF |
|
16 | Lionel Bening, Harry Foster |
Optimizing Multiple EDA Tools within the ASIC Design Flow. |
IEEE Des. Test Comput. |
2001 |
DBLP DOI BibTeX RDF |
|
16 | Janette Frigo, Maya B. Gokhale, Dominique Lavenier |
Evaluation of the streams-C C-to-FPGA compiler: an applications perspective. |
FPGA |
2001 |
DBLP DOI BibTeX RDF |
FPGA design tools, FPGA, high-level synthesis, configurable computing, hardware-software co-design, silicon compiler |
16 | Ross Smith, Michiel M. Ligthart |
High-level design for asynchronous logic. |
ASP-DAC |
2001 |
DBLP DOI BibTeX RDF |
|
16 | Rob Gerth |
Model Checking if Your Life Depends on It a View from Intel's Trenches. |
SPIN |
2001 |
DBLP DOI BibTeX RDF |
|
16 | M. Ernst, Steffen Klupsch, Oliver Hauck, Sorin A. Huss |
Rapid Prototyping for Hardware Accelerated Elliptic Curve Public-Key Cryptosystems. |
IEEE International Workshop on Rapid System Prototyping |
2001 |
DBLP DOI BibTeX RDF |
|
16 | Byeong Min, Gwan Choi |
ECC: Extended Condition Coverage for Design Verification Using Excitation and Observation. |
PRDC |
2001 |
DBLP DOI BibTeX RDF |
|
16 | Rajiv V. Joshi, Wei Hwang, Andreas Kuehlmann |
Design Of Provably Correct Storage Arrays. |
VLSI Design |
2001 |
DBLP DOI BibTeX RDF |
|
16 | Rupesh S. Shelar, Sacheendra Nath, Jagmohan S. Nanaware |
Parameterized Reusable Component Library Methodology. |
EUROMICRO |
2000 |
DBLP DOI BibTeX RDF |
|
16 | Hoon Choi, Myung-Kyoon Yim, Jae Young Lee, Byeong-Whee Yun, Yun-Tae Lee |
Formal Verification of an Industrial System-on-a-Chip. |
ICCD |
2000 |
DBLP DOI BibTeX RDF |
|
16 | Kamal S. Khouri, Niraj K. Jha |
Leakage Power Analysis and Reduction during Behavioral Synthesis. |
ICCD |
2000 |
DBLP DOI BibTeX RDF |
|
16 | Raul Camposano, Jacob Greidinger, Patrick Groeneveld, Michael Jackson 0004, Lawrence T. Pileggi, Louis Scheffer |
Design closure (panel session): hope or hype? |
DAC |
2000 |
DBLP DOI BibTeX RDF |
|
16 | Sofiène Tahar, Xiaoyu Song, Eduard Cerny, Zijian Zhou 0001, Michel Langevin, Otmane Aït Mohamed |
Modeling and formal verification of the Fairisle ATM switch fabricusing MDGs. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1999 |
DBLP DOI BibTeX RDF |
|
16 | Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha |
Hierarchical test generation and design for testability methods for ASPPs and ASIPs. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1999 |
DBLP DOI BibTeX RDF |
|
16 | Srivaths Ravi 0001, Ganesh Lakshminarayana, Niraj K. Jha |
A framework for testing core-based systems-on-a-chip. |
ICCAD |
1999 |
DBLP DOI BibTeX RDF |
|
16 | Marco Brera, Fabrizio Ferrandi, Donatella Sciuto, Franco Fummi |
Increase the Behavioral Fault Model Accuracy Using High-Level Synthesis Information. |
DFT |
1999 |
DBLP DOI BibTeX RDF |
behavioral fault model, functional TPG |
16 | Grant Martin |
Design Methodologies for System Level IP. |
DATE |
1998 |
DBLP DOI BibTeX RDF |
|
16 | Michiko Inoue, Takeshi Higashimura, Kenji Noda, Toshimitsu Masuzawa, Hideo Fujiwara |
A High-Level Synthesis Method for Weakly Testable Data Paths. |
Asian Test Symposium |
1998 |
DBLP DOI BibTeX RDF |
|
16 | Wen-Jong Fang, Allen C.-H. Wu |
A hierarchical functional structuring and partitioning approach for multiple-FPGA implementations. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1997 |
DBLP DOI BibTeX RDF |
|
16 | Samit Chaudhuri, Michael Quayle |
Synthesis using sequential functional modules (SFMs). |
ICCAD |
1996 |
DBLP DOI BibTeX RDF |
|
16 | Kevin Lano |
Reactive System Specification and Refinement. |
TAPSOFT |
1995 |
DBLP DOI BibTeX RDF |
|
16 | Qian Zhang, Herbert Grünbacher |
Petri Nets Modeling in Pipelined Microprocessor Design. |
Application and Theory of Petri Nets |
1993 |
DBLP DOI BibTeX RDF |
|
16 | Rajiv Jain, Kayhan Küçükçakar, Mitch J. Mlinar, Alice C. Parker |
Experience with ADAM Synthesis System. |
DAC |
1989 |
DBLP DOI BibTeX RDF |
|
15 | João Vieira, Nuno Roma, Gabriel Falcão 0001, Pedro Tomás |
gem5-accel: A Pre-RTL Simulation Toolchain for Accelerator Architecture Validation. |
IEEE Comput. Archit. Lett. |
2024 |
DBLP DOI BibTeX RDF |
|
15 | Matthew DeLorenzo, Animesh Basak Chowdhury, Vasudev Gohil, Shailja Thakur, Ramesh Karri, Siddharth Garg, Jeyavijayan Rajendran |
Make Every Move Count: LLM-based High-Quality RTL Code Generation Using MCTS. |
CoRR |
2024 |
DBLP DOI BibTeX RDF |
|
15 | Selim Sandal, Ismail Akturk |
Zero-Shot RTL Code Generation with Attention Sink Augmented Large Language Models. |
CoRR |
2024 |
DBLP DOI BibTeX RDF |
|
15 | Lennart M. Reimann, Anschul Prashar, Chiara Ghinami, Rebecca Pelke, Dominik Sisejkovic, Farhad Merchant, Rainer Leupers |
QTFlow: Quantitative Timing-Sensitive Information Flow for Security-Aware Hardware Design on RTL. |
CoRR |
2024 |
DBLP DOI BibTeX RDF |
|
15 | Runxi Wang, Jun-Han Han, Mircea Stan, Xinfei Guo |
Hot-LEGO: Architect Microfluidic Cooling Equipped 3DICs with Pre-RTL Thermal Simulation. |
CoRR |
2024 |
DBLP DOI BibTeX RDF |
|
15 | Wenji Fang, Shang Liu, Hongce Zhang, Zhiyao Xie |
Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization. |
CoRR |
2024 |
DBLP DOI BibTeX RDF |
|
15 | Gen Zhang, Pengfei Wang, Tai Yue, Danjun Liu, Yubei Guo, Kai Lu |
INSTILLER: Towards Efficient and Realistic RTL Fuzzing. |
CoRR |
2024 |
DBLP DOI BibTeX RDF |
|
15 | Mahyar Emami, Thomas Bourgeat, James R. Larus |
Parendi: Thousand-Way Parallel RTL Simulation. |
CoRR |
2024 |
DBLP DOI BibTeX RDF |
|
15 | Sahand Kashani, Mahyar Emami, Keisuke Kamahori, Mohammad Sepehr Pourghannad, Ritik Raj, James R. Larus |
A 475 MHz Manycore FPGA Accelerator for RTL Simulation. |
FPGA |
2024 |
DBLP DOI BibTeX RDF |
|
15 | Purav Bhatt, Dharmik Joshi, Shrikant Jadhav |
RTL to GDS Implementation and Verification of UART using UVM and OpenROAD. |
CCWC |
2024 |
DBLP DOI BibTeX RDF |
|
15 | Vinod Viswanath, Kanad Chakraborty |
DFT Static Verification using Early RTL Exploration and Debug for Mobile SoC and Edge AI Applications. |
VLSID |
2024 |
DBLP DOI BibTeX RDF |
|
15 | Haimanti Chakraborty, Ranga Vemuri |
ROBUST: RTL OBfuscation USing Bi-functional Polymorphic OperaTors. |
VLSID |
2024 |
DBLP DOI BibTeX RDF |
|
15 | Adwait Godbole, Kevin Cheang, Yatin A. Manerkar, Sanjit A. Seshia |
Lifting Micro-Update Models from RTL for Formal Security Analysis. |
ASPLOS (2) |
2024 |
DBLP DOI BibTeX RDF |
|
15 | Kevin Laeufer, Brandon Fajardo, Abhik Ahuja, Vighnesh Iyer, Borivoje Nikolic, Koushik Sen |
RTL-Repair: Fast Symbolic Repair of Hardware Design Code. |
ASPLOS (3) |
2024 |
DBLP DOI BibTeX RDF |
|
15 | Tamon Sadasue, Tsuyoshi Isshiki |
LLVM-C2RTL: C/C++ Based System Level RTL Design Framework Using LLVM Compiler Infrastructure. |
IPSJ Trans. Syst. LSI Des. Methodol. |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Bijan Alizadeh, Masoud Shiroei |
Automatic correction of RTL designs using a lightweight partial high level synthesis. |
Integr. |
2023 |
DBLP DOI BibTeX RDF |
|
15 | M. Sazadur Rahman, Rui Guo, Hadi Mardani Kamali, Fahim Rahman, Farimah Farahmandi, Mark M. Tehranipoor |
ReTrustFSM: Toward RTL Hardware Obfuscation-A Hybrid FSM Approach. |
IEEE Access |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Mohammad Rahmani Fadiheh, Alex Wezel, Johannes Müller, Jörg Bormann, Sayak Ray, Jason M. Fung, Subhasish Mitra, Dominik Stoffel, Wolfgang Kunz |
An Exhaustive Approach to Detecting Transient Execution Side Channels in RTL Designs of Processors. |
IEEE Trans. Computers |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Fubing Mao, Yapu Guo, Xiaofei Liao, Hai Jin 0001, Wei Zhang 0012, Haikun Liu, Long Zheng 0003, Xu Liu, Zihan Jiang, Xiaohua Zheng |
Accelerating Loop-Oriented RTL Simulation With Code Instrumentation. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Zhe Lin, Tingyuan Liang, Jieru Zhao, Sharad Sinha, Wei Zhang 0012 |
HL-Pow: Learning-Assisted Pre-RTL Power Modeling and Optimization for FPGA HLS. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Syed Asad Alam, David Gregg, Giulio Gambardella, Thomas B. Preußer, Michaela Blott |
On the RTL Implementation of FINN Matrix Vector Unit. |
ACM Trans. Embed. Comput. Syst. |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Hasini Witharana, Aruna Jayasena, Andrew Whigham, Prabhat Mishra 0001 |
Automated Generation of Security Assertions for RTL Models. |
ACM J. Emerg. Technol. Comput. Syst. |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Benzheng Li, Xi Zhang, Hailong You, Zhongdong Qi, Yuming Zhang |
Machine Learning Based Framework for Fast Resource Estimation of RTL Designs Targeting FPGAs. |
ACM Trans. Design Autom. Electr. Syst. |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Kinar S, Prashanth K. V, Adithya Hegde, Aditya Subrahmanya Bhat, Narender M |
Transpiling RTL Pseudo-code of the POWER Instruction Set Architecture to C for Real-time Performance Analysis on Cavatools Simulator. |
CoRR |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Mengxi Liu, Bo Zhou 0005, Zimin Zhao, Hyeonseok Hong, Hyun Kim, Sungho Suh, Vítor Fortes Rey, Paul Lukowicz |
FieldHAR: A Fully Integrated End-to-end RTL Framework for Human Activity Recognition with Neural Networks from Heterogeneous Sensors. |
CoRR |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Jingyu Pan, Chen-Chia Chang, Zhiyao Xie, Yiran Chen 0001 |
EDALearn: A Comprehensive RTL-to-Signoff EDA Benchmark for Democratized and Reproducible ML for EDA Research. |
CoRR |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Ruby Kumari, Jai Gopal Pandey, Abhijit Karmakar |
An RTL Implementation of the Data Encryption Standard (DES). |
CoRR |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Shang Liu, Wenji Fang, Yao Lu, Qijun Zhang, Hongce Zhang, Zhiyao Xie |
RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solution. |
CoRR |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Mahyar Emami, Sahand Kashani, Keisuke Kamahori, Mohammad Sepehr Pourghannad, Ritik Raj, James R. Larus |
Manticore: Hardware-Accelerated RTL Simulation with Static Bulk-Synchronous Parallelism. |
CoRR |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Wenji Fang, Yao Lu, Shang Liu, Qijun Zhang, Ceyu Xu, Lisa Wu Wills, Hongce Zhang, Zhiyao Xie |
MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design. |
CoRR |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Yingjie Li, Mingju Liu, Alan Mishchenko, Cunxi Yu |
Verilog-to-PyG - A Framework for Graph Learning and Augmentation on RTL Designs. |
CoRR |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Marcelo Orenes-Vera, Margaret Martonosi, David Wentzlaff |
Using LLMs to Facilitate Formal Verification of RTL. |
CoRR |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Amisha Srivastava, Sanjay Das, Navnil Choudhury, Rafail Psiakis, Pedro Henrique Silva, Debjit Pal, Kanad Basu |
SCAR: Power Side-Channel Analysis at RTL-Level. |
CoRR |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Hasini Witharana, Aruna Jayasena, Prabhat Mishra 0001 |
Sequence-Based Incremental Concolic Testing of RTL Models. |
CoRR |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Yun-Da Tsai, Mingjie Liu, Haoxing Ren |
RTLFixer: Automatically Fixing RTL Syntax Errors with Large Language Models. |
CoRR |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Sallar Ahmadi-Pour, Pascal Pieper, Rolf Drechsler |
Virtual-Peripheral-in-the-Loop : A Hardware-in-the-Loop Strategy to Bridge the VP/RTL Design-Gap. |
CoRR |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Yao Lu, Shang Liu, Qijun Zhang, Zhiyao Xie |
RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model. |
CoRR |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Stefan Bosse |
Rule-based High-level Hardware-RTL Synthesis of Algorithms, Virtualizing Machines, and Communication Protocols with FPGAs based on Concurrent Communicating Sequential Processes and the ConPro Synthesis Framework. |
CoRR |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Seungmin Jung |
Implementation of Novel GDI D-Flip-Flop for RTL Design. |
J. Comput. Sci. Eng. |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Peitian Pan, Christopher Batten |
Formal Verification of the Stall Invariant Property for Latency-Insensitive RTL Modules. |
MEMOCODE |
2023 |
DBLP BibTeX RDF |
|
15 | Jisu Kwon, Heuijee Yun, Daejin Park |
Dynamic MAC Unit Pruning Techniques in Runtime RTL Simulation for Area-Accuracy Efficient Implementation of Neural Network Accelerator. |
MWSCAS |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Sundarakumar Muthukumaran, Aparajithan Nathamuni Venkatesan, Kishore Pula, Ram Venkat Narayanan, Ranga Vemuri, John Marty Emmert |
Reverse Engineering of RTL Controllers from Look-Up Table Netlists. |
ISVLSI |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Guillem López-Paradís, Brian Li, Adrià Armejach, Stefan Wallentowitz, Miquel Moretó, Jonathan Balkind |
Fast Behavioural RTL Simulation of 10B Transistor SoC Designs with Metro-Mpi. |
DATE |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Md Rafid Muttaki, Shyvagata Saha, Hadi Mardani Kamali, Fahim Rahman, Mark M. Tehranipoor, Farimah Farahmandi |
RTLock: IP Protection using Scan-Aware Logic Locking at RTL. |
DATE |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Alberto Bosio, Samuele Germiniani, Graziano Pravadelli, Marcello Traiola |
Exploiting assertions mining and fault analysis to guide RTL-level approximation. |
DATE |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Ziyue Zheng, Yangdi Lyu |
STSearch: State Tracing-based Search Heuristics for RTL Validation. |
DATE |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Shailja Thakur, Baleegh Ahmad, Zhenxing Fan, Hammond Pearce, Benjamin Tan 0001, Ramesh Karri, Brendan Dolan-Gavitt, Siddharth Garg |
Benchmarking Large Language Models for Automated Verilog RTL Code Generation. |
DATE |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Richard Ruzicka, Václav Simek, Jan Nevoral |
Polymorphic RTL Computational Elements. |
DSD |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Kexing Zhou, Yun Liang 0001, Yibo Lin, Runsheng Wang, Ru Huang |
Khronos: Fusing Memory Access for Improved Hardware RTL Simulation. |
MICRO |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Fares Elsabbagh, Shabnam Sheikhha, Victor A. Ying, Quan M. Nguyen, Joel S. Emer, Daniel Sánchez 0003 |
Accelerating RTL Simulation with Hardware-Software Co-Design. |
MICRO |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Madhur Kumar, Deepank Grover, Tarun Sharma, Sujay Deb |
NoxyGen: A Network-On-Chip RTL Generator and Validation Tool. |
NoCArc@MICRO |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Haoyi Wang, Qiang Zhou 0001, Yici Cai |
Static Probability Analysis Guided RTL Hardware Trojan Test Generation. |
ASP-DAC |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Yue Cheng, Hongji Zou, Jiayu He, Chen Chen, Tun Li, Han Long |
MMFuzz: Towards Enhancing RTL Fuzz Testing Using Metric Feedbacks Based on Markov Chain. |
ATS |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Wilbur L. Myrick, Nobuyasu Shiga, Julian St. James, Ahmad Byagowi |
Exploring Wireless Clock Synchronization with OCP-TAP Time Cards and RTL-SDRs. |
ISPCS |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Zhuanhao Wu, Maya B. Gokhale, Scott Lloyd, Hiren D. Patel |
SCCL: An open-source SystemC to RTL translator. |
FCCM |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Myeongjin Kang, Nayoung Kwon, Seungmin Lee, Daejin Park |
Fast Bit Inversion Vulnerability Pre-estimation using Tcl and UPF in RTL Simulation Runtime. |
ICTC |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Nayoung Kwon, Daejin Park |
Lightweighted Shallow CTS Techniques for Checking Clock Tree Synthesizable Paths and Optimizing Clock Tree in RTL Design Time. |
ICTC |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Tobias Jauch, Alex Wezel, Mohammad Rahmani Fadiheh, Philipp Schmitz, Sayak Ray, Jason M. Fung, Christopher W. Fletcher, Dominik Stoffel, Wolfgang Kunz |
Secure-by-Construction Design Methodology for CPUs: Implementing Secure Speculation on the RTL. |
ICCAD |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Yingjie Li, Mingju Liu, Alan Mishchenko, Cunxi Yu |
Invited Paper: Verilog-to-PyG - A Framework for Graph Learning and Augmentation on RTL Designs. |
ICCAD |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Wenji Fang, Yao Lu, Shang Liu, Qijun Zhang, Ceyu Xu, Lisa Wu Wills, Hongce Zhang, Zhiyao Xie |
MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design. |
ICCAD |
2023 |
DBLP DOI BibTeX RDF |
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