Search results for "SoC"

Hits ?▲	Authors	Title	Venue	Year	Link
26	Davide Sabena, Matteo Sonza Reorda, Luca Sterpone	Partition-Based Faults Diagnosis of a VLIW Processor.	VLSI-SoC (Selected Papers)	2013	DBLP DOI BibTeX RDF
26	Nathaniel A. Conos, Saro Meguerdichian, Miodrag Potkonjak	Gate Sizing Under Uncertainty.	VLSI-SoC (Selected Papers)	2013	DBLP DOI BibTeX RDF
26	Andreas Minwegen, Dominik Auras, Gerd Ascheid	A Flexible ASIC for Time-Domain Decision-Directed Channel Estimation in MIMO-OFDM Systems.	VLSI-SoC (Selected Papers)	2013	DBLP DOI BibTeX RDF
26	Seogoo Lee, Andreas Gerstlauer	Fine Grain Precision Scaling for Datapath Approximations in Digital Signal Processing Systems.	VLSI-SoC (Selected Papers)	2013	DBLP DOI BibTeX RDF
26	Kyprianos Papadimitriou, Sotiris Thomas, Apostolos Dollas	An FPGA-Based Real-Time System for 3D Stereo Matching, Combining Absolute Differences and Census with Aggregation and Belief Propagation.	VLSI-SoC (Selected Papers)	2013	DBLP DOI BibTeX RDF
26	Mohand Bentobache, Ahcène Bounceur, Reinhardt Euler, Salvador Mir, Yann Kieffer	Minimizing Test Frequencies for Linear Analog Circuits: New Models and Efficient Solution Methods.	VLSI-SoC (Selected Papers)	2013	DBLP DOI BibTeX RDF
26	Ali Fazli Yeknami, Atila Alvandpour	Low-Power Low-Voltage ΔΣ Modulator Using Switched-Capacitor Passive Filters.	VLSI-SoC (Selected Papers)	2013	DBLP DOI BibTeX RDF
26	Michael Schaffner, Pascal A. Hager, Lukas Cavigelli, Z. Fang, Pierre Greisen, Frank K. Gürkaynak, Aljoscha Smolic, Hubert Kaeslin, Luca Benini	A Complete Real-Time Feature Extraction and Matching System Based on Semantic Kernels Binarized.	VLSI-SoC (Selected Papers)	2013	DBLP DOI BibTeX RDF
26	Kosuke Oshima, Takeshi Matsumoto, Masahiro Fujita	Debugging Methods Through Identification of Appropriate Functions for Internal Gates.	VLSI-SoC (Selected Papers)	2013	DBLP DOI BibTeX RDF
26	Sk Subidh Ali, Samah Mohamed Saeed, Ozgur Sinanoglu, Ramesh Karri	New Scan-Based Attack Using Only the Test Mode and an Input Corruption Countermeasure.	VLSI-SoC (Selected Papers)	2013	DBLP DOI BibTeX RDF
26	José L. Ayala, David Atienza Alonso, Ricardo Reis 0001 (eds.)	VLSI-SoC: Forward-Looking Trends in IC and Systems Design - 18th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2010, Madrid, Spain, September 27-29, 2010, Revised Selected Papers	VLSI-SoC (Selected Papers)	2012	DBLP DOI BibTeX RDF
26	Salvador Mir, Chi-Ying Tsui, Ricardo Reis 0001, Oliver C. S. Choy (eds.)	VLSI-SoC: Advanced Research for Systems on Chip - 19th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2011, Hong Kong, China, October 3-5, 2011, Revised Selected Papers	VLSI-SoC (Selected Papers)	2012	DBLP DOI BibTeX RDF
26	Giulia Beanato, Igor Loi, Giovanni De Micheli, Yusuf Leblebici, Luca Benini	Configurable Low-Latency Interconnect for Multi-core Clusters.	VLSI-SoC (Selected Papers)	2012	DBLP DOI BibTeX RDF
26	Michael Muehlberghuber, Christoph Keller, Frank K. Gürkaynak, Norbert Felber	FPGA-Based High-Speed Authenticated Encryption System.	VLSI-SoC (Selected Papers)	2012	DBLP DOI BibTeX RDF
26	Pierre Greisen, Michael Schaffner, Danny Luu, Val Mikos, Simon Heinzle, Frank K. Gürkaynak, Aljoscha Smolic	Spatially-Varying Image Warping: Evaluations and VLSI Implementations.	VLSI-SoC (Selected Papers)	2012	DBLP DOI BibTeX RDF
26	Zhibin Xiao, Bevan M. Baas	A Hexagonal Processor and Interconnect Topology for Many-Core Architecture with Dense On-Chip Networks.	VLSI-SoC (Selected Papers)	2012	DBLP DOI BibTeX RDF
26	Andy Motten, Luc Claesen, Yun Pan	Trinocular Stereo Vision Using a Multi Level Hierarchical Classification Structure.	VLSI-SoC (Selected Papers)	2012	DBLP DOI BibTeX RDF
26	Neil Di Spigna, Daniel Schinke, Srikant Jayanti, Veena Misra, Paul D. Franzon	Simulation and Experimental Characterization of a Unified Memory Device with Two Floating-Gates.	VLSI-SoC (Selected Papers)	2012	DBLP DOI BibTeX RDF
26	Jeremy Constantin, Ahmed Yasir Dogan, Oskar Andersson, Pascal Andreas Meinerzhagen, Joachim Neves Rodrigues, David Atienza, Andreas Burg	An Ultra-Low-Power Application-Specific Processor with Sub-VT Memories for Compressed Sensing.	VLSI-SoC (Selected Papers)	2012	DBLP DOI BibTeX RDF
26	Seokjoong Kim, Matthew R. Guthaus	SEU-Aware Low-Power Memories Using a Multiple Supply Voltage Array Architecture.	VLSI-SoC (Selected Papers)	2012	DBLP DOI BibTeX RDF
26	Qiuling Zhu, Larry T. Pileggi, Franz Franchetti	A Smart Memory Accelerated Computed Tomography Parallel Backprojection.	VLSI-SoC (Selected Papers)	2012	DBLP DOI BibTeX RDF
26	Davide Sabena, Luca Sterpone, Matteo Sonza Reorda	On the Automatic Generation of Software-Based Self-Test Programs for Functional Test and Diagnosis of VLIW Processors.	VLSI-SoC (Selected Papers)	2012	DBLP DOI BibTeX RDF
26	Anelise Kologeski, Caroline Concatto, Fernanda Lima Kastensmidt, Luigi Carro	Fault-Tolerant Techniques to Manage Yield and Power Constraints in Network-on-Chip Interconnections.	VLSI-SoC (Selected Papers)	2012	DBLP DOI BibTeX RDF
26	Farhad Alibeygi Parsan, Scott C. Smith	CMOS Implementation of Threshold Gates with Hysteresis.	VLSI-SoC (Selected Papers)	2012	DBLP DOI BibTeX RDF
26	Jürgen Becker 0001, Marcelo O. Johann, Ricardo Reis 0001 (eds.)	VLSI-SoC: Technologies for Systems Integration - 17th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2009, Florianópolis, Brazil, October 12-14, 2009, Revised Selected Papers	VLSI-SoC	2011	DBLP DOI BibTeX RDF
26	Levent Aksoy, Eduardo A. C. da Costa, Paulo F. Flores, José Monteiro 0001	Multiplierless Design of Linear DSP Transforms.	VLSI-SoC (Selected Papers)	2011	DBLP DOI BibTeX RDF
26	Toshiyuki Tsuchiya, Hiroyuki Tokusaki, Yoshikazu Hirai, Koji Sugano, Osamu Tabata	Self-dependent Equivalent Circuit Modeling of Electrostatic Comb Transducers for Integrated MEMS.	VLSI-SoC (Selected Papers)	2011	DBLP DOI BibTeX RDF
26	Huan Chen 0001, João Marques-Silva 0001	Improvements to Satisfiability-Based Boolean Function Bi-Decomposition.	VLSI-SoC (Selected Papers)	2011	DBLP DOI BibTeX RDF
26	J. Gerardo García-Sánchez, José M. de la Rosa 0001	Efficient Multi-rate Hybrid Continuous-Time/Discrete-Time Cascade 2-2 Sigma-Delta Modulators for Wideband Telecom.	VLSI-SoC (Selected Papers)	2011	DBLP DOI BibTeX RDF
26	Xiaojin Zhao, Amine Bermak, Farid Boussaïd	A Low Cost CMOS Polarimetric Ophthalmoscope Scheme for Cerebral Malaria Diagnostics.	VLSI-SoC (Selected Papers)	2011	DBLP DOI BibTeX RDF
26	Xin Ming, Ze-kun Zhou, Bo Zhang 0027	A Low-Power Ultra-Fast Capacitor-Less LDO with Advanced Dynamic Push-Pull Techniques.	VLSI-SoC (Selected Papers)	2011	DBLP DOI BibTeX RDF
26	Brendan Mullane, Vincent O'Brien	A 100dB SFDR 0.5V pk-pk Band-Pass DAC Implemented on a Low Voltage CMOS Process.	VLSI-SoC (Selected Papers)	2011	DBLP DOI BibTeX RDF
26	Ernesto Sánchez 0001, Matteo Sonza Reorda, Alberto Paolo Tonda	On the Functional Test of Branch Prediction Units Based on the Branch History Table Architecture.	VLSI-SoC (Selected Papers)	2011	DBLP DOI BibTeX RDF
26	Wing-Hung Ki, Yan Lu 0002, Feng Su, Chi-Ying Tsui	Analysis and Design Strategy of On-Chip Charge Pumps for Micro-power Energy Harvesting Applications.	VLSI-SoC (Selected Papers)	2011	DBLP DOI BibTeX RDF
26	Ji Kong, Peilin Liu	A novel reconfigurable scratchpad memory for audio applications on cost-effective SoC.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
26	Luc Claesen, Peter Vandoren, Tom Van Laerhoven, Andy Motten, Domien Nowicki, Tom De Weyer, Frank Van Reeth, Eddy Flerackers	Smart camera SoC system for interactive real-time real-brush based digital painting systems.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
26	Andy Motten, Luc Claesen	A binary adaptable window SoC architecture for a stereo vision based depth field processor.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
26	Gabriel Caffarena, Angel Fernandez Herrero, Juan A. López, Carlos Carreras	Fast Fixed-Point Optimization of DSP Algorithms.	VLSI-SoC (Selected Papers)	2010	DBLP DOI BibTeX RDF
26	Rafik Khereddine, Louay Abdallah, Emmanuel Simeu, Salvador Mir, Fabio Cenni	Adaptive Logical Control of RF LNA Performances for Efficient Energy Consumption.	VLSI-SoC (Selected Papers)	2010	DBLP DOI BibTeX RDF
26	Tsung-Yi Ho, Sheng-Hung Liu	Fast Legalization for Standard Cell Placement with Simultaneous Wirelength and Displacement Minimization.	VLSI-SoC (Selected Papers)	2010	DBLP DOI BibTeX RDF
26	Eliyah Kilada, Kenneth S. Stevens	Design and Verification of Lazy and Hybrid Implementations of the SELF Protocol.	VLSI-SoC (Selected Papers)	2010	DBLP DOI BibTeX RDF
26	Maher Jridi, Ayman Alfalou	Joint Optimization of Low-Power DCT Architecture and Efficient Quantization Technique for Embedded Image Compression.	VLSI-SoC (Selected Papers)	2010	DBLP DOI BibTeX RDF
26	Aaron V. T. Do, Chirn Chye Boon, Manthena Vamshi Krishna, Manh Anh Do, Kiat Seng Yeo	A 1-V CMOS Ultralow-Power Receiver Front End for the IEEE 802.15.4 Standard Using Tuned Passive Mixer Output Pole.	VLSI-SoC (Selected Papers)	2010	DBLP DOI BibTeX RDF
26	Christoph Studer, Markus Wenk, Andreas Burg	VLSI Implementation of Hard- and Soft-Output Sphere Decoding for Wide-Band MIMO Systems.	VLSI-SoC (Selected Papers)	2010	DBLP DOI BibTeX RDF
26	Luc Claesen, Peter Vandoren, Tom Van Laerhoven, Andy Motten, Fabian Di Fiore, Frank Van Reeth, Jing Liao 0001, Jinhui Yu	Smart Camera System-on-Chip Architecture for Real-Time Brush Based Interactive Painting Systems.	VLSI-SoC (Selected Papers)	2010	DBLP DOI BibTeX RDF
26	Christian Benkeser, Qiuting Huang	Design and Optimization of a Digital Baseband Receiver ASIC for GSM/EDGE.	VLSI-SoC (Selected Papers)	2010	DBLP DOI BibTeX RDF
26	Rémi Busseuil, Gabriel Marchesan Almeida, Luciano Ost, Sameer Varyani, Gilles Sassatelli, Michel Robert	Adaptation Strategies in Multiprocessors System on Chip.	VLSI-SoC (Selected Papers)	2010	DBLP DOI BibTeX RDF
26	Oscar Alonso, Ángel Diéguez	Control Electronics Integration toward Endoscopic Capsule Robot Performing Legged Locomotion and Illumination.	VLSI-SoC (Selected Papers)	2010	DBLP DOI BibTeX RDF
26	Hailong Jiao, Volkan Kursun	Tri-mode Operation for Noise Reduction and Data Preservation in Low-Leakage Multi-Threshold CMOS Circuits.	VLSI-SoC (Selected Papers)	2010	DBLP DOI BibTeX RDF
26	Manthena Vamshi Krishna, Xuan Jie, Manh Anh Do, Chirn Chye Boon, Kiat Seng Yeo, Aaron V. T. Do	A 1.8-V 3.6-mW 2.4-GHz Fully Integrated CMOS Frequency Synthesizer for the IEEE 802.15.4.	VLSI-SoC (Selected Papers)	2010	DBLP DOI BibTeX RDF
26	Oussama Elissati, Sébastien Rieubon, Eslam Yahya, Laurent Fesquet	Self-Timed Rings: A Promising Solution for Generating High-Speed High-Resolution Low-Phase Noise Clocks.	VLSI-SoC (Selected Papers)	2010	DBLP DOI BibTeX RDF
26	Alzemiro Henrique Lucas da Silva, Alexandre M. Amory, Fernando Gehm Moraes	Crosstalk Fault Tolerant NoC: Design and Evaluation.	VLSI-SoC	2009	DBLP DOI BibTeX RDF
26	Ian O'Connor, Junchen Liu, Kotb Jabeur, Nataliya Yakymets, Renaud Daviot, David Navarro, Pierre-Emmanuel Gaillardon, Fabien Clermidy, Maimouna Amadou, Gabriela Nicolescu	Emerging Technologies and Nanoscale Computing Fabrics.	VLSI-SoC	2009	DBLP DOI BibTeX RDF
26	António Gusmão, Luís Miguel Silveira, José Monteiro 0001	Power Macro-Modeling Using an Iterative LS-SVM Method.	VLSI-SoC	2009	DBLP DOI BibTeX RDF
26	Dieison Antonello Deprá, Sergio Bampi	Techniques for Architecture Design for Binary Arithmetic Decoder Engines Based on Bitstream Flow Analysis.	VLSI-SoC	2009	DBLP DOI BibTeX RDF
26	Amine Dehbaoui, Victor Lomné, Philippe Maurine, Lionel Torres, Michel Robert	Enhancing Electromagnetic Attacks Using Spectral Coherence Based Cartography.	VLSI-SoC	2009	DBLP DOI BibTeX RDF
26	Yann Oddos, Katell Morin-Allory, Dominique Borrione	From Assertion-Based Verification to Assertion-Based Synthesis.	VLSI-SoC	2009	DBLP DOI BibTeX RDF
26	Ayse Kivilcim Coskun, José L. Ayala, David Atienza, Tajana Simunic Rosing	Thermal Modeling and Management of Liquid-Cooled 3D Stacked Architectures.	VLSI-SoC	2009	DBLP DOI BibTeX RDF
26	Gustavo Girão, Daniel Barcelos, Flávio Rech Wagner	Performance and Energy Evaluation of Memory Organizations in NoC-Based MPSoCs under Latency and Task Migration.	VLSI-SoC	2009	DBLP DOI BibTeX RDF
26	Sergio Bampi, Ricardo Reis 0001	Challenges and Emerging Technologies for System Integration beyond the End of the Roadmap of Nano-CMOS.	VLSI-SoC	2009	DBLP DOI BibTeX RDF
26	Petru Bogdan Bacinschi, Manfred Glesner	A Multistep Extrapolated S-Parameter Model for Arbitrary On-Chip Interconnect Structures.	VLSI-SoC	2009	DBLP DOI BibTeX RDF
26	Ricardo Augusto da Luz Reis, Adam Osseiran, Hans-Jörg Pfleiderer (eds.)	VLSI-SoC: From Systems To Silicon, Proceedings of IFIP TC 10, WG 10.5, Thirteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2005), October 17-19, 2005, Perth, Australia	VLSI-SoC	2007	DBLP BibTeX RDF
26	Brian Cody, Justin Madigan, Spencer MacDonald, Kenneth W. Hsu	High speed SOC design for blowfish cryptographic algorithm.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
26	Julien Dalmasso, Marie-Lise Flottes, Bruno Rouzeyre	Compression-based SoC Test Infrastructures.	VLSI-SoC (Selected Papers)	2007	DBLP DOI BibTeX RDF
26	Manfred Glesner, Ricardo Augusto da Luz Reis, Leandro Soares Indrusiak, Vincent John Mooney III, Hans Eveking (eds.)	VLSI-SOC: From Systems to Chips - IFIP TC 10/ WG 10.5 Twelfth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2003), December 1-3, 2003, Darmstadt, Germany	VLSI-SoC (Selected Papers)	2006	DBLP DOI BibTeX RDF
26	Jacques Benkowski	The system is really in the SoC : new investment opportunities.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
26	Paul D. Franzon, David Nackashi, Christian Amsinck, Neil Di Spigna, Sachin Sonkusale	Molecular Electronics - Devices and Circuits Technology.	VLSI-SoC	2005	DBLP DOI BibTeX RDF
26	Achraf Dhayni, Salvador Mir, Libor Rufer, Ahcène Bounceur	On-chip Pseudorandom Testing for Linear and Nonlinear MEMS.	VLSI-SoC	2005	DBLP DOI BibTeX RDF
26	Leonardo Londero de Oliveira, Cristiano Santos, Daniel Lima Ferrão, Eduardo A. C. da Costa, José Monteiro 0001, João Baptista dos Santos Martins, Sergio Bampi, Ricardo Augusto da Luz Reis	A Comparison of Layout Implementations of Pipelined and Non-Pipelined Signed Radix-4 Array Multiplier and Modified Booth Multiplier Architectures.	VLSI-SoC	2005	DBLP DOI BibTeX RDF
26	Thilo Pionteck, Thomas Stiefmeier, Thorsten Staake, Manfred Glesner	On The Design of A Dynamically Reconfigurable Function-Unit for Error Detection and Correction.	VLSI-SoC	2005	DBLP DOI BibTeX RDF
26	Cristiano Lazzari, Lorena Anghel, Ricardo Reis 0001	A Transistor Placement Technique Using Genetic Algorithm and Analytical Programming.	VLSI-SoC	2005	DBLP DOI BibTeX RDF
26	Alberto Donato, Fabrizio Ferrandi, Massimo Redaelli, Marco D. Santambrogio, Donatella Sciuto	Caronte: A methodology for the Implementation of Partially dynamically Self-Reconfiguring Systems on FPGA Platforms.	VLSI-SoC	2005	DBLP DOI BibTeX RDF
26	Jun-Cheol Park, Vincent John Mooney III	Pareto Points in SRAM Design Using the Sleepy Stack Approach.	VLSI-SoC	2005	DBLP DOI BibTeX RDF
26	Milos Stanisavljevic, Alexandre Schmid, Yusuf Leblebici	A Methodology for Reliability Enhancement of Nanometer-Scale Digital Systems Based on a-priori Functional Fault- Tolerance Analysis.	VLSI-SoC	2005	DBLP DOI BibTeX RDF
26	César A. M. Marcon, José Carlos S. Palma, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Altamiro Amadeu Susin, Ricardo Augusto da Luz Reis	Modeling the Traffic Effect for the Application Cores Mapping Problem onto NoCs.	VLSI-SoC	2005	DBLP DOI BibTeX RDF
26	Shankar Mahadevan, Federico Angiolini, Jens Sparsø, Luca Benini, Jan Madsen	A Traffic Injection Methodology with Support for System-Level Synchronization.	VLSI-SoC	2005	DBLP DOI BibTeX RDF
26	G. Fraidy Bouesse, Marc Renaudin, Gilles Sicard	Improving DPA Resistance of Quasi Delay Insensitive Circuits Using Randomly Time-shifted Acknowledgment Signals.	VLSI-SoC	2005	DBLP DOI BibTeX RDF
26	Bertrand Folco, Vivian Brégier, Laurent Fesquet, Marc Renaudin	Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits.	VLSI-SoC	2005	DBLP DOI BibTeX RDF
26	Markus Koester, Heiko Kalte, Mario Porrmann, Ulrich Rückert 0001	Defragmentation Algorithms for Partially Reconfigurable Hardware.	VLSI-SoC	2005	DBLP DOI BibTeX RDF
26	Chul Kim, A. M. Rassau, Stefan Lachowicz, Saeid Nooshabadi, Kamran Eshraghian	3D-SoftChip: A Novel 3D Vertically Integrated Adaptive Computing System.	VLSI-SoC	2005	DBLP DOI BibTeX RDF
26	Rüdiger Ebendt, Rolf Drechsler	Exact BDD Minimization for Path-Related Objective Functions.	VLSI-SoC	2005	DBLP DOI BibTeX RDF
26	Jerome Quartana, Laurent Fesquet, Marc Renaudin	Modular Asynchronous Network-on-Chip: Application to GALS Systems Rapid Prototyping.	VLSI-SoC	2005	DBLP DOI BibTeX RDF
26	Nabil Badereddine, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel, Christian Landrault	Scan Cell Reordering for Peak Power Reduction during Scan Test Cycles.	VLSI-SoC	2005	DBLP DOI BibTeX RDF
26	Muhsen Aljada, Kamal E. Alameh, Adam Osseiran, Khalid Al-Begain	A Novel MicroPhotonic Structure for Optical Header Recognition.	VLSI-SoC	2005	DBLP DOI BibTeX RDF
26	João M. S. Silva, L. Miguel Silveira	Issues in Model Reduction of Power Grids.	VLSI-SoC	2005	DBLP DOI BibTeX RDF
26	Daniel Mesquita, Jean-Denis Techer, Lionel Torres, Michel Robert, Guy Cathébras, Gilles Sassatelli, Fernando Gehm Moraes	Current Mask Generation: an Analog Circuit to Thwart DPA Attacks.	VLSI-SoC	2005	DBLP DOI BibTeX RDF
26	Youngchul Cho, Ganghee Lee, Kiyoung Choi, Sungjoo Yoo, Nacer-Eddine Zergainoh	Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design.	Embedded Software for SoC	2003	DBLP DOI BibTeX RDF
26	Sungjoo Yoo, Ahmed Amine Jerraya	Introduction to Hardware Abstraction Layers for SoC.	Embedded Software for SoC	2003	DBLP DOI BibTeX RDF
26	Imed Moussa, Thierry Grellier, Giang Nguyen	Exploring SW Performance Using SoC Transaction-Level Modeling.	Embedded Software for SoC	2003	DBLP DOI BibTeX RDF
26	Shervin Sharifi, Mohammad Hosseinabady, Zainalabedin Navabi	Selective Trigger Scan Architecture for Reducing Power, Time and Data Volume in SoC Testing.	VLSI-SOC	2003	DBLP BibTeX RDF
26	Timm Ostermann, Wolfgang Gut, Christian Bacher, Bernd Deutschmann	Measures to Reduce the Electromagnetic Emission of a SoC.	VLSI-SOC	2003	DBLP BibTeX RDF
26	Michael S. McCorquodale, Eric D. Marsman, Robert M. Senger, Fadi H. Gebara, Richard B. Brown	Microsystem and SoC Design with UMIPS.	VLSI-SOC	2003	DBLP BibTeX RDF
26	Hans-Joachim Stolberg, Mladen Berekovic, Lars Friebe, Sören Moch, Mark Bernd Kulaczewski, Peter Pirsch	HiBRID-SoC: A Multi-Core System-on-Chip Architecture for Multimedia Signal Processing.	VLSI-SOC	2003	DBLP BibTeX RDF
26	Wei Zou, Chris Chu, Sudhakar M. Reddy, Irith Pomeranz	Optimizing SOC Test Resources using Dual Sequences.	VLSI-SOC	2003	DBLP BibTeX RDF
26	Zahid Khan, Tughrul Arslan, Ahmet T. Erdogan	Crosstalk Immune Coding from Area and Power Perspective for high performance AMBA based SoC systems.	VLSI-SOC	2003	DBLP BibTeX RDF
26	Arkadiy Morgenshtein, Michael Moreinis, Israel A. Wagner, Avinoam Kolodny	Logic Gates as Repeaters (LGR) for Timing Optimization of SoC Interconnects.	VLSI-SOC	2003	DBLP BibTeX RDF
26	Jürgen Becker 0001, Alexander Thomas, Maik Scheer	Asynchronous Integration of Coarse-Grained Reconfigurable XPP-Arrays Into Pipelined Risc Processor Datapath.	VLSI-SoC (Selected Papers)	2003	DBLP DOI BibTeX RDF
26	Alexandre M. Amory, Leandro A. Oliveira, Fernando Gehm Moraes	Software-Based Test for Nonprogrammable Cores in Bus-Based System-On-Chip Architectures.	VLSI-SoC (Selected Papers)	2003	DBLP DOI BibTeX RDF
26	Thilo Pionteck, Lukusa D. Kabulepa, Manfred Glesner	Exploring the Capabilities of Reconfigurable Hardware for OFDM-Based Wlans.	VLSI-SoC (Selected Papers)	2003	DBLP DOI BibTeX RDF
26	Vijay Degalahal, Rajaraman Ramanarayanan, Narayanan Vijaykrishnan, Yuan Xie 0001, Mary Jane Irwin	Effect of Power Optimizations on Soft Error Rate.	VLSI-SoC (Selected Papers)	2003	DBLP DOI BibTeX RDF