Search results for "cmps"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
11	Nevin Kirman, Meyrem Kirman, Rajeev K. Dokania, José F. Martínez, Alyssa B. Apsel, Matthew A. Watkins, David H. Albonesi	On-Chip Optical Technology in Future Bus-Based Multicore Designs.	IEEE Micro	2007	DBLP DOI BibTeX RDF	optical technology, snoopy bus, chip multiprocessor, on-chip interconnect
11	Vassos Soteriou, Noel Eisley, Hangsheng Wang, Bin Li 0018, Li-Shiuan Peh	Polaris: A System-Level Roadmapping Toolchain for On-Chip Interconnection Networks.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
11	Michael Gschwind	The Cell Broadband Engine: Exploiting Multiple Levels of Parallelism in a Chip Multiprocessor.	Int. J. Parallel Program.	2007	DBLP DOI BibTeX RDF	compute-transfer parallelism, multi-level application parallelism, Chip multiprocessor, Cell Broadband Engine, heterogeneous chip multiprocessor
11	Niti Madan, Rajeev Balasubramonian	Power Efficient Approaches to Redundant Multithreading.	IEEE Trans. Parallel Distributed Syst.	2007	DBLP DOI BibTeX RDF	redundant multi-threading (RMT), dynamic frequency scaling, Reliability, power, soft errors, transient faults, heterogeneous chip multiprocessors
11	Vassos Soteriou, Noel Eisley, Li-Shiuan Peh	Software-directed power-aware interconnection networks.	ACM Trans. Archit. Code Optim.	2007	DBLP DOI BibTeX RDF	Software-directed power reduction, simulation, interconnection networks, dynamic voltage scaling, on-chip networks, communication links
11	Evgeny Bolotin, Zvika Guz, Israel Cidon, Ran Ginosar, Avinoam Kolodny	The Power of Priority: NoC Based Distributed Cache Coherency.	NOCS	2007	DBLP DOI BibTeX RDF
11	Kyueun Yi, Jean-Luc Gaudiot	Architectural Implications of Cache Coherence Protocols with Network Applications on Chip MultiProcessors.	NPC	2007	DBLP DOI BibTeX RDF
11	Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero	MLP-Aware Dynamic Cache Partitioning.	PACT	2007	DBLP DOI BibTeX RDF
11	Alexandra Fedorova, Margo I. Seltzer, Michael D. Smith 0001	Improving Performance Isolation on Chip Multiprocessors via an Operating System Scheduler.	PACT	2007	DBLP DOI BibTeX RDF
11	Christopher LaFrieda, Engin Ipek, José F. Martínez, Rajit Manohar	Utilizing Dynamically Coupled Cores to Form a Resilient Chip Multiprocessor.	DSN	2007	DBLP DOI BibTeX RDF
11	Njuguna Njoroge, Jared Casper, Sewook Wee, Yuriy Teslyar, Daxia Ge, Christos Kozyrakis, Kunle Olukotun	ATLAS: a chip-multiprocessor with transactional memory support.	DATE	2007	DBLP DOI BibTeX RDF
11	Meeta Sharma Gupta, Jarod L. Oatley, Russ Joseph, Gu-Yeon Wei, David M. Brooks	Understanding voltage variations in chip multiprocessors using a distributed power-delivery network.	DATE	2007	DBLP DOI BibTeX RDF
11	Changkyu Kim, Simha Sethumadhavan, M. S. Govindan, Nitya Ranganathan, Divya Gulati, Doug Burger, Stephen W. Keckler	Composable Lightweight Processors.	MICRO	2007	DBLP DOI BibTeX RDF
11	Cheng Wang 0013, Ho-Seop Kim, Youfeng Wu, Victor Ying	Compiler-Managed Software-based Redundant Multi-Threading for Transient Fault Detection.	CGO	2007	DBLP DOI BibTeX RDF
11	Alaa R. Alameldeen, David A. Wood 0001	Interactions Between Compression and Prefetching in Chip Multiprocessors.	HPCA	2007	DBLP DOI BibTeX RDF
11	Ricardo Fernández Pascual, José M. García 0001, Manuel E. Acacio, José Duato	A Low Overhead Fault Tolerant Coherence Protocol for CMP Architectures.	HPCA	2007	DBLP DOI BibTeX RDF
11	Jörg-Christian Niemann, Christian Liß, Mario Porrmann, Ulrich Rückert 0001	A Multiprocessor Cache for Massively Parallel SoC Architectures.	ARCS	2007	DBLP DOI BibTeX RDF
11	Andrew Over, Bill Clarke, Peter E. Strazdins	A Comparison of Two Approaches to Parallel Simulation of Multiprocessors.	ISPASS	2007	DBLP DOI BibTeX RDF	speedup analysis, Sparc Sulima, UltraSPARC IIICu-based multiprocessor systems, careful locking, simulation time quantum, serial simulation, load-balancing, parallel simulation, parallel discrete event simulation, interconnect model, NAS parallel benchmarks
11	Domingo Benitez, Juan C. Moure, Dolores Rexachs, Emilio Luque	Adaptive L2 Cache for Chip Multiprocessors.	Euro-Par Workshops	2007	DBLP DOI BibTeX RDF
11	Srinivas Vadlamani, Stephen F. Jenks	Architectural Considerations for Efficient Software Execution on Parallel Microprocessors.	IPDPS	2007	DBLP DOI BibTeX RDF
11	Engin Ipek, Meyrem Kirman, Nevin Kirman, José F. Martínez	A Reconfigurable Chip Multiprocessor Architecture to Accommodate Software Diversity.	IPDPS	2007	DBLP DOI BibTeX RDF
11	Martin Karlsson, Erik Hagersten	Conserving Memory Bandwidth in Chip Multiprocessors with Runahead Execution.	IPDPS	2007	DBLP DOI BibTeX RDF
11	Jichuan Chang, Gurindar S. Sohi	Cooperative cache partitioning for chip multiprocessors.	ICS	2007	DBLP DOI BibTeX RDF	cooperative cache partitioning, multiple time-sharing partitions, QoS, fairness, CMP
11	Ruibin Xu, Rami G. Melhem, Daniel Mossé	Energy-Aware Scheduling for Streaming Applications on Chip Multiprocessors.	RTSS	2007	DBLP DOI BibTeX RDF
11	Amit Kumar 0002, Partha Kundu, Arvind P. Singh, Li-Shiuan Peh, Niraj K. Jha	A 4.6Tbits/s 3.6GHz single-cycle NoC router with a novel switch allocator in 65nm CMOS.	ICCD	2007	DBLP DOI BibTeX RDF
11	Antonio Flores, Juan L. Aragón, Manuel E. Acacio	Sim-PowerCMP: A Detailed Simulator for Energy Consumption Analysis in Future Embedded CMP Architectures.	AINA Workshops (1)	2007	DBLP DOI BibTeX RDF
11	Nabil Hasasneh, Ian M. Bell, Chris R. Jesshope	High Level Modelling and Design For a Microthreaded Scheduler to Support Microgrids.	AICCSA	2007	DBLP DOI BibTeX RDF
11	Ali-Reza Adl-Tabatabai, Christos Kozyrakis, Bratin Saha	Transactional programming in a multi-core environment.	PPoPP	2007	DBLP DOI BibTeX RDF	parallel programming, transactional memory, atomicity, hardware architecture
11	Christopher J. Hughes, Radek Grzeszczuk, Eftychios Sifakis, Daehyun Kim 0001, Sanjeev Kumar, Andrew Selle, Jatin Chhugani, Matthew J. Holliman, Yen-Kuang Chen	Physical simulation for animation and visual effects: parallelization and characterization for chip multiprocessors.	ISCA	2007	DBLP DOI BibTeX RDF	parallelization, CMP, characterization, physical simulation
11	Pablo Abad Fidalgo, Valentin Puente, José-Ángel Gregorio, Pablo Prieto	Rotary router: an efficient architecture for CMP interconnection networks.	ISCA	2007	DBLP DOI BibTeX RDF	interconnection networks, router architecture, chip multi-processors
11	Jacob Leverich, Hideho Arakida, Alex Solomatnikov, Amin Firoozshahian, Mark Horowitz, Christos Kozyrakis	Comparing memory systems for chip multiprocessors.	ISCA	2007	DBLP DOI BibTeX RDF	streaming memory, parallel programming, chip multiprocessors, locality optimizations, coherent caches
11	Engin Ipek, Meyrem Kirman, Nevin Kirman, José F. Martínez	Core fusion: accommodating software diversity in chip multiprocessors.	ISCA	2007	DBLP DOI BibTeX RDF	chip multiprocessors, reconfigurable architectures, software diversity
11	Jeffery A. Brown, Rakesh Kumar 0002, Dean M. Tullsen	Proximity-aware directory-based coherence for multi-core processor architectures.	SPAA	2007	DBLP DOI BibTeX RDF	chip multiprocessors, coherence
11	Matteo Monchiero, Gianluca Palermo, Cristina Silvano, Oreste Villa	Efficient Synchronization for Embedded On-Chip Multiprocessors.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
11	Francisco J. Villa, Manuel E. Acacio, José M. García 0001	On the Evaluation of Dense Chip-Multiprocessor Architectures.	ICSAMOS	2006	DBLP DOI BibTeX RDF
11	Vassos Soteriou, Hangsheng Wang, Li-Shiuan Peh	A Statistical Traffic Model for On-Chip Interconnection Networks.	MASCOTS	2006	DBLP DOI BibTeX RDF
11	Nevin Kirman, Meyrem Kirman, Rajeev K. Dokania, José F. Martínez, Alyssa B. Apsel, Matthew A. Watkins, David H. Albonesi	Leveraging Optical Technology in Future Bus-based Chip Multiprocessors.	MICRO	2006	DBLP DOI BibTeX RDF
11	Kyle J. Nesbit, Nidhi Aggarwal, James Laudon, James E. Smith 0001	Fair Queuing Memory Systems.	MICRO	2006	DBLP DOI BibTeX RDF
11	Keshavan Varadarajan, S. K. Nandy 0001, Vishal Sharda, Bharadwaj Amrutur, Ravi R. Iyer 0001, Srihari Makineni, Donald Newell	Molecular Caches: A caching structure for dynamic creation of application-specific Heterogeneous cache regions.	MICRO	2006	DBLP DOI BibTeX RDF
11	Jian Li 0059, José F. Martínez	Dynamic power-performance adaptation of parallel computation on chip multiprocessors.	HPCA	2006	DBLP DOI BibTeX RDF
11	David A. Penry, Daniel Fay, David Hodgdon, Ryan Wells, Graham Schelle, David I. August, Dan Connors	Exploiting parallelism and structure to accelerate the simulation of chip multi-processors.	HPCA	2006	DBLP DOI BibTeX RDF
11	Venkatesan Packirisamy, Shengyue Wang, Antonia Zhai, Wei-Chung Hsu, Pen-Chung Yew	Supporting Speculative Multithreading on Simultaneous Multithreaded Processors.	HiPC	2006	DBLP DOI BibTeX RDF
11	Haakon Dybdahl, Per Stenström, Lasse Natvig	A Cache-Partitioning Aware Replacement Policy for Chip Multiprocessors.	HiPC	2006	DBLP DOI BibTeX RDF
11	Gregory Buehrer, Yen-Kuang Chen, Srinivasan Parthasarathy 0001, Anthony D. Nguyen, Amol Ghoting, Daehyun Kim 0001	Efficient pattern mining on shared memory systems: implications for chip multiprocessor architectures.	Memory System Performance and Correctness	2006	DBLP DOI BibTeX RDF
11	Victor Luchangco, Daniel Nussbaum, Nir Shavit	A Hierarchical CLH Queue Lock.	Euro-Par	2006	DBLP DOI BibTeX RDF
11	Ali El-Moursy, Rajeev Garg, David H. Albonesi, Sandhya Dwarkadas	Compatible phase co-scheduling on a CMP of multi-threaded processors.	IPDPS	2006	DBLP DOI BibTeX RDF
11	Blair Fort, Davor Capalija, Zvonko G. Vranesic, Stephen Dean Brown	A Multithreaded Soft Processor for SoPC Area Reduction.	FCCM	2006	DBLP DOI BibTeX RDF
11	Noel Eisley, Vassos Soteriou, Li-Shiuan Peh	High-level power analysis for multi-core chips.	CASES	2006	DBLP DOI BibTeX RDF	simulation, chip multiprocessor (CMP), multi-core, power analysis, system-on-a-chip (SoC)
11	Pavlos Petoumenos, Georgios Keramidas, Håkan Zeffer, Stefanos Kaxiras, Erik Hagersten	Modeling Cache Sharing on Chip Multiprocessor Architectures.	IISWC	2006	DBLP DOI BibTeX RDF
11	Li Yang 0001, Lu Peng 0001	SecCMP: a secure chip-multiprocessor architecture.	ASID	2006	DBLP DOI BibTeX RDF	security, fault-tolerance, encryption, chip-multiprocessor
11	Jack Sampson, Rubén González, Jean-Francois Collard, Norman P. Jouppi, Michael S. Schlansker	Fast synchronization for chip multiprocessors.	SIGARCH Comput. Archit. News	2005	DBLP DOI BibTeX RDF
11	Neil Vachharajani, Matthew Iyer, Chinmay Ashok, Manish Vachharajani, David I. August, Daniel A. Connors	Chip multi-processor scalability for single-threaded applications.	SIGARCH Comput. Archit. News	2005	DBLP DOI BibTeX RDF
11	Jian Li 0059, José F. Martínez	Power-performance considerations of parallel computing on chip multiprocessors.	ACM Trans. Archit. Code Optim.	2005	DBLP DOI BibTeX RDF	Voltage/frequency scaling, granularity, parallel efficiency
11	Ben Wun, Jeremy Buhler, Patrick Crowley	Exploiting Coarse-Grained Parallelism to Accelerate Protein Motif Finding with a Network Processor.	IEEE PACT	2005	DBLP DOI BibTeX RDF
11	Austen McDonald, JaeWoong Chung, Hassan Chafi, Chi Cao Minh, Brian D. Carlstrom, Lance Hammond, Christos Kozyrakis, Kunle Olukotun	Characterization of TCC on Chip-Multiprocessors.	IEEE PACT	2005	DBLP DOI BibTeX RDF
11	Lawrence Spracklen, Yuan Chou, Santosh G. Abraham	Effective Instruction Prefetching in Chip Multiprocessors for Modern Commercial Applications.	HPCA	2005	DBLP DOI BibTeX RDF
11	Francisco J. Villa, Manuel E. Acacio, José M. García 0001	Memory Subsystem Characterization in a 16-Core Snoop-Based Chip-Multiprocessor Architecture.	HPCC	2005	DBLP DOI BibTeX RDF
11	Thomas Y. Yeh, Glenn Reinman	Fast and fair: data-stream quality of service.	CASES	2005	DBLP DOI BibTeX RDF	NUCA, non-uniform access, per thread degradation, cluster, adaptive, cache, distributed, data-stream, partition, embedded, CMP, chip multiprocessor, migration, bandwidth, QOS, phase, memory wall, PDAS
11	Björn Jäger, Jörg-Christian Niemann, Ulrich Rückert 0001	Analytical approach to massively parallel architectures for nanotechnologies.	ASAP	2005	DBLP DOI BibTeX RDF
11	Martin Karlsson, Erik Hagersten, Kevin E. Moore, David A. Wood 0001	Exploring Processor Design Options for Java-Based Middleware.	ICPP	2005	DBLP DOI BibTeX RDF	Java, Middleware, CMP, workloads, ILP, Characterization
11	Evan Speight, Hazim Shafi, Lixin Zhang 0002, Ramakrishnan Rajamony	Adaptive Mechanisms and Policies for Managing Cache Hierarchies in Chip Multiprocessors.	ISCA	2005	DBLP DOI BibTeX RDF
11	Bob Kuhn	Productivity in HPC Clusters.	NPC	2004	DBLP DOI BibTeX RDF
11	Chun Liu 0001, Anand Sivasubramaniam, Mahmut T. Kandemir	Organizing the Last Line of Defense before Hitting the Memory Wall for CMP.	HPCA	2004	DBLP DOI BibTeX RDF
11	Lance Hammond, Vicky Wong, Michael K. Chen, Brian D. Carlstrom, John D. Davis, Ben Hertzberg, Manohar K. Prabhu, Honggo Wijaya, Christos Kozyrakis, Kunle Olukotun	Transactional Memory Coherence and Consistency.	ISCA	2004	DBLP DOI BibTeX RDF
11	Zoran Radovic, Erik Hagersten	Hierarchical Backoff Locks for Nonuniform Communication Architectures.	HPCA	2003	DBLP DOI BibTeX RDF
11	Michael K. Chen, Kunle Olukotun	The Jrpm System for Dynamically Parallelizing Java Programs.	ISCA	2003	DBLP DOI BibTeX RDF
11	Chong-liang Ooi, Seon Wook Kim, Il Park 0001, Rudolf Eigenmann, Babak Falsafi, T. N. Vijaykumar	Multiplex: unifying conventional and speculative thread-level parallelism on a chip multiprocessor.	ICS	2001	DBLP DOI BibTeX RDF
11	Marcelo H. Cintra, José F. Martínez, Josep Torrellas	Architectural support for scalable speculative parallelization in shared-memory multiprocessors.	ISCA	2000	DBLP DOI BibTeX RDF
11	John L. Gustafson	Reevaluating Amdahl's Law.	Commun. ACM	1988	DBLP DOI BibTeX RDF