Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
17 | Nan Liu 0002, Song Chen 0001, Takeshi Yoshimura |
Resource-Aware Multi-Layer Floorplanning for Partially Reconfigurable FPGAs. |
IEICE Trans. Electron. |
2013 |
DBLP DOI BibTeX RDF |
|
17 | Katherine Shu-Min Li, Yingchieh Ho, Liang-Bi Chen |
Interconnect-Driven Floorplanning with Noise-Aware Buffer Planning. |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. |
2013 |
DBLP DOI BibTeX RDF |
|
17 | Ruining He, Guoqiang Liang, Yuchun Ma, Yu Wang 0002, Jinian Bian |
Unification of PR Region floorplanning and Fine-Grained Placement for Dynamic Partially Reconfigurable FPGAs. |
J. Circuits Syst. Comput. |
2013 |
DBLP DOI BibTeX RDF |
|
17 | Jackey Z. Yan, Chris Chu |
SDS: An Optimal Slack-Driven Block Shaping Algorithm for Fixed-Outline Floorplanning. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2013 |
DBLP DOI BibTeX RDF |
|
17 | S. Anand, S. Saravanasankar, P. Subbaraj |
A multiobjective optimization tool for Very Large Scale Integrated nonslicing floorplanning. |
Int. J. Circuit Theory Appl. |
2013 |
DBLP DOI BibTeX RDF |
|
17 | Chyi-Shiang Hoo, Kanesan Jeevan, Velappa Ganapathy, Harikrishnan Ramiah |
Variable-Order Ant System for VLSI multiobjective floorplanning. |
Appl. Soft Comput. |
2013 |
DBLP DOI BibTeX RDF |
|
17 | D. Gracia Nirmala Rani, S. Rajaram 0001 |
A survey on B*-Tree-based evolutionary algorithms for VLSI floorplanning optimisation. |
Int. J. Comput. Appl. Technol. |
2013 |
DBLP DOI BibTeX RDF |
|
17 | Zhufei Chu, Yinshui Xia, Lun-Yao Wang, Jian Wang |
Voltage Drop Aware Power Pad Assignment and Floorplanning for Multi-voltage SoC Designs. |
CAD/Graphics |
2013 |
DBLP DOI BibTeX RDF |
|
17 | Mohammad A. Ahmed, Malgorzata Chrzanowska-Jeske |
TSV capacitance aware 3-D floorplanning. |
3DIC |
2013 |
DBLP DOI BibTeX RDF |
|
17 | Artur Quiring, Markus Olbrich, Erich Barke |
Improving 3D-Floorplanning using smart selection operations in meta-heuristic optimization. |
3DIC |
2013 |
DBLP DOI BibTeX RDF |
|
17 | Christian Beckhoff, Dirk Koch, Jim Tørresen |
Automatic Floorplanning and Interface Synthesis of Island Style Reconfigurable Systems with GoAhead. |
ARCS |
2013 |
DBLP DOI BibTeX RDF |
|
17 | Kai-Chung Chan, Chao-Jam Hsu, Jia-Ming Lin |
A flexible fixed-outline floorplanning methodology for mixed-size modules. |
ASP-DAC |
2013 |
DBLP DOI BibTeX RDF |
|
17 | Shantesh Pinge, Rajeev K. Nain, Malgorzata Chrzanowska-Jeske |
Fast floorplanning with placement constraints. |
LASCAS |
2013 |
DBLP DOI BibTeX RDF |
|
17 | Puskar Budhathoki, Johann Knechtel, Andreas Henschel, Ibrahim Abe M. Elfadel |
Integration of thermal management and floorplanning based on three-dimensional layout representations. |
ICECS |
2013 |
DBLP DOI BibTeX RDF |
|
17 | Shyam Ramji |
Challenges in managing timing and wiring contracts during hierarchical floorplanning and design closure. |
ISPD |
2013 |
DBLP DOI BibTeX RDF |
|
17 | Robert Fischbach, Johann Knechtel, Jens Lienig |
Utilizing 2D and 3D rectilinear blocks for efficient IP reuse and floorplanning of 3D-integrated systems. |
ISPD |
2013 |
DBLP DOI BibTeX RDF |
|
17 | Sheng-Jhih Jiang, Tsung-Yi Ho |
A rapid analog amendment framework using the incremental floorplanning technique. |
ISCAS |
2013 |
DBLP DOI BibTeX RDF |
|
17 | Bo Huang, Song Chen 0001, Wei Zhong, Takeshi Yoshimura |
Topology-aware floorplanning for 3D application-specific Network-on-Chip synthesis. |
ISCAS |
2013 |
DBLP DOI BibTeX RDF |
|
17 | Shuang Yu, Fen Ge, Gui Feng, Ning Wu |
A two-phase floorplanning approach for Application-specific Network-on-Chip. |
ASICON |
2013 |
DBLP DOI BibTeX RDF |
|
17 | Jieliang Lu, Qin Wang 0009, Jing Xie 0010, Zhigang Mao |
TSVs-aware floorplanning for 3D integrated circuit. |
ASICON |
2013 |
DBLP DOI BibTeX RDF |
|
17 | Chih-han Hsu, Shanq-Jang Ruan, Ying-Jung Chen, Tsang-Chi Kan |
Reliability consideration with rectangle- and double-signal through silicon vias insertion in 3D thermal-aware floorplanning. |
ISQED |
2013 |
DBLP DOI BibTeX RDF |
|
17 | S. Anand, S. Saravanasankar, P. Subbaraj |
Customized simulated annealing based decision algorithms for combinatorial optimization in VLSI floorplanning problem. |
Comput. Optim. Appl. |
2012 |
DBLP DOI BibTeX RDF |
|
17 | Po-Hsun Wu, Tsung-Yi Ho |
Bus-driven floorplanning with bus pin assignment and deviation minimization. |
Integr. |
2012 |
DBLP DOI BibTeX RDF |
|
17 | Jai-Ming Lin, Zhi-Xiong Hung |
SKB-Tree: A Fixed-Outline Driven Representation for Modern Floorplanning Problems. |
IEEE Trans. Very Large Scale Integr. Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
17 | Naohiro Hamada, Hiroshi Saito |
Integration of Behavioral Synthesis and Floorplanning for Asynchronous Circuits with Bundled-Data Implementation. |
IEICE Trans. Electron. |
2012 |
DBLP DOI BibTeX RDF |
|
17 | Nan Liu 0002, Song Chen 0001, Takeshi Yoshimura |
Floorplanning for High Utilization of Heterogeneous FPGAs. |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. |
2012 |
DBLP DOI BibTeX RDF |
|
17 | Dipanjan Sengupta, Andreas G. Veneris, Steven J. E. Wilton, André Ivanov |
Multi-objective voltage island floorplanning using sequence pair representation. |
Sustain. Comput. Informatics Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
17 | Felipe Frantz, Lioua Labrak, Ian O'Connor |
3D IC floorplanning: Automating optimization settings and exploring new thermal-aware management techniques. |
Microelectron. J. |
2012 |
DBLP DOI BibTeX RDF |
|
17 | Iksoon Lim, Hyounseok Song, Hyunchul Shin |
Integrated Circuit Floorplanning by Using an Analytical Algorithm. |
ICHIT (1) |
2012 |
DBLP DOI BibTeX RDF |
|
17 | David W. Browning, Ayman M. El Ansary, Mohamed Shalaby |
System floorplanning optimization. |
ICEAC |
2012 |
DBLP DOI BibTeX RDF |
|
17 | Jai-Ming Lin, Wei-Yi Cheng, Chung-Lin Lee, Richard C. Hsu |
Voltage island-driven floorplanning considering level shifter placement. |
ASP-DAC |
2012 |
DBLP DOI BibTeX RDF |
|
17 | Aaron Wood, Adam Knight, Benjamin Ylvisaker, Scott Hauck |
Multi-kernel floorplanning for enhanced CGRAS. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
17 | Bo Huang, Song Chen 0001, Wei Zhong, Takeshi Yoshimura |
Application-Specific Network-on-Chip synthesis with topology-aware floorplanning. |
SBCCI |
2012 |
DBLP DOI BibTeX RDF |
|
17 | Mohammad A. Ahmed, Shantesh Pinge, Malgorzata Chrzanowska-Jeske |
Fast floorplanning for fixed-outline and nonrectangular regions. |
ICECS |
2012 |
DBLP DOI BibTeX RDF |
|
17 | Jackey Z. Yan, Chris Chu |
Optimal slack-driven block shaping algorithm in fixed-outline floorplanning. |
ISPD |
2012 |
DBLP DOI BibTeX RDF |
|
17 | Renshen Wang, Nimish Shah |
Scalable hierarchical floorplanning for fast physical prototyping of systems-on-chip. |
ISPD |
2012 |
DBLP DOI BibTeX RDF |
|
17 | Zhen Chen, Jinzhu Chen, Wenzhong Guo, Guolong Chen |
A coevolutionary multi-objective PSO algorithm for VLSI floorplanning. |
ICNC |
2012 |
DBLP DOI BibTeX RDF |
|
17 | Kizheppatt Vipin, Suhaib A. Fahmy |
Architecture-Aware Reconfiguration-Centric Floorplanning for Partial Reconfiguration. |
ARC |
2012 |
DBLP DOI BibTeX RDF |
|
17 | Song Chen 0001, Xiaolin Zhang, Takeshi Yoshimura |
Practically scalable floorplanning with voltage island generation. |
ISLPED |
2012 |
DBLP DOI BibTeX RDF |
|
17 | I. Hameem Shanavas, Ramaswamy Kannan Gnanamurthy |
Wirelength Minimization in Partitioning and Floorplanning Using Evolutionary Algorithms. |
VLSI Design |
2011 |
DBLP DOI BibTeX RDF |
|
17 | Qiang Zhou 0001, Jin Shi, Bin Liu 0007, Yici Cai |
Floorplanning Considering IR Drop in Multiple Supply Voltages Island Designs. |
IEEE Trans. Very Large Scale Integr. Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
17 | Rajeev K. Nain, Malgorzata Chrzanowska-Jeske |
Fast Placement-Aware 3-D Floorplanning Using Vertical Constraints on Sequence Pairs. |
IEEE Trans. Very Large Scale Integr. Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
17 | Ming-Chao Tsai, Ting-Chi Wang, Ting Ting Hwang |
Through-Silicon Via Planning in 3-D Floorplanning. |
IEEE Trans. Very Large Scale Integr. Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
17 | Ankur Jain, Syed M. Alam, Scott Pozder, Robert E. Jones |
Thermal-electrical co-optimisation of floorplanning of three-dimensional integrated circuits under manufacturing and physical design constraints. |
IET Comput. Digit. Tech. |
2011 |
DBLP DOI BibTeX RDF |
|
17 | Licheng Xue, Feng Shi 0009, Weixing Ji, Haroon-Ur-Rashid Khan |
3D floorplanning of low-power and area-efficient Network-on-Chip architecture. |
Microprocess. Microsystems |
2011 |
DBLP DOI BibTeX RDF |
|
17 | Jianli Chen, Wenxing Zhu, M. Montaz Ali |
A Hybrid Simulated Annealing Algorithm for Nonslicing VLSI Floorplanning. |
IEEE Trans. Syst. Man Cybern. Part C |
2011 |
DBLP DOI BibTeX RDF |
|
17 | Pritha Banerjee 0001, Megha Sangtani, Susmita Sur-Kolay |
Floorplanning for Partially Reconfigurable FPGAs. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
17 | Jai-Ming Lin, Zhi-Xiong Hung |
UFO: Unified Convex Optimization Algorithms for Fixed-Outline Floorplanning Considering Pre-Placed Modules. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
17 | Qiang Ma 0002, Zaichen Qian, Evangeline F. Y. Young, Hai Zhou 0001 |
MSV-Driven Floorplanning. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
17 | Karthik Sankaranarayanan, Brett H. Meyer, Mircea R. Stan, Kevin Skadron |
Thermal benefit of multi-core floorplanning: A limits study. |
Sustain. Comput. Informatics Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
17 | Kian Haghdad, Mohab Anis, Yehea I. Ismail |
Floorplanning for low power IC design considering temperature variations. |
Microelectron. J. |
2011 |
DBLP DOI BibTeX RDF |
|
17 | Yiding Han, Koushik Chakraborty, Sanghamitra Roy, Vilasita Kuntamukkala |
Design and Implementation of a Throughput-Optimized GPU Floorplanning Algorithm. |
ACM Trans. Design Autom. Electr. Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
17 | Michael B. Healy, Fayez Mohamood, Hsien-Hsin S. Lee, Sung Kyu Lim |
Integrated microarchitectural floorplanning and run-time controller for inductive noise mitigation. |
ACM Trans. Design Autom. Electr. Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
17 | Yih-Lang Li, Yu-Ning Chang, Wen-Nai Cheng |
A gridless routing system with nonslicing floorplanning-based crosstalk reduction on gridless track assignment. |
ACM Trans. Design Autom. Electr. Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
17 | Mandar Padmawar, Sanghamitra Roy, Koushik Chakraborty |
Microprocessor Power Supply Noise Aware Floorplanning Using a Circuit-Architectural Framework. |
J. Low Power Electron. |
2011 |
DBLP DOI BibTeX RDF |
|
17 | Felipe Frantz, Lioua Labrak, Ian O'Connor |
3D-IC floorplanning: Applying meta-optimization to improve performance. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
17 | Licheng Xue, Weixing Ji, Qi Zuo, Yang Zhang |
Floorplanning exploration and performance evaluation of a new Network-on-Chip. |
DATE |
2011 |
DBLP DOI BibTeX RDF |
|
17 | Debora Matos, Gianluca Palermo, Vittorio Zaccaria, Cezar Reinbrecht, Altamiro Amadeu Susin, Cristina Silvano, Luigi Carro |
Floorplanning-aware design space exploration for application-specific hierarchical networks on-chip. |
NoCArc@MICRO |
2011 |
DBLP DOI BibTeX RDF |
|
17 | Artur Quiring, Marc Lindenberg, Markus Olbrich, Erich Barke |
3D floorplanning considering vertically aligned rectilinear modules using T∗-tree. |
3DIC |
2011 |
DBLP DOI BibTeX RDF |
|
17 | Andreas Thor Winther, Wei Liu 0016, Alberto Nannarelli, Sarma B. K. Vrudhula |
Temperature dependent wire delay estimation in floorplanning. |
NORCHIP |
2011 |
DBLP DOI BibTeX RDF |
|
17 | Xi Chen, Jiang Hu, Ning Xu 0006 |
Regularity-constrained floorplanning for multi-core processors. |
ISPD |
2011 |
DBLP DOI BibTeX RDF |
|
17 | Dipanjan Sengupta, Andreas G. Veneris, Steven J. E. Wilton, André Ivanov, Res Saleh |
Sequence pair based voltage island floorplanning. |
IGCC |
2011 |
DBLP DOI BibTeX RDF |
|
17 | David Cuesta Gómez, José Luis Risco-Martín, José Luis Ayala, José Ignacio Hidalgo |
A combination of evolutionary algorithm and mathematical programming for the 3d thermal-aware floorplanning problem. |
GECCO |
2011 |
DBLP DOI BibTeX RDF |
|
17 | Po-Hsun Wu, Tsung-Yi Ho |
Thermal-aware bus-driven floorplanning. |
ISLPED |
2011 |
DBLP BibTeX RDF |
|
17 | Sachhidh Kannan, Garrett S. Rose |
A hierarchical 3-D floorplanning algorithm for many-core CMP networks. |
ISCAS |
2011 |
DBLP DOI BibTeX RDF |
|
17 | Wei Zhong, Song Chen 0001, Fei Ma, Takeshi Yoshimura, Satoshi Goto |
Floorplanning driven Network-on-Chip synthesis for 3-D SoCs. |
ISCAS |
2011 |
DBLP DOI BibTeX RDF |
|
17 | Jeonghee Shin, John A. Darringer, Guojie Luo, Merav Aharoni, Alexey Lvov, Gi-Joon Nam, Michael B. Healy |
Floorplanning challenges in early chip planning. |
SoCC |
2011 |
DBLP DOI BibTeX RDF |
|
17 | Naohiro Hamada, Hiroshi Saito |
Integration of behavioral synthesis and floorplanning for asynchronous circuits with bundled-data implementation. |
ACM Great Lakes Symposium on VLSI |
2011 |
DBLP DOI BibTeX RDF |
|
17 | Xiaolin Zhang, Zhi Lin, Song Chen 0001, Takeshi Yoshimura |
An effecient level-shifter floorplanning method for Multi-voltage design. |
ASICON |
2011 |
DBLP DOI BibTeX RDF |
|
17 | Yiding Han, Sanghamitra Roy, Koushik Chakraborty |
Optimizing simulated annealing on GPU: A case study with IC floorplanning. |
ISQED |
2011 |
DBLP DOI BibTeX RDF |
|
17 | Mandar Padmawar, Sanghamitra Roy, Koushik Chakraborty |
Integrated circuit-architectural framework for PSN aware floorplanning in microprocessors. |
ISQED |
2011 |
DBLP DOI BibTeX RDF |
|
17 | Nan Liu 0002, Song Chen 0001, Takeshi Yoshimura |
Floorplanning for high utilization of heterogeneous FPGAs. |
ISQED |
2011 |
DBLP DOI BibTeX RDF |
|
17 | Yiding Han, Koushik Chakraborty, Sanghamitra Roy, Vilasita Kuntamukkala |
A GPU Algorithm for IC Floorplanning: Specification, Analysis and Optimization. |
VLSI Design |
2011 |
DBLP DOI BibTeX RDF |
|
17 | Yiming Li, Yi Li, Mingtian Zhou |
Area Optimization in Floorplanning Using AP-TCG. |
J. Convergence Inf. Technol. |
2010 |
DBLP BibTeX RDF |
|
17 | Alessio Montone, Marco D. Santambrogio, Donatella Sciuto, Seda Ogrenci Memik |
Placement and Floorplanning in Dynamically Reconfigurable FPGAs. |
ACM Trans. Reconfigurable Technol. Syst. |
2010 |
DBLP DOI BibTeX RDF |
|
17 | Song Chen 0001, Takeshi Yoshimura |
Multi-layer floorplanning for stacked ICs: Configuration number and fixed-outline constraints. |
Integr. |
2010 |
DBLP DOI BibTeX RDF |
|
17 | Yuchun Ma, Qiang Zhou 0001, Pingqiang Zhou, Xianlong Hong |
Thermal Impacts of Leakage Power in 2D/3D floorplanning. |
J. Circuits Syst. Comput. |
2010 |
DBLP DOI BibTeX RDF |
|
17 | Jackey Z. Yan, Chris Chu |
DeFer: Deferred Decision Making Enabled Fixed-Outline Floorplanning Algorithm. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2010 |
DBLP DOI BibTeX RDF |
|
17 | Guolong Chen, Wenzhong Guo, Yuzhong Chen |
A PSO-based intelligent decision algorithm for VLSI floorplanning. |
Soft Comput. |
2010 |
DBLP DOI BibTeX RDF |
|
17 | Ying-Chieh Chen, Yiming Li 0005 |
Temperature-aware floorplanning via geometric programming. |
Math. Comput. Model. |
2010 |
DBLP DOI BibTeX RDF |
|
17 | Cheng-Hong Li, Sampada Sonalkar, Luca P. Carloni |
Exploiting local logic structures to optimize multi-core SoC floorplanning. |
DATE |
2010 |
DBLP DOI BibTeX RDF |
|
17 | Pavel Ghosh, Arunabha Sen |
Power efficient voltage islanding for Systems-on-chip from a floorplanning perspective. |
DATE |
2010 |
DBLP DOI BibTeX RDF |
|
17 | Bei Yu 0001, Sheqin Dong, Song Chen 0001, Satoshi Goto |
Floorplanning and topology generation for application-specific network-on-chip. |
ASP-DAC |
2010 |
DBLP DOI BibTeX RDF |
|
17 | Qiang Ma 0002, Martin D. F. Wong, Kai-Yuan Chao |
Configurable multi-product floorplanning. |
ASP-DAC |
2010 |
DBLP DOI BibTeX RDF |
|
17 | Jai-Ming Lin, Hsi Hung |
UFO: unified convex optimization algorithms for fixed-outline floorplanning. |
ASP-DAC |
2010 |
DBLP DOI BibTeX RDF |
|
17 | Linfu Xiao, Subarna Sinha, Jingyu Xu, Evangeline F. Y. Young |
Fixed-outline thermal-aware 3D floorplanning. |
ASP-DAC |
2010 |
DBLP DOI BibTeX RDF |
|
17 | Won Ha Choi, Xun Liu |
Case Study: GPU-based implementation of sequence pair based floorplanning using CUDA. |
ISCAS |
2010 |
DBLP DOI BibTeX RDF |
|
17 | Houng-Yi Li, Iris Hui-Ru Jiang, Hung-Ming Chen |
Simultaneous voltage island generation and floorplanning. |
SoCC |
2010 |
DBLP DOI BibTeX RDF |
|
17 | Wenxu Sheng, Sheqin Dong, Yuliang Wu, Satoshi Goto |
Fixed outline multi-bend bus driven floorplanning. |
ISQED |
2010 |
DBLP DOI BibTeX RDF |
|
17 | Shengqing Shi, Xi Zhang, Rong Luo |
The thermal-aware floorplanning for 3D ICs using Carbon Nanotube. |
APCCAS |
2010 |
DBLP DOI BibTeX RDF |
|
17 | Wenjuan Zhang, Shefali Srivastava, Yajun Ha |
B*-tree based variability-aware floorplanning. |
APCCAS |
2010 |
DBLP DOI BibTeX RDF |
|
17 | Baofang Chang, Wu Jigang, Thambipillai Srikanthan, Lian Li |
A Novel Approach for Multilevel Fixed Outline Floorplanning. |
PAAP |
2010 |
DBLP DOI BibTeX RDF |
|
17 | Bei Yu 0001, Sheqin Dong, Song Chen 0001, Satoshi Goto |
Voltage and Level-Shifter Assignment Driven Floorplanning. |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. |
2009 |
DBLP DOI BibTeX RDF |
|
17 | Yuchun Ma, Xin Li, Yu Wang 0002, Xianlong Hong |
Thermal-Aware Incremental Floorplanning for 3D ICs Based on MILP Formulation. |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. |
2009 |
DBLP DOI BibTeX RDF |
|
17 | Kang Li, Juebang Yu, Jian Li |
VLSI Floorplanning with Boundary Constraints Based on Single-Sequence Representation. |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. |
2009 |
DBLP DOI BibTeX RDF |
|
17 | Wan-Ping Lee, Hung-Yi Liu, Yao-Wen Chang |
Voltage-Island Partitioning and Floorplanning Under Timing Constraints. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2009 |
DBLP DOI BibTeX RDF |
|
17 | Meng-Chen Wu, Ming-Ching Lu, Hung-Ming Chen, Jing-Yang Jou |
Performance-constrained voltage assignment in multiple supply voltage SoC floorplanning. |
ACM Trans. Design Autom. Electr. Syst. |
2009 |
DBLP DOI BibTeX RDF |
|
17 | Yun Huang, Qiang Zhou 0001, Yici Cai, Haixia Yan |
A thermal-driven force-directed floorplanning algorithm for 3D ICs. |
CAD/Graphics |
2009 |
DBLP DOI BibTeX RDF |
|
17 | Li Li, Yuchun Ma, Ning Xu 0006, Yu Wang 0002, Xianlong Hong |
Modern Floorplanning with Boundary Clustering Constraint. |
ISVLSI |
2009 |
DBLP DOI BibTeX RDF |
|
17 | Xin Li, Yuchun Ma, Xianlong Hong |
A novel thermal optimization flow using incremental floorplanning for 3D ICs. |
ASP-DAC |
2009 |
DBLP DOI BibTeX RDF |
|