Search results for "netlist"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
10	Jianhui Xing, Hong Wang, Shiyuan Yang	Constructing Transparency Paths for IP Cores Using Greedy Searching Strategy.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
10	Enrico Macii	Leakage power optimization in standard-cell designs.	SBCCI	2004	DBLP DOI BibTeX RDF
10	Rupesh S. Shelar, Sachin S. Sapatnekar, Prashant Saxena, Xinning Wang	A predictive distributed congestion metric and its application to technology mapping.	ISPD	2004	DBLP DOI BibTeX RDF	congestion prediction, technology mapping
10	Mario R. Casu, Luca Macchiarulo	Floorplanning for throughput.	ISPD	2004	DBLP DOI BibTeX RDF	systems-on-chip, throughput, floorplanning, wire pipelining
10	Dennis K. Y. Tong, Evangeline F. Y. Young	Performance-driven register insertion in placement.	ISPD	2004	DBLP DOI BibTeX RDF	post-retiming, register insertion, placement
10	Jie-Hong Roland Jiang, Alan Mishchenko, Robert K. Brayton	On breakable cyclic definitions.	ICCAD	2004	DBLP DOI BibTeX RDF
10	Chuan Lin 0002, Hai Zhou 0001	Optimal wire retiming without binary search.	ICCAD	2004	DBLP DOI BibTeX RDF
10	Rajesh Bollapragada	3D-VLSI Design Tool.	International Conference on Computational Science	2004	DBLP DOI BibTeX RDF
10	David A. Papa, Saurabh N. Adya, Igor L. Markov	Constructive benchmarking for placement.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	placer, performance, evaluation, benchmark, comparison
10	M. Moiz Khan, Spyros Tragoudas	Rewiring for Watermarking Digital Circuits.	ISQED	2004	DBLP DOI BibTeX RDF
10	Ganesh K. Venayagamoorthy, Venu G. Gudise	Swarm Intelligence for Digital Circuits Implementation on Field Programmable Gate Arrays Platforms.	Evolvable Hardware	2004	DBLP DOI BibTeX RDF
10	PariVallal Kannan, Dinesh Bhatia	Estimating Pre-Placement FPGA Interconnection Requirements.	VLSI Design	2004	DBLP DOI BibTeX RDF
10	Pranav Anbalagan, Jeffrey A. Davis	Maximum Multiplicity Distributions for Length Prediction Driven Placement.	VLSI Design	2004	DBLP DOI BibTeX RDF
10	Narender Hanchate, Nagarajan Ranganathan	A New Technique for Leakage Reduction in CMOS Circuits using Self-Controlled Stacked Transistors.	VLSI Design	2004	DBLP DOI BibTeX RDF
10	Qinghua Liu, Malgorzata Marek-Sadowska	Pre-layout wire length and congestion estimation.	DAC	2004	DBLP DOI BibTeX RDF	prediction, congestion, wire length
10	Paul K. Rodman	Forest vs. trees: where's the slack?	DAC	2004	DBLP DOI BibTeX RDF
10	Raymond A. Wildman, Joshua I. Kramer, Daniel S. Weile, Phillip Christie	Multi-objective optimization of interconnect geometry.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
10	O. Milter, Avinoam Kolodny	Crosstalk noise reduction in synthesized digital logic circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
10	Ingmar Neumann, Wolfgang Kunz	Layout driven retiming using the coupled edge timing model.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
10	Michael J. Wirthlin, Brian McMurtrey	Web-based IP evaluation and distribution using applets.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
10	Yongseok Cheon, Martin D. F. Wong	Design hierarchy-guided multilevel circuit partitioning.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
10	Arun Raghupathy, Nitin Chandrachoodan, K. J. Ray Liu	Algorithm and VLSI architecture for high performance adaptive video scaling.	IEEE Trans. Multim.	2003	DBLP DOI BibTeX RDF
10	Tilman Glökler, Andreas Hoffmann 0002, Heinrich Meyr	Methodical Low-Power ASIP Design Space Exploration.	J. VLSI Signal Process.	2003	DBLP DOI BibTeX RDF	ICORE, low power, ASIP, application-specific instruction set processor, low energy, LISA
10	Nur Engin, Hans G. Kerkhoff	Fast Fault Simulation for Nonlinear Analog Circuits.	IEEE Des. Test Comput.	2003	DBLP DOI BibTeX RDF
10	Behzad Akbarpour, Sofiène Tahar	Modeling System C Fixed-Point Arithmetic in HOL.	ICFEM	2003	DBLP DOI BibTeX RDF
10	John T. O'Donnell	Embedding a Hardware Description Language in Template Haskell.	Domain-Specific Program Generation	2003	DBLP DOI BibTeX RDF
10	Jean Oudinot	The Most Complete Mixed-Signal Simulation Solution with ADVance MS.	PATMOS	2003	DBLP DOI BibTeX RDF
10	Michael G. Wrighton, André DeHon	Hardware-assisted simulated annealing with application for fast FPGA placement.	FPGA	2003	DBLP DOI BibTeX RDF	field-programmable gate arrays, simulated annealing, placement, reconfigurable computing, design automation
10	Mehrdad Eslami Dehkordi, Stephen Dean Brown	Recursive circuit clustering for minimum delay and area.	FPGA	2003	DBLP DOI BibTeX RDF
10	Ketan Padalia, Ryan Fung, Mark Bourgeault, Aaron Egier, Jonathan Rose	Automatic transistor and physical design of FPGA tiles from an architectural specification.	FPGA	2003	DBLP DOI BibTeX RDF	FPGA, programmable logic, PLD, automatic layout
10	Fei Li 0003, Deming Chen, Lei He 0001, Jason Cong	Architecture evaluation for power-efficient FPGAs.	FPGA	2003	DBLP DOI BibTeX RDF	FPGA power model, low power design, FPGA architecture
10	Akshay Sharma, Carl Ebeling, Scott Hauck	PipeRoute: a pipelining-aware router for FPGAs.	FPGA	2003	DBLP DOI BibTeX RDF	BFS, PipeRoute, retimed circuits, routing, pipelining, minimum spanning tree, retiming, pipelined circuits
10	Pedram A. Riahi, Zainalabedin Navabi, Fabrizio Lombardi	The VPI-Based Combinational IP Core Module-Based Mixed Level Serial Fault Simulation and Test Generation Methodology.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
10	Ravi Varadarajan	Convergence of placement technology in physical synthesis: is placement really a point tool?	ISPD	2003	DBLP DOI BibTeX RDF
10	Hugo Hedberg, Thomas Lenart, Henrik Svensson, Peter Nilsson 0001, Viktor Öwall	Teaching Digital HW-Design by Implementing a Complete MP3 Decoder.	MSE	2003	DBLP DOI BibTeX RDF
10	Huaiyu Xu, Maogang Wang, Bo-Kyung Choi, Majid Sarrafzadeh	A Trade-off Oriented Placement Tool.	ICCAD	2003	DBLP DOI BibTeX RDF	Quality, Placement, Runtime
10	Qi Wang, Sumit Roy 0003	RTL Power Optimization with Gate-Level Accuracy.	ICCAD	2003	DBLP DOI BibTeX RDF
10	Josep Carmona 0001, Jordi Cortadella	ILP Models for the Synthesis of Asynchronous Control Circuits.	ICCAD	2003	DBLP DOI BibTeX RDF
10	Chuan Lin 0002, Hai Zhou 0001	Retiming for Wire Pipelining in System-On-Chip.	ICCAD	2003	DBLP DOI BibTeX RDF
10	Thomas Lenart, Viktor Öwall	A 2048 complex point FFT processor using a novel data scaling approach.	ISCAS (4)	2003	DBLP DOI BibTeX RDF
10	Masud H. Chowdhury, Chirayu S. Amin, Yehea I. Ismail, Chandramouli V. Kashyap, Byron Krauter	Realizable reduction of RLC circuits using node elimination.	ISCAS (3)	2003	DBLP DOI BibTeX RDF
10	Ewan Mardhana, Tohru Ikeguchi	Neurosearch: a program library for neural network driven search meta-heuristics.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
10	Sadiq M. Sait, Aiman H. El-Maleh, Raslan H. Al-Abaji	General iterative heuristics for VLSI multiobjective partitioning.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
10	Rolf Drechsler, Junhao Shi, Görschwin Fey	MuTaTe: an efficient design for testability technique for multiplexor based circuits.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	multiplexor based circuits, design for testability, logic synthesis, BDDs, decision diagrams
10	Ananta K. Majhi, Guido Gronthoud, Camelia Hora, Maurice Lousberg, Pop Valer, Stefan Eichenberger	Improving Diagnostic Resolution of Delay Faults using Path Delay Fault Model.	VTS	2003	DBLP DOI BibTeX RDF
10	Mahesh A. Iyer	Race: A Word-Level ATPG-Based Constraints Solver System For Smart Random Simulation.	ITC	2003	DBLP DOI BibTeX RDF
10	Kevin Melocco, Hina Arora, Paul Setlak, Gary Kunselman, Shazia Mardhani	A Comprehensive Approach to Assessing and Analyzing 1149.1 Test Logic.	ITC	2003	DBLP DOI BibTeX RDF
10	Tom Waayers	An improved Test Control Architecture and Test Control Expansion for Core-Based System Chips.	ITC	2003	DBLP DOI BibTeX RDF
10	Robert Thomson 0003, Tughrul Arslan	The Evolutionary Design and Synthesis of Non-Linear Digital VLSI Systems.	Evolvable Hardware	2003	DBLP DOI BibTeX RDF
10	Chirayu S. Amin, Masud H. Chowdhury, Yehea I. Ismail	Realizable RLCK circuit crunching.	DAC	2003	DBLP DOI BibTeX RDF	crunching, simulation, interconnect, passive, realizable, model order reduction
10	Bo Hu 0006, Malgorzata Marek-Sadowska	Wire length prediction based clustering and its application in placement.	DAC	2003	DBLP DOI BibTeX RDF	wire length prediction, clustering, placement
10	Stelian Alupoaei, Srinivas Katkoori	Net-based force-directed macrocell placement for wirelength optimization.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
10	Qi Wang, Sarma B. K. Vrudhula	Algorithms for minimizing standby power in deep submicrometer, dual-Vt CMOS circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
10	Shantanu Dutt, Vinay Verma, Hasan Arslan	A search-based bump-and-refit approach to incremental routing for ECO applications in FPGAs.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	Bump-and-refit (B&R) paradigm, ECO (engineering change order), bumping cost, incremental routing, switchbox, field programmable gate arrays, dynamic programming, global routing, detailed routing
10	Thomas Kutzschebauch, Leon Stok	Layout Driven Decomposition with Congestion Consideration.	DATE	2002	DBLP DOI BibTeX RDF
10	Rolf Drechsler, Wolfgang Günther 0001, Thomas Eschbach, Lothar Linhard, Gerhard Angst	Recursive Bi-Partitioning of Netlists for Large Number of Partitions.	DSD	2002	DBLP DOI BibTeX RDF
10	Aneesh Koorapaty, Lawrence T. Pileggi	Modular, Fabric-Specific Synthesis for Programmable Architectures.	FPL	2002	DBLP DOI BibTeX RDF
10	Yongseok Cheon, D. F. Wong 0001	Design hierarchy guided multilevel circuit partitioning.	ISPD	2002	DBLP DOI BibTeX RDF	clustering, Rent's rule, circuit partitioning, design hierarchy
10	John O'Donnell 0001	Overview of Hydra: A Concurrent Language for Synchronous Digital Circuit Design.	IPDPS	2002	DBLP DOI BibTeX RDF
10	Brad L. Hutchings, R. Franklin, D. Carver	Assisting Network Intrusion Detection with Reconfigurable Hardware.	FCCM	2002	DBLP DOI BibTeX RDF
10	Sasha Novakovsky, Shy Shyman, Ziyad Hanna	High capacity and automatic functional extraction tool for industrial VLSI circuit designs.	ICCAD	2002	DBLP DOI BibTeX RDF	Formal Equivalence Verification (FEV), Hardware Description Languages (HDL), Switch Level Analysis, functional abstraction, satisfiability procedures, synthesis, Design For Testability (DFT), logic simulation, Binary Decision Diagrams (BDDs)
10	Deshanand P. Singh, Stephen Dean Brown	Incremental placement for layout driven optimizations on FPGAs.	ICCAD	2002	DBLP DOI BibTeX RDF
10	Muzammil Iqbal, Ahmed Sharkawy, Usman Hameed, Phillip Christie	Stochastic wire length sampling for cycle time estimation.	SLIP	2002	DBLP DOI BibTeX RDF	cycle time estimates, wire sampling, performance modeling, physical design
10	Amit Singh 0001, Malgorzata Marek-Sadowska	FPGA interconnect planning.	SLIP	2002	DBLP DOI BibTeX RDF
10	Wei-Jin Dai, Michel Courtoy	Hierarchical Front-End Physical Design Solution Drives Modified Hand-Off (invited).	ISQED	2002	DBLP DOI BibTeX RDF
10	Olivier Coudert	Timing and Design Closure in Physical Design Flows (invited).	ISQED	2002	DBLP DOI BibTeX RDF
10	Stelian Alupoaei, Srinivas Katkoori	Net Clustering Based Macrocell Placement.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	Macrocell placement, net clustering, net placement, net prioritization, force-directed placement, iterative improvement
10	Debasis Samanta, Nishant Sinha 0001, Ajit Pal	Synthesis of High Performance Low Power Dynamic CMOS Circuits.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
10	Gabriela Nicolescu, S. Martinez, Lobna Kriaa, Wassim Youssef, Sungjoo Yoo, Benoît Charlot, Ahmed Amine Jerraya	Application of Multi-Domain and Multi-Language Cosimulation to an Optical MEM Switch Design.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	heterogeneous systems design, MOEMS, cosimulation
10	Michael J. Wirthlin, Brian McMurtrey	IP delivery for FPGAs using Applets and JHDL.	DAC	2002	DBLP DOI BibTeX RDF	JHDL, FPGA, intellectual property, applet
10	Michael Santarini, Sudhakar Jilla, Mark Miller, Tommy Eng, Sandeep Khanna, Kamalesh N. Ruparel, Tom Russell, Kazu Yamada	Whither (or wither?) ASIC handoff?	DAC	2002	DBLP DOI BibTeX RDF
10	Srihari Cadambi, Chandra Mulpuri, Pranav Ashar	A fast, inexpensive and scalable hardware acceleration technique for functional simulation.	DAC	2002	DBLP DOI BibTeX RDF	FPGA, hardware acceleration, VLIW, functional simulation
10	Piet Vanassche, Georges G. E. Gielen, Willy M. C. Sansen	Behavioral modeling of (coupled) harmonic oscillators.	DAC	2002	DBLP DOI BibTeX RDF	coupled harmonic oscillators, behavioral modeling, averaging, perturbation theory
10	Cho W. Moon, Harish Kriplani, Krishna P. Belkhale	Timing model extraction of hierarchical blocks by graph reduction.	DAC	2002	DBLP DOI BibTeX RDF
10	Andrew B. Kahng, John C. Lach, William H. Mangione-Smith, Stefanus Mantik, Igor L. Markov, Miodrag Potkonjak, Paul Tucker, Huijuan Wang, Gregory Wolfe	Constraint-based watermarking techniques for design IP protection.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
10	Michel Renovell, Jean-Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian	A Discussion on Test Pattern Generation for FPGA - Implemented Circuits.	J. Electron. Test.	2001	DBLP DOI BibTeX RDF	FPGA, test, ATPG
10	Rolf Drechsler, Wolfgang Günther 0001, Lothar Linhard, Gerhard Angst	Level Assignment for Displaying Combinational Logic.	DSD	2001	DBLP DOI BibTeX RDF
10	Subash Chandar G., S. Vaideeswaran	Addressing verification bottlenecks of fully synthesized processor cores using equivalence checkers.	ASP-DAC	2001	DBLP DOI BibTeX RDF
10	Jinan Lou, Shankar Krishnamoorthy, Henry S. Sheng	Estimating routing congestion using probabilistic analysis.	ISPD	2001	DBLP DOI BibTeX RDF
10	Peter Verplaetse, Joni Dambre, Dirk Stroobandt, Jan Van Campenhout	On partitioning vs. placement rent properties.	SLIP	2001	DBLP DOI BibTeX RDF	wire length distribution, partitioning, placement, estimation, Rent's rule
10	André DeHon	Rent's rule based switching requirements.	SLIP	2001	DBLP DOI BibTeX RDF	switching requirements, hierarchical networks, Rent's rule
10	Ingmar Neumann, Wolfgang Kunz	Tight coupling of timing-driven placement and retiming.	ISCAS (5)	2001	DBLP DOI BibTeX RDF
10	Wei-Hsin Chang, Shuenn-Der Tzeng, Chen-Yi Lee	A novel subcircuit extraction algorithm by recursive identification scheme.	ISCAS (5)	2001	DBLP DOI BibTeX RDF
10	Hen-Ming Lin, Jing-Yang Jou	On tri-state buffer inference in HDL synthesis.	ISCAS (5)	2001	DBLP DOI BibTeX RDF
10	Yu Cao 0001, Xuejue Huang, Chenming Hu, Norman Chang, Shen Lin, O. Sam Nakagawa, Weize Xie	Effective On-chip Inductance Modeling for Multiple Signal Lines and Application on Repeater Insertion.	ISQED	2001	DBLP DOI BibTeX RDF
10	Debesh Kumar Das, Bhargab B. Bhattacharya, Satoshi Ohtake, Hideo Fujiwara	Testable Design of Sequential Circuits with Improved Fault Efficiency.	VLSI Design	2001	DBLP DOI BibTeX RDF
10	Sujatha Sundararaman, Sriram Govindarajan, Ranga Vemuri	Application Specific Macro Based Synthesis.	VLSI Design	2001	DBLP DOI BibTeX RDF
10	Sree Ganesan, Ranga Vemuri	Library Binding for High-Level Synthesis of Analog Systems.	VLSI Design	2001	DBLP DOI BibTeX RDF
10	Johnny Pihl	Design automation with the TSPC circuit technique: a high-performance wave digital filter.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
10	Indradeep Ghosh, Niraj K. Jha, Sudipta Bhawmik	A BIST scheme for RTL circuits based on symbolic testabilityanalysis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
10	Shantanu Dutt, Wenyong Deng	Probability-based approaches to VLSI circuit partitioning.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
10	Paul Tafertshofer, Andreas Ganz, Kurt Antreich	IGRAINE-an Implication GRaph-bAsed engINE for fast implication, justification, and propagation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
10	John Marty Emmert, Dinesh K. Bhatia	A Fault Tolerant Technique for FPGAs.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	incremental reconfiguration, incremental routing, incremental placement, fault tolerance, FPGA
10	Manuela Anton, Mauro Chinosi, Daniele Sirtori, Roberto Zafalon	Architectural Design Space Exploration Achieved through Innovative RTL Power Estimation Techniques.	PATMOS	2000	DBLP DOI BibTeX RDF
10	Ivan Blunno, Luciano Lavagno	Automated Synthesis of Micro-Pipelines from Behavioral Verilog HDL.	ASYNC	2000	DBLP DOI BibTeX RDF
10	Srini Krishnamoorthy, Sriram Swaminathan, Russell Tessier	Area-Optimized Technology Mapping for Hybrid FPGAs.	FPL	2000	DBLP DOI BibTeX RDF
10	Philip James-Roxby, Steven A. Guccione	Automated Extraction of Run-Time Parameterizable Cores from Programmable Device Configurations.	FCCM	2000	DBLP DOI BibTeX RDF
10	José Ignacio Hidalgo, Juan Lanchares, Román Hermida	Partitioning and Placement for Multi-FPGA Systems Using Genetic Algorithms.	EUROMICRO	2000	DBLP DOI BibTeX RDF
10	Thomas Kutzschebauch	Efficient Logic Optimization Using Regularity Extraction.	ICCD	2000	DBLP DOI BibTeX RDF
10	Subarnarekha Sinha, Sunil P. Khatri, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli	Binary and Multi-Valued SPFD-Based Wire Removal in PLA Networks.	ICCD	2000	DBLP DOI BibTeX RDF