Search results for "time-to-market"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
5	John A. Stankovic	VEST - A Toolset for Constructing and Analyzing Component Based Embedded Systems.	EMSOFT	2001	DBLP DOI BibTeX RDF
5	Ton Dekkers	Project Improvement as Start-Up.	PROFES	2001	DBLP DOI BibTeX RDF
5	Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni	Hierarchical power supply noise evaluation for early power grid design prediction.	SLIP	2001	DBLP DOI BibTeX RDF
5	Pierluigi Daglio, M. Araldi, Michele Morbarigazzi, Carlo Roma	A Fully Qualified Analog Design Flow for Non Volatile Memories Technologies.	ISQED	2001	DBLP DOI BibTeX RDF
5	Vineet Sahula, C. P. Ravikumar	The Hierarchical Concurrent Flow Graph Approach for Modeling and Analysis of Design Processes.	VLSI Design	2001	DBLP DOI BibTeX RDF
5	Keith H. Bennett, Malcolm Munro, Nicolas Gold, Paul J. Layzell 0001, David Budgen, Pearl Brereton	An Architectural Model for Service-Based Software with Ultra Rapid Evolution.	ICSM	2001	DBLP DOI BibTeX RDF
5	Volker Gruhn, Lothar Schöpe, Matthias Book	A Specific Software Development Process for an Electronic Commerce Portal.	APAQS	2001	DBLP DOI BibTeX RDF
5	Frank Slomka, Matthias Dörfel, Ralf Münzenberger, Richard Hofmann	Hardware/Software Codesign and Rapid Prototyping of Embedded Systems.	IEEE Des. Test Comput.	2000	DBLP DOI BibTeX RDF
5	Richard Goldman, Karen Bartleson	Tool Interoperability is Key to Improved Design Quality.	ISQED	2000	DBLP DOI BibTeX RDF
5	Krishnendu Chakrabarty	Design of System-on-a-Chip Test Access Architectures using Integer Linear Programming.	VTS	2000	DBLP DOI BibTeX RDF	test data bandwidth, linearization, test access mechanism (TAM), testing time, Embedded core testing, test bus
5	Mark E. Dean	Trends in Computing.	FMCAD	2000	DBLP DOI BibTeX RDF
5	Chi-Feng Wu, Cheng-Wen Wu	Testing Interconnects of Dynamic Reconfigurable FPGAs.	ASP-DAC	1999	DBLP DOI BibTeX RDF
5	Luc Bianco, Michel Auguin, Alain Pegatoquet	A Prototyping Method of Embedded Real Time Systems for Signal Processing Applications.	EUROMICRO	1999	DBLP DOI BibTeX RDF
5	William Fornaciari, Donatella Sciuto	HW/SW Co-design of Embedded Systems.	Ada-Europe	1999	DBLP DOI BibTeX RDF
5	Carol Pyron, Javier Prado, James Golab	Test Strategy for the PowerPC 750 Microprocessor.	IEEE Des. Test Comput.	1998	DBLP DOI BibTeX RDF
5	Guido Post, Andrea Müller, Thorsten Grötker	A System-Level Co-Verification Environment for ATM Hardware Design.	DATE	1998	DBLP DOI BibTeX RDF	test bench design and reuse, ATM hardware design, system design methodology, co-simulation, interface modeling, co-verification
5	Silvije Jovalekic, Bernd Rist	Impact of Object-Oriented Software Engineering Applied to the Development of Security Systems.	SAFECOMP	1998	DBLP DOI BibTeX RDF
5	James E. Saultz	Rapid Prototyping of Application-Specific Signal Processors (RASSP) In-Progress Report.	J. VLSI Signal Process.	1997	DBLP DOI BibTeX RDF
5	Peter F. A. Middelhoek, Sreeranga P. Rajan	From VHDL to efficient and first-time-right designs: a formal approach.	ACM Trans. Design Autom. Electr. Syst.	1996	DBLP DOI BibTeX RDF	CDFG, SFG, rapid system prototyping, VHDL, VHDL, design methodology, correctness by construction, transformational design
5	David N. Card	Guest Editor's Introduction: The RAD Fad- Is Timing Really Everything?	IEEE Softw.	1995	DBLP DOI BibTeX RDF
5	Emmanuel Henry, Benoît Faller	Large-Scale Industrial Reuse to Reduce Cost and Cycle Time.	IEEE Softw.	1995	DBLP DOI BibTeX RDF
4	Ines Viskic, Lochi Yu, Daniel Gajski	Design exploration and automatic generation of MPSoC platform TLMs from Kahn Process Network applications.	LCTES	2010	DBLP DOI BibTeX RDF	kahn process, transaction level model, automatic generation, process network, process mapping
4	David Cuesta, José Luis Ayala, José Ignacio Hidalgo, Massimo Poncino, Andrea Acquaviva, Enrico Macii	Thermal-aware floorplanning exploration for 3D multi-core architectures.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	3D, floorplanning, MPSoC, temperature
4	Thomas Harms, Juan-Antonio Caraballo, Reynold D'Sa, Ruud A. Haring, Derek Urbaniak, Guntram Wolski, James You	What will make your next design experience a much better one?	DAC	2010	DBLP DOI BibTeX RDF
4	Chuan Duan, Paula Laurent, Jane Cleland-Huang, Charles Kwiatkowski	Towards automated requirements prioritization and triage.	Requir. Eng.	2009	DBLP DOI BibTeX RDF	Requirements triage, Data mining, Non-functional requirements, Requirements prioritization
4	Alastair Colin Murray, Richard Vincent Bennett, Björn Franke, Nigel P. Topham	Code transformation and instruction set extension.	ACM Trans. Embed. Comput. Syst.	2009	DBLP DOI BibTeX RDF	source-level transformations, compilers, design space exploration, ASIPs, instruction set extension, Customizable processors
4	Karin Avnit, Vijay D'Silva, Arcot Sowmya, S. Ramesh, Sri Parameswaran	Provably correct on-chip communication: A formal approach to automatic protocol converter synthesis.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	converter synthesis, protocol compatibility, System-on-chip, automatic design
4	Tamás Vajk, Róbert Kereskényi, Tihamer Levendovszky, Ákos Lédeczi	Raising the Abstraction of Domain-Specific Model Translator Development.	ECBS	2009	DBLP DOI BibTeX RDF
4	Zhongbo Cao, Ramon Mercado, Diane T. Rover	System-level memory modeling for bus-based memory architecture exploration.	EIT	2009	DBLP DOI BibTeX RDF
4	Carlo Galuzzi	Introduction to Instruction-Set Customization.	SAMOS	2009	DBLP DOI BibTeX RDF
4	Francielle S. Santos, Hermano P. Moura	What is wrong with the software development?: research trends and a new software engineering paradigm.	OOPSLA Companion	2009	DBLP DOI BibTeX RDF	intervention theory, software engineering, communication, augmented reality, knowledge management
4	Maman Abdurohman, Kuspriyanto, Sarwono Sutikno, Arif Sasongko	Transaction Level Modeling for Early Verification on Embedded System Design.	ACIS-ICIS	2009	DBLP DOI BibTeX RDF
4	P. Subramanian, Jagonda Patil, Manish Kumar Saxena	FPGA prototyping of a multi-million gate System-on-Chip (SoC) design for wireless USB applications.	IWCMC	2009	DBLP DOI BibTeX RDF	ECMA-368, FPGA-physical implementation, FPGA-synthesis, SoC (system-on-chip), synthesis constraints, FPGA, ASIC (application specific integrated circuits), functional verification, clock gating
4	Zhenxin Sun, Weng-Fai Wong	A UML-based approach for heterogeneous IP integration.	ASP-DAC	2009	DBLP DOI BibTeX RDF
4	Malgorzata Mochól, Tobias Bürger, Markus Luczak-Rösch, Elena Simperl, Lyndon J. B. Nixon, Agata Filipowska, Christoph Tempich	Enterprise X.0 and ECONOM Workshops Chairs' Message.	BIS (Workshops)	2009	DBLP DOI BibTeX RDF
4	Chien Pang Lu, Mango Chia-Tso Chao, Chen Hsing Lo, Chih-Wei Chang	A metal-only-ECO solver for input-slew and output-loading violations.	ISPD	2009	DBLP DOI BibTeX RDF	input skew violation, output loading, buffer insertion, eco
4	Loïc Lagadec, Damien Picard	Software-like debugging methodology for reconfigurable platforms.	IPDPS	2009	DBLP DOI BibTeX RDF
4	Pilar Rodríguez 0002, Agustín Yagüe, Pedro Pablo Alarcón, Juan Garbajosa	Some Findings Concerning Requirements in Agile Methodologies.	PROFES	2009	DBLP DOI BibTeX RDF
4	Akos Szoke	Decision Support for Iteration Scheduling in Agile Environments.	PROFES	2009	DBLP DOI BibTeX RDF	iteration planning, scheduling, agile planning
4	Matthew M. Ziegler, Victor V. Zyuban, George Gristede, Milena Vratonjic, Joshua Friedrich	The opportunity cost of low power design: a case study in circuit tuning.	ISLPED	2009	DBLP DOI BibTeX RDF	low power design, productivity, circuit tuning
4	Don S. Batory	On the importance and challenges of FOSD.	FOSD	2009	DBLP DOI BibTeX RDF	science of automated design, verification, testing, features, feature interactions, feature-oriented software development
4	Andreas W. Liehr, Klaus Buchenrieder	Transforming UML-Based System Descriptions into Simulation Models as Part of System Development Frameworks.	EUROCAST	2009	DBLP DOI BibTeX RDF	Hardware / Software Co-Design, Unified Modeling Language, System Modeling, Performance Simulation, Queuing Network Models
4	Ramamurthy Vishweshwara, Ramakrishnan Venkatraman, Vipul Kadodwala	Early clock prototyping for design analysis and quality entitlement.	ISQED	2009	DBLP DOI BibTeX RDF
4	Meng-Syue Chan, Chun-Yao Wang, Yung-Chih Chen	An efficient approach to sip design integration.	ISQED	2009	DBLP DOI BibTeX RDF
4	Sreeranga P. Rajan, Oksana Tkachuk, Mukul R. Prasad, Indradeep Ghosh, Nitin Goel, Tadahiro Uehara	WEAVE: WEb Applications Validation Environment.	ICSE Companion	2009	DBLP DOI BibTeX RDF
4	Jörg Henkel, Vijaykrishnan Narayanan, Sri Parameswaran, Roshan G. Ragel	Security and Dependability of Embedded Systems: A Computer Architects' Perspective.	VLSI Design	2009	DBLP DOI BibTeX RDF
4	Goetz Botterweck, Iris Groher, Andreas Polzer, Christa Schwanninger, Steffen Thiel, Markus Völter	1st International Workshop on Model-driven Approaches in Software Product Line Engineering: (MAPLE 2009).	SPLC	2009	DBLP BibTeX RDF
4	Daniel Pech, Jens Knodel, Ralf Carbon, Clemens Schitter, Dirk Hein	Variability management in small development organizations: experiences and lessons learned from a case study.	SPLC	2009	DBLP BibTeX RDF	software architecture, evolution, decision model, product line engineering, variability management
4	Pradip A. Thaker	Holistic verification: myth or magic bullet?	DAC	2009	DBLP DOI BibTeX RDF	SoC verification, mixed-signal verification, power management verification, emulation
4	Xuening Sun, Pierluigi Nuzzo 0002, Chang-Ching Wu, Alberto L. Sangiovanni-Vincentelli	Contract-based system-level composition of analog circuits.	DAC	2009	DBLP DOI BibTeX RDF	integration, composition, contract, system, analog, UWB, platform, platform-based design, radio-frequency, assume-guarantee
4	Andreas Raabe, Rastislav Bodík	Synthesizing hardware from sketches.	DAC	2009	DBLP DOI BibTeX RDF	sketching
4	Andrzej J. Strojwas, Tejas Jhaveri, Vyacheslav Rovner, Lawrence T. Pileggi	Creating an affordable 22nm node using design-lithography co-optimization.	DAC	2009	DBLP DOI BibTeX RDF	design technology co-optimization, templates, DFM, regular fabric
4	Andreas G. Veneris, Sean Safarpour	The day Sherlock Holmes decided to do EDA.	DAC	2009	DBLP DOI BibTeX RDF	error localization, verification, debugging
4	May Yee Chong, Björn Bjurling, Ramide Dantas, Carlos Alberto Kamienski, Börje Ohlman	Goal-Based Service Creation Using Autonomic Entities.	MACE	2009	DBLP DOI BibTeX RDF
4	Kurt Englmeier, Ricki Koinig	Domain-Specific Deployment and Configuration Language for Composition and Adaptation of Coarse-Grained Services.	IEEE SCC	2009	DBLP DOI BibTeX RDF
4	David Sellier, Mike Mannion, Jason Xabier Mansell	Managing requirements inter-dependency for software product line derivation.	Requir. Eng.	2008	DBLP DOI BibTeX RDF	Software product line, Requirement specifications, Domain engineering
4	Juan Carlos Baraza, Joaquin Gracia, Sara Blanc, Daniel Gil, Pedro J. Gil	Enhancement of Fault Injection Techniques Based on the Modification of VHDL Code.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
4	Pei-Wen Luo, Jwu-E Chen, Chin-Long Wey, Liang-Chia Cheng, Ji-Jan Chen, Wen Ching Wu	Impact of Capacitance Correlation on Yield Enhancement of Mixed-Signal/Analog Integrated Circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
4	Alexandro Baldassin, Paulo Centoducatte, Sandro Rigo, Daniel C. Casarotto, Luiz C. V. dos Santos, Max R. de O. Schultz, Olinto J. V. Furtado	An open-source binary utility generator.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	Platform debugging, retargetable tools, TLM
4	Lan Cao, Balasubramaniam Ramesh	Agile Requirements Engineering Practices: An Empirical Study.	IEEE Softw.	2008	DBLP DOI BibTeX RDF
4	Jonas Elmqvist, Simin Nadjm-Tehrani	Formal Support for Quantitative Analysis of Residual Risks in Safety-Critical Systems.	HASE	2008	DBLP DOI BibTeX RDF
4	N. Alaraje, Guy Hembroff	Impact of NoFPGA IP router architecture on link bandwidth.	EIT	2008	DBLP DOI BibTeX RDF
4	Paul Edward McKechnie, Nathan A. Lindop, Wim Vanderbauwhede	A type system for static typing of a domain-specific language.	FPGA	2008	DBLP DOI BibTeX RDF	static type checking, FPGA, type system
4	Kangtae Kim, Hyungrok Kim, Sundeok Kim, Gihun Chang	A Case Study on SW Product Line Architecture Evaluation: Experience in the Consumer Electronics Domain.	ICSEA	2008	DBLP DOI BibTeX RDF
4	E. Frank, Reinhard Wilhelm, Rolf Ernst, Alberto L. Sangiovanni-Vincentelli, Marco Di Natale	Methods, Tools and Standards for the Analysis, Evaluation and Design of Modern Automotive Architectures.	DATE	2008	DBLP DOI BibTeX RDF
4	David Novo, Bruno Bougard, Andy Lambrechts, Liesbet Van der Perre, Francky Catthoor	Scenario-Based Fixed-point Data Format Refinement to Enable Energy-scalable Software Defined Radios.	DATE	2008	DBLP DOI BibTeX RDF
4	Ed Brinksma, Jozef Hooman	Dependability for high-tech systems: an industry-as-laboratory approach.	DATE	2008	DBLP DOI BibTeX RDF
4	Seon-Jae Jang, Hae-Geun Kim, Youn-Ky Chung	Manual Specific Testing and Quality Evaluation for Embedded Software.	ACIS-ICIS	2008	DBLP DOI BibTeX RDF
4	Bruno Bougard, Min Li 0001, David Novo, Liesbet Van der Perre, Francky Catthoor	Bridging the energy gap in size, weight and power constrained software defined radio: Agile baseband processing as a key enabler.	ICASSP	2008	DBLP DOI BibTeX RDF
4	Shinya Shimizu, Hideaki Kimata, Kazuto Kamikura, Yoshiyuki Yashima	A backward compatible 3D scene coding using residual prediction.	ICASSP	2008	DBLP DOI BibTeX RDF
4	Ricardo P. Jacobi, Reinaldo A. Bergamaschi	Challenges of the nanoscale era.	SBCCI	2008	DBLP DOI BibTeX RDF	integrated circuits
4	André V. Fidalgo, Gustavo R. Alves, Manuel G. Gericota, José Manuel Martins Ferreira	A comparative analysis of fault injection methods via enhanced on-chip debug infrastructures.	SBCCI	2008	DBLP DOI BibTeX RDF	real time systems, dependability, fault injection
4	Stefano Monti, Walter Nesci, Serino Angellotti, Claudio Schellino, Massimo Seminara, Rainer Wuesthenagen	Configuration and Change Management of the Outcomes of an Automotive Engine Control Model Based Software Design Process.	COMPSAC	2008	DBLP DOI BibTeX RDF
4	Alain Pegatoquet, Filip Thoen, Denis Paterson	Virtual Reality for 2.5 G Wireless Communication Modem Software Development.	COMPSAC	2008	DBLP DOI BibTeX RDF	EGPRS, simulation, MPSoC, GSM, GPRS, Virtual platform
4	Goetz Botterweck, Steffen Thiel, Ciarán Cawley, Daren Nestor, André Preußner	Visual Configuration in Automotive Software Product Lines.	COMPSAC	2008	DBLP DOI BibTeX RDF	Product Deriviation, Software Product Lines, Visualisation, Automotive, Variability Management, Product Configuration
4	David de Andrés, Juan-Carlos Ruiz-Garcia, Daniel Gil, Pedro J. Gil	Dependability Assessment for the Selection of Embedded Cores.	EDCC	2008	DBLP DOI BibTeX RDF
4	Jianjun Zhao, Jeffrey S. Poulin	Appendix: Workshop and Tutorial Abstracts.	ICSR	2008	DBLP DOI BibTeX RDF
4	Yi-Ting Lin, Chien-Chou Wang, Ing-Jer Huang	AMBA AHB bus potocol checker with efficient debugging mechanism.	ISCAS	2008	DBLP DOI BibTeX RDF
4	Jingjun Zhang, Xueyong Cai, Guangyuan Liu	Mapping Features to Architectural Components in Aspect-Oriented Software Product Lines.	CSSE (2)	2008	DBLP DOI BibTeX RDF
4	Marijn Janssen	Exploring the Service-Oriented Enterprise: Drawing Lessons from a Case Study.	HICSS	2008	DBLP DOI BibTeX RDF
4	Saurabh Jain, W. Robert Daasch, David Armbrust	Analyzing the Impact of Fault Tolerant BIST for VLSI Design.	DFT	2008	DBLP DOI BibTeX RDF
4	Antti Jääskeläinen, Antti Kervinen, Mika Katara	Creating a Test Model Library for GUI Testing of Smartphone Applications (Short Paper).	QSIC	2008	DBLP DOI BibTeX RDF
4	Charles Thangaraj, Tom Chen 0001	Early Design Phase Power Performance Trade-Offs Using In-Situ Macro Models.	DELTA	2008	DBLP DOI BibTeX RDF	pareto-front, What-if analysis, Power-performance trade-off
4	Vinod Kathail, Tom Miller	Architecture Exploration for Low Power Design.	VLSI Design	2008	DBLP DOI BibTeX RDF
4	Alex Talevski, Pornpit Wongthongtham, Surasak Komchaliaw	Towards a software component ontology.	iiWAS	2008	DBLP DOI BibTeX RDF	ontology, software engineering, software component
4	Michael Bell	Service-Oriented Life Cycle Modeling: The Shift from Web Services to Enterprise Services.	EDOC	2008	DBLP DOI BibTeX RDF
4	Ganesh S. Dasika, Shidhartha Das, Kevin Fan, Scott A. Mahlke, David M. Bull	DVFS in loop accelerators using BLADES.	DAC	2008	DBLP DOI BibTeX RDF	embedded systems, low power, high-level synthesis, voltage scaling, frequency scaling
4	Ruchir Puri, William H. Joyner, Shekhar Borkar, Ty Garibay, Jonathan Lotz, Robert K. Montoye	Custom is from Venus and synthesis from Mars.	DAC	2008	DBLP DOI BibTeX RDF	IC synthesis techniques, custom IC design, VLSI design
4	Marco Di Natale	Design and Development of Component-Based Embedded Systems for Automotive Applications.	Ada-Europe	2008	DBLP DOI BibTeX RDF
4	Devesh Sharma, Aybüke Aurum, Barbara Paech	Business Value through Product Line Engineering - A Case Study.	EUROMICRO-SEAA	2008	DBLP DOI BibTeX RDF
4	Lars Frantzen, Maria de las Nieves Huerta, Zsolt Gere Kiss, Thomas Wallet	On-The-Fly Model-Based Testing of Web Services with Jambition.	WS-FM	2008	DBLP DOI BibTeX RDF
4	Rob Kommeren, Päivi Parviainen	Philips experiences in global distributed software development.	Empir. Softw. Eng.	2007	DBLP DOI BibTeX RDF	Philips, Globally distributed software, Software development
4	Smruti R. Sarangi, Satish Narayanasamy, Bruce Carneal, Abhishek Tiwari 0002, Brad Calder, Josep Torrellas	Patching Processor Design Errors with Programmable Hardware.	IEEE Micro	2007	DBLP DOI BibTeX RDF	hardware errors, microarchitecture for fault-tolerance, design defects in real processors, processor errata analysis
4	Todd J. Foster, Dennis L. Lastor, Padmaraj Singh	First Silicon Functional Validation and Debug of Multicore Microprocessors.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
4	Renate Fruchter, Subashri Swaminathan, Manjunath Boraiah, Chhavi Upadhyay	Reflection in interaction.	AI Soc.	2007	DBLP DOI BibTeX RDF
4	Srinivasan Murali, Luca Benini, Giovanni De Micheli	An Application-Specific Design Methodology for On-Chip Crossbar Generation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
4	Sudeep Pasricha, Nikil D. Dutt	A Framework for Cosynthesis of Memory and Communication Architectures for MPSoC.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
4	Ilya Wagner, Valeria Bertacco, Todd M. Austin	Microprocessor Verification via Feedback-Adjusted Markov Models.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
4	Chris Seeling, Greg Watson, Kaiwei Sun	GPU-Based Interactive, Stereoscopic Visualization of Automotive Crash Simulations.	IEEE Computer Graphics and Applications	2007	DBLP DOI BibTeX RDF	stereoscopic visualization, crash simulations, automotive industry
4	Flávio Rech Wagner, Wander O. Cesário, Ahmed Amine Jerraya	Hardware/software IP integration using the ROSES design environment.	ACM Trans. Embed. Comput. Syst.	2007	DBLP DOI BibTeX RDF	IP integration, Systems-on-chip