Search results for "unrolling"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
12	Jongmyon Kim, D. Scott Wills, Linda M. Wills	Architectural Enhancements for Color Image and Video Processing on Embedded Systems.	Asia-Pacific Computer Systems Architecture Conference	2005	DBLP DOI BibTeX RDF
12	Chia-Hsien Liu, Tay-Jyi Lin, Chie-Min Chao, Pi-Chen Hsiao, Li-Chun Lin, Shin-Kai Chen, Chao-Wei Huang, Chih-Wei Liu, Chein-Wei Jen	Hierarchical instruction encoding for VLIW digital signal processors.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
12	Juho Lahti, Jari K. Juntunen, Olli Lehtoranta, Timo D. Hämäläinen	Algorithmic optimization of H.264/AVC encoder.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
12	Paris Kitsos, Michalis D. Galanis, Odysseas G. Koufopavlou	A RAM-based FPGA implementation of the 64-bit MISTY1 block cipher.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
12	Woongki Baek, Jihong Kim 0001	Load-store reordering for low-power multimedia data transfers.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
12	Sumio Morioka, Akashi Satoh	A 10-Gbps full-AES crypto design with a twisted BDD S-Box architecture.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
12	Sumit Gupta, Rajesh K. Gupta 0001, Nikil D. Dutt, Alexandru Nicolau	Coordinated parallelizing compiler optimizations and high-level synthesis.	ACM Trans. Design Autom. Electr. Syst.	2004	DBLP DOI BibTeX RDF	dynamic CSE, parallelizing transformations, presynthesis, embedded systems, high-level synthesis, Code motions, common subexpression elimination
12	Krishnan Srinivasan, Nagender Telkar, Vijay Ramamurthi, Karam S. Chatha	System-Level Design Techniques for Throughput and Power Optimization of Multiprocessor SoC Architectures.	ISVLSI	2004	DBLP DOI BibTeX RDF
12	Alireza Hodjat, Ingrid Verbauwhede	Minimum Area Cost for a 30 to 70 Gbits/s AES Processor.	ISVLSI	2004	DBLP DOI BibTeX RDF
12	Sumit Gupta, Nikil D. Dutt, Rajesh Gupta 0001, Alexandru Nicolau	Loop Shifting and Compaction for the High-Level Synthesis of Designs with Complex Control Flow.	DATE	2004	DBLP DOI BibTeX RDF
12	Huibin Shi, Chris Bailey 0002	Investigating Available Instruction Level Parallelism for Stack Based Machine Architectures.	DSD	2004	DBLP DOI BibTeX RDF
12	Peter Sanders 0001, Sebastian Winkel	Super Scalar Sample Sort.	ESA	2004	DBLP DOI BibTeX RDF
12	Michael Wolfe	Supercompilers, the AMD Opteron, and Your Cell Phone.	IPDPS	2004	DBLP DOI BibTeX RDF
12	Yosi Ben-Asher, Daniel Citron, Gadi Haber	Overlapping Memory Operations with Circuit Evaluation in Reconfigurable Computing.	IPDPS	2004	DBLP DOI BibTeX RDF
12	Alireza Hodjat, Ingrid Verbauwhede	A 21.54 Gbits/s Fully Pipelined AES Processor on FPGA.	FCCM	2004	DBLP DOI BibTeX RDF
12	David Zaretsky, Gaurav Mittal, Xiaoyong Tang, Prithviraj Banerjee	Overview of the FREEDOM Compiler for Mapping DSP Software to FPGAs.	FCCM	2004	DBLP DOI BibTeX RDF
12	Zhao-Hui Du, Chu-Cheow Lim, Xiao-Feng Li, Chen Yang, Qingyu Zhao, Tin-Fook Ngai	A cost-driven compilation framework for speculative parallelization of sequential programs.	PLDI	2004	DBLP DOI BibTeX RDF	cost-driven compilation, speculative parallel threading, loop transformation, thread-level speculation, speculative multithreading, speculative parallelization
12	Daijue Tang, Yinlei Yu, Darsh Ranjan, Sharad Malik	Analysis of Search Based Algorithms for Satisfiability of Propositional and Quantified Boolean Formulas Arising from Circuit State Space Diameter Problems.	SAT (Selected Papers	2004	DBLP DOI BibTeX RDF
12	Takahiro Katagiri, Kenji Kise, Hiroki Honda, Toshitsugu Yuba	Effect of auto-tuning with user's knowledge for numerical software.	Conf. Computing Frontiers	2004	DBLP DOI BibTeX RDF	eigensolver, performance modeling, parameter optimization, auto-tuning, numerical library
12	Qingda Lu, Xiaoyang Gao, Sriram Krishnamoorthy, Gerald Baumgartner, J. Ramanujam, P. Sadayappan	Empirical Performance-Model Driven Data Layout Optimization.	LCPC	2004	DBLP DOI BibTeX RDF
12	Roar Lien, Tim Grembowski, Kris Gaj	A 1 Gbit/s Partially Unrolled Architecture of Hash Functions SHA-1 and SHA-512.	CT-RSA	2004	DBLP DOI BibTeX RDF
12	Krishnan Srinivasan, Karam S. Chatha	An ILP Formulation for System Level Throughput and Power Optimization in Multiprocessor SoC Architectures.	VLSI Design	2004	DBLP DOI BibTeX RDF
12	François-Xavier Standaert, Siddika Berna Örs, Bart Preneel	Power Analysis of an FPGA: Implementation of Rijndael: Is Pipelining a DPA Countermeasure?	CHES	2004	DBLP DOI BibTeX RDF
12	Surendra Byna, Xian-He Sun, William Gropp, Rajeev Thakur	Predicting memory-access cost based on data-access patterns.	CLUSTER	2004	DBLP DOI BibTeX RDF
12	Peter M. W. Knijnenburg, Toru Kisuki, Michael F. P. O'Boyle	Combined Selection of Tile Sizes and Unroll Factors Using Iterative Compilation.	J. Supercomput.	2003	DBLP DOI BibTeX RDF	program transformation, instruction level parallelism, program optimization, locality optimization, adaptive compilation
12	Min Zhao 0009, Bruce R. Childers, Mary Lou Soffa	Predicting the impact of optimizations for embedded systems.	LCTES	2003	DBLP DOI BibTeX RDF	code models, embedded systems, prediction, optimizing compilers, loop optimizations, resource models, optimization models
12	Gregorio Bernabé, José M. García 0001, José González 0002	Reducing 3D Wavelet Transform Execution Time through the Streaming SIMD Extensions.	PDP	2003	DBLP DOI BibTeX RDF
12	Raphaël Montelatici	Polarized Proof Nets with Cycles and Fixpoints Semantics.	TLCA	2003	DBLP DOI BibTeX RDF
12	John S. Seng, Dean M. Tullsen	The Effect of Compiler Optimizations on Pentium 4 Power Consumption.	Interaction between Compilers and Computer Architectures	2003	DBLP DOI BibTeX RDF
12	Jirong Liao, Weng-Fai Wong, Tulika Mitra	A Model for Hardware Realization of Kernel Loops.	FPL	2003	DBLP DOI BibTeX RDF
12	Roni Rosner, Micha Moffie, Yiannakis Sazeides, Ronny Ronen	Selecting long atomic traces for high coverage.	ICS	2003	DBLP DOI BibTeX RDF	trace atomicity, trace processors, trace selection, trace cache
12	Takahiro Katagiri, Kenji Kise, Hiroaki Honda, Toshitsugu Yuba	FIBER: A Generalized Framework for Auto-tuning Software.	ISHPC	2003	DBLP DOI BibTeX RDF	Numerical library Eigensolver, Eigensolver, Performance modeling, Parameter optimization, Auto-Tuning
12	Jia Guo, María Jesús Garzarán, David A. Padua	The Power of Belady?s Algorithm in Register Allocation for Long Basic Blocks.	LCPC	2003	DBLP DOI BibTeX RDF
12	Pavel Tvrdík, Ivan Simecek	Analytical Modeling of Optimized Sparse Linear Code.	PPAM	2003	DBLP DOI BibTeX RDF
12	Marta Jiménez, José M. Llabería, Agustín Fernández	Register tiling in nonrectangular iteration spaces.	ACM Trans. Program. Lang. Syst.	2002	DBLP DOI BibTeX RDF	register level, locality, Data reuse, loop optimization, loop tiling
12	Yi Qian, Steve Carr 0001, Philip H. Sweany	Loop fusion for clustered VLIW architectures.	LCTES-SCOPES	2002	DBLP DOI BibTeX RDF	clustered VLIW architectures, loop fusion
12	Enric Gibert, F. Jesús Sánchez, Antonio González 0001	Effective instruction scheduling techniques for an interleaved cache clustered VLIW processor.	MICRO	2002	DBLP DOI BibTeX RDF
12	Bruno Blanchet, Patrick Cousot, Radhia Cousot, Jérôme Feret, Laurent Mauborgne, Antoine Miné, David Monniaux, Xavier Rival	Design and Implementation of a Special-Purpose Static Program Analyzer for Safety-Critical Real-Time Embedded Software.	The Essence of Computation	2002	DBLP DOI BibTeX RDF
12	Beniamino Di Martino, Nicola Mazzocca, Giacinto Paolo Saggese, Antonio G. M. Strollo	A Technique for FPGA Synthesis Driven by Automatic Source Code Analysis and Transformations.	FPL	2002	DBLP DOI BibTeX RDF
12	Heidi E. Ziegler, Byoungro So, Mary W. Hall, Pedro C. Diniz	Coarse-Grain Pipelining on Multiple FPGA Architectures.	FCCM	2002	DBLP DOI BibTeX RDF	Coarse-grain Pipelining, FPGA-based Custom Computing Machines, Parallelizing Compiler Analysis Techniques
12	Hisayasu Kuroda, Takahiro Katagiri, Yasumasa Kanada	Knowledge Discovery in Auto-tuning Parallel Numerical Library.	Progress in Discovery Science	2002	DBLP DOI BibTeX RDF
12	Farzan Fallah	Binary time-frame expansion.	ICCAD	2002	DBLP DOI BibTeX RDF
12	Mário P. Véstias, Horácio C. Neto	System-Level Co-Synthesis of Dataflow Dominated Applications on Reconfigurable Hardware/Software Architectures.	IEEE International Workshop on Rapid System Prototyping	2002	DBLP DOI BibTeX RDF
12	Xiaohua Hu 0001	Comparison of Classification Methods for Customer Attrition Analysis.	Rough Sets and Current Trends in Computing	2002	DBLP DOI BibTeX RDF
12	Haifeng Zhou, Zhenghui Lin, Wei Cao	Research on VHDL RTL Synthesis System.	DELTA	2002	DBLP DOI BibTeX RDF	VHDL RTL synthesis, ambiguous grammar, language level optimization, inference, formal semantics, parser
12	Rajeev Barua, Walter Lee, Saman P. Amarasinghe, Anant Agarwal	Compiler Support for Scalable and Efficient Memory Systems.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	bank disambiguation, memory parallelism, Raw, Compiler, Maps, memory
12	Matthew C. Merten, Andrew R. Trick, Ronald D. Barnes, Erik M. Nystrom, Christopher N. George, John C. Gyllenhaal, Wen-mei W. Hwu	An Architectural Framework for Runtime Optimization.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	Postlink optimization, hardware profiling, low-overhead profiling, program hot spot, partial function inlining, trace formation and optimization, dynamic optimization, runtime optimization, code layout
12	Gautam Doshi, Rakesh Krishnaiyer, Kalyan Muthukumar	Optimizing Software Data Prefetches with Rotating Registers.	IEEE PACT	2001	DBLP DOI BibTeX RDF
12	Karam S. Chatha, Ranga Vemuri	MAGELLAN: multiway hardware-software partitioning and scheduling for latency minimization of hierarchical control-dataflow task graphs.	CODES	2001	DBLP DOI BibTeX RDF
12	Ying Zhao, Sharad Malik	Exact memory size estimation for array computations.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
12	Jian Huang, David J. Lilja	Extending Value Reuse to Basic Blocks with Compiler Support.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	Block history buffer, block reuse, compiler flow analysis, value reuse, value locality
12	Miodrag Potkonjak, Jan M. Rabaey	Maximally and arbitrarily fast implementation of linear andfeedback linear computations.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
12	Brian Grant, Markus Mock, Matthai Philipose, Craig Chambers, Susan J. Eggers	The benefits and costs of DyC's run-time optimizations.	ACM Trans. Program. Lang. Syst.	2000	DBLP DOI BibTeX RDF	specialization, dynamic compilation
12	Toru Kisuki, Peter M. W. Knijnenburg, Michael F. P. O'Boyle	Combined Selection of Tile Sizes and Unroll Factors Using Iterative Compilation.	IEEE PACT	2000	DBLP DOI BibTeX RDF
12	Gang-Ryung Uh, Yuhong Wang, David B. Whalley, Sanjay Jinturkar, Chris Burns, Vincent Cao	Techniques for Effectively Exploiting a Zero Overhead Loop Buffer.	CC	2000	DBLP DOI BibTeX RDF
12	Dexter Kozen, Maria-Christina Patron	Certification of Compiler Optimizations Using Kleene Algebra with Tests.	Computational Logic	2000	DBLP DOI BibTeX RDF
12	Suhyun Kim, Soo-Mook Moon, Jinpyo Park, Kemal Ebcioglu	Unroll-based register coalescing.	ICS	2000	DBLP DOI BibTeX RDF
12	G. Esakkimuthu, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin	Memory system energy (poster session): influence of hardware-software optimizations.	ISLPED	2000	DBLP DOI BibTeX RDF
12	Dirk W. Hoffmann, Thomas Kropf	Efficient Design Error Correction of Digital Circuits.	ICCD	2000	DBLP DOI BibTeX RDF
12	Michael Voss, Rudolf Eigenmann	ADAPT: Automated De-Coupled Adaptive Program Transformation.	ICPP	2000	DBLP DOI BibTeX RDF
12	Howard Cheng, Eugene V. Zima	On accelerated methods to evaluate sums of products of rational numbers.	ISSAC	2000	DBLP DOI BibTeX RDF	binary splitting, chains of recurrences, representation of integers
12	Ganesh Lakshminarayana, Kamal S. Khouri, Niraj K. Jha	Wavesched: a novel scheduling technique for control-flow intensive designs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
12	Gang-Ryung Uh, Yuhong Wang, David B. Whalley, Sanjay Jinturkar, Chris Burns, Vincent Cao	Effective Exploitation of a Zero Overhead Loop Buffer.	Workshop on Languages, Compilers, and Tools for Embedded Systems	1999	DBLP DOI BibTeX RDF
12	Derek L. Howard, Mikko H. Lipasti	The Effect of Program Optimization on Trace Cache Efficiency.	IEEE PACT	1999	DBLP DOI BibTeX RDF	compiler optimization, Microarchitecture, superscalar processors, trace cache
12	Pranav Ashar, Anand Raghunathan, Aarti Gupta, Subhrajit Bhattacharya	Verification of Scheduling in the Presence of Loops Using Uninterpreted Symbolic Simulation.	ICCD	1999	DBLP DOI BibTeX RDF
12	Suhyun Kim, Soo-Mook Moon, Jinpyo Park, Han-Saem Yun	Unroll-Based Copy Elimination for Enhanced Pipeline Scheduling.	LCPC	1999	DBLP DOI BibTeX RDF
12	Rajeev Barua, Walter Lee, Saman P. Amarasinghe, Anant Agarwal	Maps: A Compiler-Managed Memory System for Raw Machines.	ISCA	1999	DBLP DOI BibTeX RDF
12	Jens-Peter Kaps, Christof Paar	Fast DES Implementation for FPGAs and Its Application to a Universal Key-Search Machine.	Selected Areas in Cryptography	1998	DBLP DOI BibTeX RDF
12	Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha	IMPACT: A High-Level Synthesis System for Low Power Control-Flow Intensive Circuits.	DATE	1998	DBLP DOI BibTeX RDF	multiplexer re-structuring, low power, high-level synthesis, resource sharing, control-flow, module selection
12	Volker Braun, Jens Knoop, Dirk Koschützki	Cool: A Control-Flow Generator for System Analysis.	CC	1998	DBLP DOI BibTeX RDF
12	David J. Kolson, Alexandru Nicolau, Nikil D. Dutt	Copy Elimination for Parallelizing Compilers.	LCPC	1998	DBLP DOI BibTeX RDF
12	Mihnea Marinescu, Benjamin Goldberg	Partial-Evaluation Techniques for Concurrent Programs.	PEPM	1997	DBLP DOI BibTeX RDF	concurrency, CSP, CSP, partial evaluation, nondeterminism, binding-time analysis
12	Steve Carr 0001, Yiping Guan	Unroll-and-Jam Using Uniformly Generated Sets.	MICRO	1997	DBLP DOI BibTeX RDF	Instruction-Level Parallelism, Loop Optimization
12	Huzefa Mehta, Robert Michael Owens, Mary Jane Irwin	A Simulation Methodology for Software Energy Evaluation.	VLSI Design	1997	DBLP DOI BibTeX RDF
12	M. Anton Ertl, Andreas Krall	Removing Anti Dependences by Repairing.	CC	1996	DBLP DOI BibTeX RDF	anti dependence, instruction-level parallelism, speculative execution, repairing, register renaming
12	Marta Jiménez, José M. Llabería, Agustín Fernández, Enric Morancho	A Unified Transformation Technique for Multilevel Blocking.	Euro-Par, Vol. I	1996	DBLP DOI BibTeX RDF
12	John D. McCalpin, Mark Smotherman	Automatic benchmark generation for cache optimization of matrix operations.	ACM Southeast Regional Conference	1995	DBLP DOI BibTeX RDF
12	Jack L. Lo, Susan J. Eggers	Improving Balanced Scheduling with Compiler Optimizations that Increase Instruction-Level Parallelism.	PLDI	1995	DBLP DOI BibTeX RDF
12	Tan-Li Chou, Kaushik Roy 0001	Estimation of sequential circuit activity considering spatial and temporal correlations.	ICCD	1995	DBLP DOI BibTeX RDF	sequential circuit activity estimation, signal activity, internal nodes, sequential logic circuits, logic signals, ESTG, extended state transition graph, exact signal probabilities, large circuits, state logic, logic simulation results, graph theory, finite state machines, finite state machine, sequential circuits, spatial correlations, circuit switching, switching activities, approximate method, temporal correlations
12	Michel J. Daydé, Iain S. Duff, Antoine Petitet	A parallel block implementation of Level-3 BLAS for MIMD vector processors.	ACM Trans. Math. Softw.	1994	DBLP DOI BibTeX RDF	matrix-matrix kernels, parallelization, vectorization, Level-3 BLAS
12	Stefan M. Freudenberger, Thomas R. Gross, P. Geoffrey Lowney	Avoidance and Suppression of Compensation Code in a Trace Scheduling Compiler.	ACM Trans. Program. Lang. Syst.	1994	DBLP DOI BibTeX RDF	SPEC89, performance evaluation, instruction-level parallelism, trace scheduling
12	Stephen Weeks, Matthias Felleisen	On the Orthogonality of Assignments and Procedures in Algol.	POPL	1993	DBLP DOI BibTeX RDF	ALGOL-60, ALGOL
12	Evelyn Duesterwald, Rajiv Gupta 0001, Mary Lou Soffa	A Practical Data Flow Framework for Array Reference Analysis and its Use in Optimizations.	PLDI	1993	DBLP DOI BibTeX RDF
12	Laurie J. Hendren, Guang R. Gao	Designing programming languages for analyzability: a fresh look at pointer data structures.	ICCL	1992	DBLP DOI BibTeX RDF
12	Toshio Nakatani, Kemal Ebcioglu	"Combining" as a compilation technique for VLIW architectures.	MICRO	1989	DBLP DOI BibTeX RDF
12	François Bodin, François Charot, Charles Wagner	Overview of a high-performance programmable pipeline structure.	ICS	1989	DBLP DOI BibTeX RDF
12	James C. Dehnert, Peter Y.-T. Hsu, Joseph P. Bratt	Overlapped Loop Support in the Cydra 5.	ASPLOS	1989	DBLP DOI BibTeX RDF	Cydra 5
12	Jeanne Ferrante, Karl J. Ottenstein, Joe D. Warren	The Program Dependence Graph and Its Use in Optimization.	ACM Trans. Program. Lang. Syst.	1987	DBLP DOI BibTeX RDF
12	James A. Davis	A functional language architecture that supports fine-grain parallelism (extended abstract).	ACM Conference on Computer Science	1987	DBLP DOI BibTeX RDF