Search results for "ATS"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Jenny Fan, Xiao-Yu Li, Ismed Hartanto	Using FPGA configuration memory to accelerate yield learning for advanced process.	ATS	2007	DBLP DOI BibTeX RDF
1	Sunghoon Chun, YongJoon Kim, Sungho Kang 0001	High-MDSI: A High-level Signal Integrity Fault Test Pattern Generation Method for Interconnects.	ATS	2007	DBLP DOI BibTeX RDF
1	Meng-Fan Wu, Kai-Shun Hu, Jiun-Lang Huang	An Efficient Peak Power Reduction Technique for Scan Testing.	ATS	2007	DBLP DOI BibTeX RDF
1	Hsiang-Huang Wu, Jin-Fu Li 0001, Chi-Feng Wu, Cheng-Wen Wu	CAMEL: An Efficient Fault Simulator with Coupling Fault Simulation Enhancement for CAMs.	ATS	2007	DBLP DOI BibTeX RDF
1	Brion L. Keller, Anis Uzzaman, Bibo Li, Thomas J. Snethen	Using Programmable On-Product Clock Generation (OPCG) for Delay Test.	ATS	2007	DBLP DOI BibTeX RDF
1	Xiaoqing Yang, Jinian Bian, Shujun Deng, Yanni Zhao	EHSAT Modeling from Algorithm Description for RTL Model Checking.	ATS	2007	DBLP DOI BibTeX RDF
1	Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu	Test Generation for Transistor Shorts using Stuck-at Fault Simulator and Test Generator.	ATS	2007	DBLP DOI BibTeX RDF
1	Thomas Edison Yu, Tomokazu Yoneda, Krishnendu Chakrabarty, Hideo Fujiwara	Thermal-Safe Test Access Mechanism and Wrapper Co-optimization for System-on-Chip.	ATS	2007	DBLP DOI BibTeX RDF
1	Shawn Molavi, Toby McPheeters	Concurrent Test Implementations.	ATS	2007	DBLP DOI BibTeX RDF
1	Hung-Kai Chen 0001, Chauchin Su	A Test and Diagnosis Methodology for RF Transceivers.	ATS	2007	DBLP DOI BibTeX RDF
1	Jian Kang, Sharad C. Seth, Shashank K. Mehta	Symbolic Path Sensitization Analysis and Applications.	ATS	2007	DBLP DOI BibTeX RDF
1	Tong-Yu Hsieh, Kuen-Jong Lee, Jian-Jhih You	Test Efficiency Analysis and Improvement of SOC Test Platforms.	ATS	2007	DBLP DOI BibTeX RDF
1	Yu Huang 0005, Nilanjan Mukherjee 0001, Wu-Tung Cheng, Greg Aldrich	A RTL Testability Analyzer Based on Logical Virtual Prototyping.	ATS	2007	DBLP DOI BibTeX RDF
1	Yu Wei P'ng, Moo Kit Lee, Peng Weng Ng, Chin Hu Ong	IDDQ Test Challenges in Nanotechnologies: A Manufacturing Test Strategy.	ATS	2007	DBLP DOI BibTeX RDF
1	Yuki Yoshikawa, Satoshi Ohtake, Hideo Fujiwara	False Path Identification using RTL Information and Its Application to Over-testing Reduction for Delay Faults.	ATS	2007	DBLP DOI BibTeX RDF
1		16th Asian Test Symposium, ATS 2007, Beijing, China, October 8-11, 2007	ATS	2007	DBLP DOI BibTeX RDF
1	Xiaoxin Fan, Yu Hu 0001, Laung-Terng Wang	An On-Chip Test Clock Control Scheme for Multi-Clock At-Speed Testing.	ATS	2007	DBLP DOI BibTeX RDF
1	Minjin Zhang, Xiaowei Li 0001	Test Generation for Crosstalk Glitches Considering Multiple Coupling Effects.	ATS	2007	DBLP DOI BibTeX RDF
1	David Bement, David Karr	Bluetooth Hopping BER Testing Methodologies on a Production Test Platform.	ATS	2007	DBLP DOI BibTeX RDF
1	Bo-Hua Chen, Wei-Chung Kao, Bing-Chuan Bai, Shyue-Tsong Shen, James C.-M. Li	Response Inversion Scan Cell (RISC): A Peak Capture Power Reduction Technique.	ATS	2007	DBLP DOI BibTeX RDF
1	Dongwoo Hong, Kwang-Ting Cheng	An Accurate Jitter Estimation Technique for Efficient High Speed I/O Testing.	ATS	2007	DBLP DOI BibTeX RDF
1	Piet Engelke, Bettina Braitling, Ilia Polian, Michel Renovell, Bernd Becker 0001	SUPERB: Simulator Utilizing Parallel Evaluation of Resistive Bridges.	ATS	2007	DBLP DOI BibTeX RDF
1	Friedrich Taenzler	Production Test of High Volume Commercial RFIC.	ATS	2007	DBLP DOI BibTeX RDF
1	Jaehoon Song, Juhee Han, Dooyoung Kim, Hyunbean Yi, Sungju Park	Design Reuse of on/off-Chip Bus Bridge for Efficient Test Access to AMBA-based SoC.	ATS	2007	DBLP DOI BibTeX RDF
1	Kary Chien	Invited Talk 3: Foundry Full-Scale Reliability Testing Capability Setup for Advanced Technology.	ATS	2007	DBLP DOI BibTeX RDF
1	Huaxing Tang, Chen Liu, Wu-Tung Cheng, Sudahkar M. Reddy, Wei Zou	Improving Performance of Effect-Cause Diagnosis with Minimal Memory Overhead.	ATS	2007	DBLP DOI BibTeX RDF
1	Elham K. Moghaddam, Shaahin Hessabi	An On-Line BIST Technique for Delay Fault Detection in CMOS Circuits.	ATS	2007	DBLP DOI BibTeX RDF
1	Monalisa Sarma, Rajib Mall	System Testing using UML Models.	ATS	2007	DBLP DOI BibTeX RDF
1	Shaohua Lei, Yinhe Han 0001, Xiaowei Li 0001	Frequency Analysis Method for Propagation of Transient Errors in Combinational Logic.	ATS	2007	DBLP DOI BibTeX RDF
1	Aiman H. El-Maleh, Mustafa Imran Ali, Ahmad A. Al-Yamani	A Reconfigurable Broadcast Scan Compression Scheme Using Relaxation Based Test Vector Decompos.	ATS	2007	DBLP DOI BibTeX RDF
1	Tomokazu Yoneda, Yuusuke Fukuda, Hideo Fujiwara	Test Scheduling for Memory Cores with Built-In Self-Repair.	ATS	2007	DBLP DOI BibTeX RDF
1	Magali Bastian, Vincent Gouin, Patrick Girard 0001, Christian Landrault, Alexandre Ney, Serge Pravossoudovitch, Arnaud Virazel	Influence of Threshold Voltage Deviations on 90nm SRAM Core-Cell Behavior.	ATS	2007	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	Enhanced Broadside Testing for Improved Transition Fault Coverage.	ATS	2007	DBLP DOI BibTeX RDF
1	Xijiang Lin, Mark Kassab, Janusz Rajski	Test Generation for Timing-Critical Transition Faults.	ATS	2007	DBLP DOI BibTeX RDF
1	Ruifeng Guo, Yu Huang 0005, Wu-Tung Cheng	Fault Dictionary Based Scan Chain Failure Diagnosis.	ATS	2007	DBLP DOI BibTeX RDF
1	Fidel Muradali, Jochen Rivoir	Special Session: Analog Production Test.	ATS	2007	DBLP DOI BibTeX RDF
1	Mahshid Sedghi, Armin Alaghi, Elnaz Koopahi, Zainalabedin Navabi	An HDL-Based Platform for High Level NoC Switch Testing.	ATS	2007	DBLP DOI BibTeX RDF
1	Deng Yue	Understanding GSM/EDGE Modulated Signal Test on Cellular BB SOC.	ATS	2007	DBLP DOI BibTeX RDF
1	T. W. Williams	Invited Talk 2: EDA to the Rescue of the Silicon Roadmap.	ATS	2007	DBLP DOI BibTeX RDF
1	Wataru Kawamura, Takeshi Onodera	Experimental Results of Transition Fault Simulation with DC Scan Tests.	ATS	2007	DBLP DOI BibTeX RDF
1	Majid Nabi, Hamid Shojaei, Siamak Mohammadi, Zainalabedin Navabi	Optimized Assignment Coverage Computation in Formal Verification of Digital Systems.	ATS	2007	DBLP DOI BibTeX RDF
1	Ramashis Das, John P. Hayes	Monitoring Transient Errors in Sequential Circuits.	ATS	2007	DBLP DOI BibTeX RDF
1	Stefan Spinner, Jie Jiang 0018, Ilia Polian, Piet Engelke, Bernd Becker 0001	Simulating Open-Via Defects.	ATS	2007	DBLP DOI BibTeX RDF
1	T. M. Mak	Invited Talk 1: Testing of Power Constraint Computing.	ATS	2007	DBLP DOI BibTeX RDF
1	Masaki Hashizume, Yutaka Hata, Tomomi Nishida, Hiroyuki Yotsuyanagi, Yukiya Miura	Current Testable Design of Resistor String DACs.	ATS	2007	DBLP DOI BibTeX RDF
1	Hideyuki Ichihara, Yukinori Setohara, Yusuke Nakashima, Tomoo Inoue	Test Compression / Decompression Based on JPEG VLC Algorithm.	ATS	2007	DBLP DOI BibTeX RDF
1	Weixin Wu, Michael S. Hsiao	Mining Sequential Constraints for Pseudo-Functional Testing.	ATS	2007	DBLP DOI BibTeX RDF
1	Shiyi Xu	Reconsideration of Software Reliability Measurements.	ATS	2007	DBLP DOI BibTeX RDF
1	Urban Ingelsson, Paul M. Rosinger, S. Saqib Khursheed, Bashir M. Al-Hashimi, Peter Harrod	Resistive Bridging Faults DFT with Adaptive Power Management Awareness.	ATS	2007	DBLP DOI BibTeX RDF
1	Hsieh-Hung Hsieh, Yen-Chih Huang, Liang-Hung Lu, Guo-Wei Huang	A BIST Technique for RF Voltage-Controlled Oscillators.	ATS	2007	DBLP DOI BibTeX RDF
1	Yu Huang 0005, Xijiang Lin	Programmable Logic BIST for At-speed Test.	ATS	2007	DBLP DOI BibTeX RDF
1	Florence Azaïs, Laurent Larguier, Michel Renovell	Impact of Simultaneous Switching Noise on the Static behavior of Digital CMOS Circuits.	ATS	2007	DBLP DOI BibTeX RDF
1	Selim Sermet Akbay, Shreyas Sen, Abhijit Chatterjee	Testing RF Components with Supply Current Signatures.	ATS	2007	DBLP DOI BibTeX RDF
1	Ganesh Srinivasan, Abhijit Chatterjee, Vishwanath Natarajan	Fourier Spectrum-Based Signature Test: A Genetic CAD Toolbox for Reliable RF Testing Using Low-Performance Test Resources.	ATS	2007	DBLP DOI BibTeX RDF
1	Chunsheng Liu, Yang Wu, Yu Huang 0005	Effect of IR-Drop on Path Delay Testing Using Statistical Analysis.	ATS	2007	DBLP DOI BibTeX RDF
1	Xinsong Zhang, Simon S. Ang, Chandra Carter	Test Point Selections for a Programmable Gain Amplifier Using NIST and Wavelet Transform Methods.	ATS	2007	DBLP DOI BibTeX RDF
1	Chandan Giri, Pradeep Kumar Choudhary, Santanu Chattopadhyay	Scan Power Reduction Through Scan Architecture Modification And Test Vector Reordering.	ATS	2007	DBLP DOI BibTeX RDF
1	Nai-Chen Daniel Cheng, Yu Lee, Ji-Jan Chen	A 2-ps Resolution Wide Range BIST Circuit for Jitter Measurement.	ATS	2007	DBLP DOI BibTeX RDF
1	Alexandre Rousset, Alberto Bosio, Patrick Girard 0001, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel	Fast Bridging Fault Diagnosis using Logic Information.	ATS	2007	DBLP DOI BibTeX RDF
1	Jin-Fu Li 0001	Testing Comparison Faults of Ternary Content Addressable Memories with Asymmetric Cells.	ATS	2007	DBLP DOI BibTeX RDF
1	Shahdad Irajpour, Sandeep K. Gupta 0001, Melvin A. Breuer	Improving Timing-Independent Testing of Crosstalk Using Realistic Assumptions on Delay Faults.	ATS	2007	DBLP DOI BibTeX RDF
1	Liyang Lai, Wu-Tung Cheng, Thomas Rinderknecht	Programmable Scan-Based Logic Built-In Self Test.	ATS	2007	DBLP DOI BibTeX RDF
1	Stephan Eggersglüß, Rolf Drechsler	Improving Test Pattern Compactness in SAT-based ATPG.	ATS	2007	DBLP DOI BibTeX RDF
1	Seongmoon Wang, Wenlong Wei, Srimat T. Chakradhar	A High Compression and Short Test Sequence Test Compression Technique to Enhance Compressions of LFSR Reseeding.	ATS	2007	DBLP DOI BibTeX RDF
1	Yasuharu Kohiyama, C. P. Ravikumar, Yasuo Sato, Laung-Terng Wang, Yervant Zorian	Next Generation Test, Diagnostics and Yield Challenges for EDA, ATE, IP and Fab - A Perspective from All Sides.	ATS	2007	DBLP DOI BibTeX RDF
1	Takahiro J. Yamaguchi	Top 5 Issues in Practical Testing of High-Speed Interface Devices.	ATS	2007	DBLP DOI BibTeX RDF
1	Krishna Chakravadhanula, Nitin Parimi, Brian Foutz, Bing Li, Vivek Chickermane	Low Power Reduced Pin Count Test Methodology.	ATS	2007	DBLP DOI BibTeX RDF
1	Mingjing Chen, Alex Orailoglu	Improving Circuit Robustness with Cost-Effective Soft-Error-Tolerant Sequential Elements.	ATS	2007	DBLP DOI BibTeX RDF
1	Sean Lu, Dee-Won Lee	Integrated Test Solution for embedded UHF/RF SOC.	ATS	2007	DBLP DOI BibTeX RDF
1	Livier Lizarraga, Salvador Mir, Gilles Sicard	Evaluation of a BIST Technique for CMOS Imagers.	ATS	2007	DBLP DOI BibTeX RDF
1	Anis Uzzaman, Fidel Muradali, Takashi Aikyo, Robert C. Aitken, Tom Jackson, Rajesh Galivanche, Takeshi Onodera	Test Roles in Diagnosis and Silicon Debug.	ATS	2007	DBLP DOI BibTeX RDF
1	Wu Yang, Wu-Tung Cheng, Yu Huang 0005, Martin Keim, Randy Klingenberg	Scan Diagnosis and Its Successful Industrial Applications.	ATS	2007	DBLP DOI BibTeX RDF
1	Akinori Maeda	How the noise floor affects the production yield.	ATS	2007	DBLP DOI BibTeX RDF
1	Liquan Fang, Yang Zhong, H. van de Donk, Yizi Xing	Implementation of Defect Oriented Testing and ICCQ testing for industrial mixed-signal IC.	ATS	2007	DBLP DOI BibTeX RDF
1	Feijun Zheng, Kwang-Ting Cheng, Xiaolang Yan, John Moondanos, Ziyad Hanna	An Efficient Diagnostic Test Pattern Generation Framework Using Boolean Satisfiability.	ATS	2007	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Praveen Parvathala, Srinivas Patil	Estimating the Fault Coverage of Functional Test Sequences Without Fault Simulation.	ATS	2007	DBLP DOI BibTeX RDF
1	Feng-An Qian, Jian-Hui Jiang	An Improved Test Case Generation Method of Pair-Wise Testing.	ATS	2007	DBLP DOI BibTeX RDF
1	Sanjiv Taneja	Keynote Speech 2: Consumerization of Electronics and Nanometer Technologies: Implications on Test.	ATS	2007	DBLP DOI BibTeX RDF
1	Brion L. Keller, Tom Jackson, Anis Uzzaman	A Review of Power Strategies for DFT and ATPG.	ATS	2007	DBLP DOI BibTeX RDF
1	Hsuan-Jung Hsu, Chun-Chieh Tu, Shi-Yu Huang	Built-In Speed Grading with a Process-Tolerant ADPLL.	ATS	2007	DBLP DOI BibTeX RDF
1	I-De Huang, Sandeep K. Gupta 0001	On Generating Vectors That Invoke High Circuit Delays - Delay Testing and Dynamic Timing Analysis.	ATS	2007	DBLP DOI BibTeX RDF
1	Li-Ming Denq, Cheng-Wen Wu	A Hybrid BIST Scheme for Multiple Heterogeneous Embedded Memories.	ATS	2007	DBLP DOI BibTeX RDF
1	Dong Xiang, Krishnendu Chakrabarty, Dianwei Hu, Hideo Fujiwara	Scan Testing for Complete Coverage of Path Delay Faults with Reduced Test Data Volume, Test Application Time, and Hardware Cost.	ATS	2007	DBLP DOI BibTeX RDF
1	Sying-Jyan Wang, Xin-Long Li, Katherine Shu-Min Li	Layout-Aware Multi-Layer Multi-Level Scan Tree Synthesis.	ATS	2007	DBLP DOI BibTeX RDF
1	Hafizur Rahaman 0001, Dipak Kumar Kole, Debesh K. Das, Bhargab B. Bhattacharya	Optimum Test Set for Bridging Fault Detection in Reversible Circuits.	ATS	2007	DBLP DOI BibTeX RDF
1	Jochen Rivoir	Fast and Low Cost HW Bit Map for Memory Test Based on Residue Polynomial System over GF(2).	ATS	2007	DBLP DOI BibTeX RDF
1	Sying-Jyan Wang, Po-Chang Tsai, Hung-Ming Weng, Katherine Shu-Min Li	Test Data and Test Time Reduction for LOS Transition Test in Multi-Mode Segmented Scan Architecture.	ATS	2007	DBLP DOI BibTeX RDF
1	Haihua Shen, Heng Zhang	An Accurate Analysis of Microprocessor Design Verification.	ATS	2007	DBLP DOI BibTeX RDF
1	Nan-Cheng Lai, Sying-Jyan Wang	Low-Capture-Power Test Generation by Specifying A Minimum Set of Controlling Inputs.	ATS	2007	DBLP DOI BibTeX RDF
1	Toshinori Hosokawa, Ryoichi Inoue, Hideo Fujiwara	Fault-dependent/independent Test Generation Methods for State Observable FSMs.	ATS	2007	DBLP DOI BibTeX RDF
1	Jacob Abraham, Salvador Mir, Yinghua Min, Jeremy Wang, Cheng-Wen Wu	Test Education in the Global Economy.	ATS	2007	DBLP DOI BibTeX RDF
1	Hiroshi Takahashi, Yoshinobu Higami, Shuhei Kadoyama, Takashi Aikyo, Yuzo Takamatsu, Koji Yamazaki, Toshiyuki Tsutsumi, Hiroyuki Yotsuyanagi, Masaki Hashizume	Clues for Modeling and Diagnosing Open Faults with Considering Adjacent Lines.	ATS	2007	DBLP DOI BibTeX RDF
1	Yukiya Miura	Detection of Interconnect Open Faults with Unknown Values by Ramp Voltage Application.	ATS	2006	DBLP DOI BibTeX RDF
1	Jinkyu Lee 0005, Nur A. Touba	Efficiently Utilizing ATE Vector Repeat for Compression by Scan Vector Decomposition.	ATS	2006	DBLP DOI BibTeX RDF
1	Tao Lv 0001, Ling-Yi Liu, Yang Zhao, Huawei Li 0001, Xiaowei Li 0001	An Observability Branch Coverage Metric Based on Dynamic Factored Use-Define Chains.	ATS	2006	DBLP DOI BibTeX RDF
1	Paul Wong, Jing Jiang	How to Perform DFT Timing in Mixed Signal Designs, from 28 Hours to 7 Minutes.	ATS	2006	DBLP DOI BibTeX RDF
1	Sanae Seike, Ken Namura, Yukio Ohya, Anis Uzzaman, Shinichi Arima, Dale Meehl, Vivek Chickermane, Azumi Kobayashi, Satoshi Tanaka, Hiroyuki Adachi	Early Life Cycle Yield Learning for Nanometer Devices Using Volume Yield Diagnostics Analysis.	ATS	2006	DBLP DOI BibTeX RDF
1	Po-Chang Tsai, Sying-Jyan Wang	Multi-Mode Segmented Scan Architecture with Layout-Aware Scan Chain Routing for Test Data and Test Time Reduction.	ATS	2006	DBLP DOI BibTeX RDF
1	Dhiraj Goswami, Kun-Han Tsai, Mark Kassab, Takeo Kobayashi, Janusz Rajski, Bruce Swanson, Darryl Walters, Yasuo Sato, Toshiharu Asaka, Takashi Aikyo	At-Speed Testing with Timing Exceptions and Constraints-Case Studies.	ATS	2006	DBLP DOI BibTeX RDF
1	Taweesak Reungpeerakul, Xiaoshu Qian, Samiha Mourad	BCH-based Compactors of Test Responses with Controllable Masks.	ATS	2006	DBLP DOI BibTeX RDF

Publications at "ATS"( http://dblp.L3S.de/Venues/ATS )