Search results for "Clocking"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
10	Kyosun Kim, Kaijie Wu 0001, Ramesh Karri	The Robust QCA Adder Designs Using Composable QCA Building Blocks.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
10	Simon Ogg, Enrico Valli, Crescenzo D'Alessandro, Alexandre Yakovlev, Bashir M. Al-Hashimi, Luca Benini	Reducing Interconnect Cost in NoC through Serialized Asynchronous Links.	NOCS	2007	DBLP DOI BibTeX RDF
10	Craig A. Stewart, Malinda Lingwall, David A. Bader	Lecture on Progress toward Petascale Applications in Bioinformatics and Computational Biology.	BIBE	2007	DBLP DOI BibTeX RDF
10	Bernhard Fechner, Andre Osterloh	Transient Fault Detection in State-Automata.	DepCoS-RELCOMEX	2007	DBLP DOI BibTeX RDF
10	Timothy Johnson, Umesh Nawathe	An 8-core, 64-thread, 64-bit power efficient sparc soc (niagara2).	ISPD	2007	DBLP DOI BibTeX RDF
10	Anna Richelli, Luca Mensi, Luigi Colalongo, Zsolt Miklós Kovács-Vajna, Pier Luigi Rolandi	A 1.2V-5V High Efficiency CMOS Charge Pump for Non-Volatile Memories.	ISCAS	2007	DBLP DOI BibTeX RDF
10	Héctor Pettenghi, Maria J. Avedillo, José M. Quintana	Non Return Mobile Logic Family.	ISCAS	2007	DBLP DOI BibTeX RDF
10	Yuxin Wang, Zeljko Ignjatovic	On-Chip Substrate Noise Suppression Using Clock Randomization Methodology.	ISCAS	2007	DBLP DOI BibTeX RDF
10	Amit Mondal, Aleksandar Kuzmanovic	A Poisoning-Resilient TCP Stack.	ICNP	2007	DBLP DOI BibTeX RDF
10	Ismo Hänninen, Jarmo Takala	Robust Adders Based on Quantum-Dot Cellular Automata.	ASAP	2007	DBLP DOI BibTeX RDF
10	Masaru Fukushi, Susumu Horiguchi, Luke Demoracski, Fabrizio Lombardi	A Scalable Framework for Defect Isolation of DNA Self-assemlbled Networks.	DFT	2007	DBLP DOI BibTeX RDF
10	Kathi Fisler	Two-Dimensional Regular Expressions for Compositional Bus Protocols.	FMCAD	2007	DBLP DOI BibTeX RDF
10	Nabil Hasasneh, Ian M. Bell, Chris R. Jesshope	High Level Modelling and Design For a Microthreaded Scheduler to Support Microgrids.	AICCSA	2007	DBLP DOI BibTeX RDF
10	Hisako Adachi, Shinji Nakamura	Efficient Designs for Adder Comparator.	CISS	2007	DBLP DOI BibTeX RDF
10	Rostislav (Reuven) Dobkin, Ran Ginosar, Christos P. Sotiriou	High Rate Data Synchronization in GALS SoCs.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
10	Marco Ottavi, Luca Schiano, Fabrizio Lombardi, Douglas Tougaw	HDLQ: A HDL environment for QCA design.	ACM J. Emerg. Technol. Comput. Syst.	2006	DBLP DOI BibTeX RDF	CAD, fault injection, QCA, HDL
10	Chidamber Kulkarni, Gordon J. Brebner	Memory centric thread synchronization on platform FPGAs.	DATE	2006	DBLP DOI BibTeX RDF
10	Mikkel Bystrup Stensgaard, Tobias Bjerregaard, Jens Sparsø, Johnny Halkjær Pedersen	A Simple Clockless Network-on-Chip for a Commercial Audio DSP Chip.	DSD	2006	DBLP DOI BibTeX RDF
10	Nobuo Karaki	Asynchronous Design: An Enabler for Flexible Microelectronics.	ASYNC	2006	DBLP DOI BibTeX RDF
10	Shih-Hsu Huang, Chia-Ming Chang 0002, Yow-Tyng Nieh	Fast multi-domain clock skew scheduling for peak current reduction.	ASP-DAC	2006	DBLP DOI BibTeX RDF
10	Navneeth Kankani, Vineet Agarwal, Janet Meiling Wang	A probabilistic analysis of pipelined global interconnect under process variations.	ASP-DAC	2006	DBLP DOI BibTeX RDF
10	Matthias Függer, Ulrich Schmid 0001, Gottfried Fuchs, Gerald Kempf	Fault-Tolerant Distributed Clock Generation in VLSI Systems-on-Chip.	EDCC	2006	DBLP DOI BibTeX RDF
10	JungHee Jo, KyoungWook Min, YongJoon Lee	Architecture of an LBS Platform to Support Privacy Control for Tracking Moving Objects in a Ubiquitous Environments.	ICUCT	2006	DBLP DOI BibTeX RDF
10	Houman Zarrabi, Haydar Saaied, Asim J. Al-Khalili, Yvon Savaria	Zero skew differential clock distribution network.	ISCAS	2006	DBLP DOI BibTeX RDF
10	Pei-Yu Huang, Yu-Min Lee, Jeng-Liang Tsai, Charlie Chung-Ping Chen	Simultaneous area minimization and decaps insertion for power delivery network using adjoint sensitivity analysis with IEKS method.	ISCAS	2006	DBLP DOI BibTeX RDF
10	Mitchell J. Myjak, José G. Delgado-Frias	Superpipelined reconfigurable hardware for DSP.	ISCAS	2006	DBLP DOI BibTeX RDF
10	Mohammad B. Vahidfar, Omid Shoaei, M. Fardis	A low power, transverse analog FIR filter for feed forward equalization of gigabit Ethernet.	ISCAS	2006	DBLP DOI BibTeX RDF
10	Markus Ferringer, Gottfried Fuchs, Andreas Steininger, Gerald Kempf	VLSI Implementation of a Fault-Tolerant Distributed Clock Generation.	DFT	2006	DBLP DOI BibTeX RDF
10	Konrad Walus, Gabriel Schulhof, Graham A. Jullien	Implementation of a Simulation Engine for Clocked Molecular QCA.	CCECE	2006	DBLP DOI BibTeX RDF
10	Sanjoy Kumar Dey, Swapna Banerjee	An 8-Bit, 3.8GHz Dynamic BiCMOS Comparator for High-Performance ADC.	VLSI Design	2006	DBLP DOI BibTeX RDF
10	Chua-Chin Wang, Gang-Neng Sung, Ming-Kai Chang, Ying-Yu Shen	Engery-Efficient Double-Edge Triggered Flip-Flop Design.	APCCAS	2006	DBLP DOI BibTeX RDF
10	Shih-Hsu Huang, Chun-Hua Cheng, Yow-Tyng Nieh, Wei-Chieh Yu	Register binding for clock period minimization.	DAC	2006	DBLP DOI BibTeX RDF	high-level synthesis, clock skew, timing optimization
10	John M. Cohn, Jeong-Taek Kong, Chris Malachowsky, Rich Tobias, Brendan Traw	Design challenges for next-generation multimedia, game and entertainment platforms.	DAC	2006	DBLP DOI BibTeX RDF	multimedia, gaming, design methodology, entertainment
10	Miguel Eduardo Litvin, Samiha Mourad	Self-reset logic for fast arithmetic applications.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
10	Russell Tessier, David Jasinski, Atul Maheshwari, Aiyappan Natarajan, Weifeng Xu, Wayne P. Burleson	An energy-aware active smart card.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
10	Xiaoming Yu, Miron Abramovici	Sequential circuit ATPG using combinational algorithms.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
10	Bryan Veal, Kang Li 0001, David K. Lowenthal	New Methods for Passive Estimation of TCP Round-Trip Times.	PAM	2005	DBLP DOI BibTeX RDF
10	Khushboo Shah, Stephan Bohacek	High short-term bit-rates from TCP Flows.	MASCOTS	2005	DBLP DOI BibTeX RDF
10	Elad Barkan, Eli Biham	Conditional Estimators: An Effective Attack on A5/1.	Selected Areas in Cryptography	2005	DBLP DOI BibTeX RDF
10	Christian Jacobi 0002, Kai Weber 0001, Viresh Paruthi, Jason Baumgartner	Automatic Formal Verification of Fused-Multiply-Add FPUs.	DATE	2005	DBLP DOI BibTeX RDF
10	Yu-Shen Yang, Andreas G. Veneris, Paul J. Thadikaran, Srikanth Venkataraman	Extraction Error Modeling and Automated Model Debugging in High-Performance Low Power Custom Designs.	DATE	2005	DBLP DOI BibTeX RDF
10	Hans M. Jacobson, Pradip Bose, Zhigang Hu, Alper Buyuktosunoglu, Victor V. Zyuban, Richard J. Eickemeyer, Lee Eisen, John Griswell, Doug Logan, Balaram Sinharoy, Joel M. Tendler	Stretching the Limits of Clock-Gating Efficiency in Server-Class Processors.	HPCA	2005	DBLP DOI BibTeX RDF
10	Jiantao Wang, David X. Wei, Steven H. Low	Modelling and stability of FAST TCP.	INFOCOM	2005	DBLP DOI BibTeX RDF
10	Amol Y. Deshmukh, Jayant Morghade, Akashdeep Khera, Preeti R. Bajaj	Binary Neural Networks - A CMOS Design Approach.	KES (1)	2005	DBLP DOI BibTeX RDF
10	Craig S. Lent, Sarah E. Frost, Peter M. Kogge	Reversible computation with quantum-dot cellular automata (QCA).	Conf. Computing Frontiers	2005	DBLP DOI BibTeX RDF	reversible computing, quantum-dot cellular automata, molecular electronics
10	Michael P. Frank	Introduction to reversible computing: motivation, progress, and challenges.	Conf. Computing Frontiers	2005	DBLP DOI BibTeX RDF	digital logic technologies, field-effect devices, limits of computing, VLSI, high-performance computing, computer architecture, power management, reversible computing, reversible logic, unconventional computing, low-power computing
10	Rumi Zhang, Wei Wang 0003, Konrad Walus, Graham A. Jullien	Performance comparison of quantum-dot cellular automata adders.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
10	Wei-Ta Chen, Jen-Chien Hsu, Hong-Wen Lune, Chauchin Su	A spread spectrum clock generator for SATA-II.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
10	Amparo Fúster-Sabater, Pino Caballero-Gil	A Simple Acceptance/Rejection Criterium for Sequence Generators in Symmetric Cryptography.	ICCSA (3)	2005	DBLP DOI BibTeX RDF	bit-string algorithm, cryptography, stream cipher, Confidentiality
10	Deepak C. Sekar	Clock trees: differential or single ended?.	ISQED	2005	DBLP DOI BibTeX RDF
10	Rung-Shiang Cheng, Hui-Tang Lin, Wen-Shyang Hwang, Ce-Kuen Shieh	Improving the Ramping up Behavior of TCP Slow Start.	AINA	2005	DBLP DOI BibTeX RDF
10	Ashok Narasimhan, Shantanu Divekar, Praveen Elakkumanan, Ramalingam Sridhar	A Low-Power Current-Mode Clock Distribution Scheme for Multi-GHz NoC-Based SoCs.	VLSI Design	2005	DBLP DOI BibTeX RDF
10	Emil Talpes, Diana Marculescu	Increased Scalability and Power Efficiency by Using Multiple Speed Pipelines.	ISCA	2005	DBLP DOI BibTeX RDF
10	Saraju P. Mohanty, Nagarajan Ranganathan	A framework for energy and transient power reduction during behavioral synthesis.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
10	Ravi S. Prasad, Manish Jain, Constantinos Dovrolis	Effects of Interrupt Coalescence on Network Measurements.	PAM	2004	DBLP DOI BibTeX RDF
10	W. J. Bainbridge, Luis A. Plana, Stephen B. Furber	The Design and Test of a Smartcard Chip Using a CHAIN Self-Timed Network-on-Chip.	DATE	2004	DBLP DOI BibTeX RDF
10	Aristides Efthymiou, Christos P. Sotiriou, Douglas A. Edwards	Automatic Scan Insertion and Pattern Generation for Asynchronous Circuits.	DATE	2004	DBLP DOI BibTeX RDF
10	Juan C. Diaz, Marta Saburit	Clock Management in a Gigabit Ethernet Physical Layer Transceiver Circuit.	DATE	2004	DBLP DOI BibTeX RDF
10	Matthew W. Heath, Wayne P. Burleson, Ian G. Harris	Synchro-Tokens: Eliminating Nondeterminism to Enable Chip-Level Test of Globally-Asynchronous Locally-Synchronous SoC?s.	DATE	2004	DBLP DOI BibTeX RDF
10	Scott Fairbanks, Simon W. Moore	Analog Micropipeline Rings for High Precision Timing.	ASYNC	2004	DBLP DOI BibTeX RDF
10	Ali Kanso	More Generalized Clock-Controlled Alternating Step Generator.	ACNS	2004	DBLP DOI BibTeX RDF	Clock-Controlled Registers, Alternating Step Generator and Clock-Controlled Alernating Step Generator, Stream Ciphers
10	Elaine Ou, Woodward Yang	Fast Error-Correcting Circuits for Fault-Tolerant Memory.	MTDT	2004	DBLP DOI BibTeX RDF
10	Baohua Wang, Pinaki Mazumder	On optimality of adiabatic switching in MOS energy-recovery circuit.	ISLPED	2004	DBLP DOI BibTeX RDF	adiabatic circuit, power clock optimization, variational calculus
10	Baohua Wang, Pinaki Mazumder	On optimality of adiabatic switching in MOS energy-recovery circuit.	ISLPED	2004	DBLP DOI BibTeX RDF	adiabatic circuit, power clock optimization, variational calculus
10	Daniel J. Allen, Angelo W. Pereira, Paul E. Hasler	A programmable coefficient continuous-time A/D Delta-Sigma modulator.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
10	Manuel Salim Maza, Mónico Linares Aranda	Analysis and verification of interconnected rings as clock distribution networks.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	GALS, ring oscillators, clock distribution networks
10	David C. Keezer, Dany Minier, F. Binette	Modular Extension of ATE to 5 Gbps.	ITC	2004	DBLP DOI BibTeX RDF
10	Laung-Terng Wang, Khader S. Abdel-Hafez, Shianling Wu, Xiaoqing Wen, Hiroshi Furukawa, Fei-Sheng Hsu, Shyh-Horng Lin, Sen-Wei Tsai	VirtualScan: A New Compressed Scan Technology for Test Cost Reduction.	ITC	2004	DBLP DOI BibTeX RDF
10	Jeff Rearick, Sylvia Patterson, Krista Dorner	Integrating Boundary Scan into Multi-GHz I/O Circuitry.	ITC	2004	DBLP DOI BibTeX RDF
10	Saraju P. Mohanty, Nagarajan Ranganathan, Sunil K. Chappidi	ILP Models for Energy and Transient Power Minimization During Behavioral Synthesis.	VLSI Design	2004	DBLP DOI BibTeX RDF
10	David S. Kung 0001	Timing closure for low-FO4 microprocessor design.	DAC	2004	DBLP DOI BibTeX RDF	FO4, synthesis, placement, high performance
10	Arindam Mukherjee 0001, Malgorzata Marek-Sadowska	Wave steering to integrate logic and physical syntheses.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
10	Jovan Dj. Golic, Renato Menicocci	Edit Probability Correlation Attacks on Stop/ Go Clocked Keystream Generators.	J. Cryptol.	2003	DBLP DOI BibTeX RDF	Stop/go clocked shift registers, Edit probability, Stream ciphers, Correlation attack
10	Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Hyun Suk Kim, Wu Ye, David Duarte	Evaluating Integrated Hardware-Software Optimizations Using a Unified Energy Estimation Framework.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	simulation, optimizations, energy models, Energy estimation
10	Ed Grochowski, David Ayers, Vivek Tiwari	Microarchitectural dI/dt Control.	IEEE Des. Test Comput.	2003	DBLP DOI BibTeX RDF
10	Milos Krstic, Eckhard Grass	New GALS Technique for Datapath Architectures.	PATMOS	2003	DBLP DOI BibTeX RDF
10	Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi	Peak Power Minimization Through Datapath Scheduling.	ISVLSI	2003	DBLP DOI BibTeX RDF
10	Conrad H. Ziesler, Joohee Kim, Marios C. Papaefthymiou	Energy Recovering ASIC Design.	ISVLSI	2003	DBLP DOI BibTeX RDF
10	Yaron Semiat, Ran Ginosar	Timing Measurements of Synchronization Circuits.	ASYNC	2003	DBLP DOI BibTeX RDF
10	L. Kalyan Kumar, Amol J. Mupid, Aditya S. Ramani, V. Kamakoti 0001	Testable Clock Routing Architecture for Field Programmable Gate Arrays.	FPL	2003	DBLP DOI BibTeX RDF
10	Jeng-Liang Tsai, Tsung-Hao Chen, Charlie Chung-Ping Chen	Optimal minimum-delay/area zero-skew clock tree wire-sizing in pseudo-polynomial time.	ISPD	2003	DBLP DOI BibTeX RDF	?-optimal, incremental refinement, pseudo-polynomial, clock tree, wire-sizing, zero-skew
10	Ali Kanso	Clock-Controlled Shrinking Generator of Feedback Shift Registers.	ACISP	2003	DBLP DOI BibTeX RDF
10	Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi	Power Fluctuation Minimization During Behavioral Synthesis using ILP-Based Datapath Scheduling.	ICCD	2003	DBLP DOI BibTeX RDF
10	Keith D. Cooper, Li Xu	Memory Redundancy Elimination to Improve Application Energy Efficiency.	LCPC	2003	DBLP DOI BibTeX RDF
10	Soha Hassoun	Optimal use of 2-phase transparent latches in buffered maze routing.	ISCAS (4)	2003	DBLP DOI BibTeX RDF
10	Jongsun Kim, Zhiwei Xu 0003, Mau-Chung Frank Chang	Reconfigurable memory bus systems using multi-Gbps/pin CDMA I/O transceivers.	ISCAS (2)	2003	DBLP DOI BibTeX RDF
10	Bhushan A. Shinkre, James E. Stine	A pipelined clock-delayed domino carry-lookahead adder.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF
10	Ching-Hwa Cheng	Design Scan Test Strategy for Single Phase Dynamic Circuits.	DFT	2003	DBLP DOI BibTeX RDF
10	Saraju P. Mohanty, N. Ranganathan	A Framework for Energy and Transient Power Reduction during Behavioral Synthesis.	VLSI Design	2003	DBLP DOI BibTeX RDF
10	Rohini Krishnan, Om Prakash Gangwal, Jos T. J. van Eijndhoven, Anshul Kumar	Design of a 2D DCT/IDCT application specific VLIW processor supporting scaled and sub-sampled blocks.	VLSI Design	2003	DBLP DOI BibTeX RDF
10	Willi Geiselmann, Rainer Steinwandt	Hardware to Solve Sparse Systems of Linear Equations over GF(2).	CHES	2003	DBLP DOI BibTeX RDF
10	Yu-Min Lee, Charlie Chung-Ping Chen	Power grid transient simulation in linear time based on transmission-line-modeling alternating-direction-implicit method.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
10	Victor Varshavsky, Vyacheslav Marakhovsky	GALA (Globally Asynchronous - Locally Arbitrary) Design.	Concurrency and Hardware Design	2002	DBLP DOI BibTeX RDF
10	Li Shang, Alireza Kaviani, Kusuma Bathala	Dynamic power consumption in Virtex[tm]-II FPGA family.	FPGA	2002	DBLP DOI BibTeX RDF
10	Keith J. Keller, Hiroshi Takahashi, Kim T. Le, Kewal K. Saluja, Yuzo Takamatsu	Reduction of Target Fault List for Crosstalk-Induced Delay Faults by using Layout Constraints.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
10	Pradip Bose, David M. Brooks, Alper Buyuktosunoglu, Peter W. Cook, K. Das, Philip G. Emma, Michael Gschwind, Hans M. Jacobson, Tejas Karkhanis, Prabhakar Kudva, Stanley Schuster, James E. Smith 0001, Viji Srinivasan, Victor V. Zyuban, David H. Albonesi, Sandhya Dwarkadas	Early-Stage Definition of LPX: A Low Power Issue-Execute Processor.	PACS	2002	DBLP DOI BibTeX RDF
10	Brucek Khailany, William J. Dally, Andrew Chang 0001, Ujval J. Kapasi, Jinyung Namkoong, Brian Towles	VLSI Design and Verification of the Imagine Processor.	ICCD	2002	DBLP DOI BibTeX RDF
10	Kong-Pang Pun, Chiu-sing Choy, Cheong-Fat Chan, José E. Franca	A quadrature IF mixer with high image rejection for continuous-time complex Sigma-Delta modulators.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
10	Sungwook Kim, Gerald E. Sobelman	Efficient digit-serial FIR filters with skew-tolerant domino.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
10	Victor V. Zyuban	Unified architecture level energy-efficiency metric.	ACM Great Lakes Symposium on VLSI	2002	DBLP DOI BibTeX RDF	performance, architecture, energy-efficiency, metric, power, energy, microarchitecture