Search results for "FPGA"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Safeen Huda, Jason Helge Anderson	Towards PVT-Tolerant Glitch-Free Operation in FPGAs.	FPGA	2016	DBLP DOI BibTeX RDF
1	Girish Deshpande, Dinesh K. Bhatia	An Activity Aware Placement Approach For 3D FPGAs (Abstract Only).	FPGA	2016	DBLP DOI BibTeX RDF
1	Nikolaos Alachiotis 0001, Gabriel Weisz	High Performance Linkage Disequilibrium: FPGAs Hold the Key.	FPGA	2016	DBLP DOI BibTeX RDF
1	Yu Bai 0004, Mingjie Lin	Stochastic-Based Spin-Programmable Gate Array with Emerging MTJ Device Technology (Abstract Only).	FPGA	2016	DBLP DOI BibTeX RDF
1	David M. Lewis, Gordon R. Chiu, Jeffrey Chromczak, David R. Galloway, Ben Gamsa, Valavan Manohararajah, Ian Milton, Tim Vanderhoek, John Van Dyken	The Stratix™ 10 Highly Pipelined FPGA Architecture.	FPGA	2016	DBLP DOI BibTeX RDF
1	Sabrina Zereen, Sundeep Lal, Mohammed A. S. Khalid, Sazzadur Chowdhury	An FPGA-Based Controller for a 77 GHz MEMS Tri-Mode Automotive Radar (Abstract Only).	FPGA	2016	DBLP DOI BibTeX RDF
1	Xitong Gao, John Wickerson, George A. Constantinides	Automatically Optimizing the Latency, Area, and Accuracy of C Programs for High-Level Synthesis.	FPGA	2016	DBLP DOI BibTeX RDF
1	Janarbek Matai, Dustin Richmond, Dajung Lee, Zac Blair, Qiongzhi Wu, Amin Abazari, Ryan Kastner	Resolve: Generation of High-Performance Sorting Architectures from High-Level Synthesis.	FPGA	2016	DBLP DOI BibTeX RDF
1	Hayden Kwok-Hay So, John Wawrzynek	OLAF'16: Second International Workshop on Overlay Architectures for FPGAs.	FPGA	2016	DBLP DOI BibTeX RDF
1	Zhiyuan Yang 0001, Ankur Srivastava 0001	Physical Design of 3D FPGAs Embedded with Micro-channel-based Fluidic Cooling.	FPGA	2016	DBLP DOI BibTeX RDF
1	Ronak Kogta, Suresh Purini, Ajit Mathew	Re-targeting Optimization Sequences from Scalar Processors to FPGAs in HLS compilers (Abstract Only).	FPGA	2016	DBLP DOI BibTeX RDF
1	Sizhuo Zhang, Hari Angepat, Derek Chiou	HGum: Messaging Framework for Hardware Accelerators (Abstact Only).	FPGA	2016	DBLP DOI BibTeX RDF
1	Sayeh Sharifymoghaddam, Ali Sheikholeslami	Low-Swing Signaling for FPGA Power Reduction (Abstract Only).	FPGA	2016	DBLP DOI BibTeX RDF
1	Jincheng Su, Fan Yang 0001, Xuan Zeng 0001, Dian Zhou	Efficient Memory Partitioning for Parallel Data Access via Data Reuse.	FPGA	2016	DBLP DOI BibTeX RDF
1	James J. Davis 0001, Eddie Hung, Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung, George A. Constantinides	Knowledge is Power: Module-level Sensing for Runtime Optimisation (Abstact Only).	FPGA	2016	DBLP DOI BibTeX RDF
1	Hsin-Jung Yang, Kermin Fleming, Michael Adler, Felix Winterstein, Joel S. Emer	LMC: Automatic Resource-Aware Program-Optimized Memory Partitioning.	FPGA	2016	DBLP DOI BibTeX RDF
1	Gregg Baeckler	HyperPipelining of High-Speed Interface Logic.	FPGA	2016	DBLP DOI BibTeX RDF
1	Stefan Visser, Harald Homulle, Edoardo Charbon	A 1 GSa/s, Reconfigurable Soft-core FPGA ADC (Abstract Only).	FPGA	2016	DBLP DOI BibTeX RDF
1	Zhen Yang, Jian Wang 0036, Meng Yang 0013, Jinmei Lai	Testing FPGA Local Interconnects Based on Repeatable Configuration Modules (Abstract Only).	FPGA	2016	DBLP DOI BibTeX RDF
1	Shlomi Alkalay, Hari Angepat, Adrian M. Caulfield, Eric S. Chung, Oren Firestein, Michael Haselman, Stephen Heil, Kyle Holohan, Matt Humphrey, Tamás Juhász, Puneet Kaur, Sitaram Lanka, Daniel Lo, Todd Massengill, Kalin Ovtcharov, Michael Papamichael, Andrew Putnam, Raja Seera, Rimon Tadros, Jason Thong, Lisa Woods, Derek Chiou, Doug Burger	Agile Co-Design for a Reconfigurable Datacenter.	FPGA	2016	DBLP DOI BibTeX RDF
1	Cédric Marchand 0002, Lilian Bossuet, Abdelkarim Cherkaoui	Enhanced TERO-PUF Implementations and Characterization on FPGAs (Abstract Only).	FPGA	2016	DBLP DOI BibTeX RDF
1	Que Yanghua, Chinnakkannu Adaikkala Raj, Harnhua Ng, Kirvy Teo, Nachiket Kapre	Case for Design-Specific Machine Learning in Timing Closure of FPGA Designs.	FPGA	2016	DBLP DOI BibTeX RDF
1	Carl Ebeling, Dana How, David M. Lewis, Herman Schmit	Stratix™ 10 High Performance Routable Clock Networks.	FPGA	2016	DBLP DOI BibTeX RDF
1	Bo Peng, Tianqi Wang, Xi Jin 0002, Chuanjun Wang	An FPGA-SOC Based Accelerating Solution for N-body Simulations in MOND (Abstract Only).	FPGA	2016	DBLP DOI BibTeX RDF
1	Timothy A. Linscott, Benjamin Gojman, Raphael Rubin, André DeHon	Pitfalls and Tradeoffs in Simultaneous, On-Chip FPGA Delay Measurement.	FPGA	2016	DBLP DOI BibTeX RDF
1	Henri Fraisse, Abhishek Joshi, Dinesh Gaitonde, Alireza Kaviani	Boolean Satisfiability-Based Routing and Its Application to Xilinx UltraScale Clock Network.	FPGA	2016	DBLP DOI BibTeX RDF
1	Guohao Dai, Yuze Chi, Yu Wang 0002, Huazhong Yang	FPGP: Graph Processing Framework on FPGA A Case Study of Breadth-First Search.	FPGA	2016	DBLP DOI BibTeX RDF
1	Ze-ke Wang, Hui Yan Cheah, Johns Paul, Bingsheng He, Wei Zhang 0012	Accelerating Database Query Processing on OpenCL-based FPGAs (Abstract Only).	FPGA	2016	DBLP DOI BibTeX RDF
1	Pankaj Shanker	Spatial Debug & Debug Without Re-programming in FPGAs: On-Chip debugging in FPGAs.	FPGA	2016	DBLP DOI BibTeX RDF
1	Xifan Tang, Pierre-Emmanuel Gaillardon, Giovanni De Micheli	A Full-Capacity Local RoutingArchitecture for FPGAs (Abstract Only).	FPGA	2016	DBLP DOI BibTeX RDF
1	Yunxuan Yu, Lei He 0001	FPGA Power Estimation Using Automatic Feature Selection (Abstract Only).	FPGA	2016	DBLP DOI BibTeX RDF
1	Daolu Zha, Xi Jin 0002, Tian Xiang	An Improved Global Stereo-Matching on FPGA for Real-Time Applications (Abstract Only).	FPGA	2016	DBLP DOI BibTeX RDF
1	Nimish Agashiwala, Satya Prakash Upadhyay, Kia Bazargan	t-QuadPlace: Timing Driven Quadratic Placement using Quadrisection Partitioning for FPGAs (Abstact Only).	FPGA	2016	DBLP DOI BibTeX RDF
1	Nachiket Kapre, Deheng Ye	GPU-Accelerated High-Level Synthesis for Bitwidth Optimization of FPGA Datapaths.	FPGA	2016	DBLP DOI BibTeX RDF
1	Xinheng Liu, Yao Chen 0008, Tan Nguyen, Swathi T. Gurumani, Kyle Rupnow, Deming Chen	High Level Synthesis of Complex Applications: An H.264 Video Decoder.	FPGA	2016	DBLP DOI BibTeX RDF
1	Wenchao Qian, Christopher Babecki, Robert Karam, Swarup Bhunia	ENFIRE: An Energy-efficient Fine-grained Spatio-temporal Reconfigurable Computing Fabric (Abstact Only).	FPGA	2016	DBLP DOI BibTeX RDF
1	Jie Lei 0001, Yu-Ting Chen, Yunsong Li, Jason Cong	A High-throughput Architecture for Lossless Decompression on FPGA Designed Using HLS (Abstract Only).	FPGA	2016	DBLP DOI BibTeX RDF
1	Grace Zgheib, Manana Lortkipanidze, Muhsen Owaida, David Novo, Paolo Ienne	FPRESSO: Enabling Express Transistor-Level Exploration of FPGA Architectures.	FPGA	2016	DBLP DOI BibTeX RDF
1	Tianqi Wang, Bo Peng, Xi Jin 0002	an Extensible Heterogeneous Multi-FPGA Framework for Accelerating N-body Simulation (Abstract Only).	FPGA	2016	DBLP DOI BibTeX RDF
1	Tan Nguyen, Swathi T. Gurumani, Kyle Rupnow, Deming Chen	FCUDA-SoC: Platform Integration for Field-Programmable SoC with the CUDA-to-FPGA Compiler.	FPGA	2016	DBLP DOI BibTeX RDF
1	Gabriel Weisz, Joseph Melber, Yu Wang 0110, Kermin Fleming, Eriko Nurvitadhi, James C. Hoe	A Study of Pointer-Chasing Performance on Shared-Memory Processor-FPGA Systems.	FPGA	2016	DBLP DOI BibTeX RDF
1	François Serre, Thomas Holenstein, Markus Püschel	Optimal Circuits for Streamed Linear Permutations Using RAM.	FPGA	2016	DBLP DOI BibTeX RDF
1	Mohammed Shaaban Ibraheem, Syed Zahid Ahmed, Khalil Hachicha, Sylvain Hochberg, Patrick Garda	A Low DDR Bandwidth 100FPS 1080p Video 2D Discrete Wavelet Transform Implementation on FPGA (Abstract Only).	FPGA	2016	DBLP DOI BibTeX RDF
1	Tuan D. A. Nguyen, Akash Kumar 0001	PRFloor: An Automatic Floorplanner for Partially Reconfigurable FPGA Systems.	FPGA	2016	DBLP DOI BibTeX RDF
1	Muhammed Al Kadi, Benedikt Janßen, Michael Hübner 0001	FGPU: An SIMT-Architecture for FPGAs.	FPGA	2016	DBLP DOI BibTeX RDF
1	Tayo Oguntebi, Kunle Olukotun	GraphOps: A Dataflow Library for Graph Analytics Acceleration.	FPGA	2016	DBLP DOI BibTeX RDF
1	Sen Ma, Zeyad Aklah, David Andrews 0001	Just In Time Assembly of Accelerators.	FPGA	2016	DBLP DOI BibTeX RDF
1	Naveen Suda, Vikas Chandra, Ganesh Dasika, Abinash Mohanty, Yufei Ma 0002, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao 0001	Throughput-Optimized OpenCL-based FPGA Accelerator for Large-Scale Convolutional Neural Networks.	FPGA	2016	DBLP DOI BibTeX RDF
1	Michael J. Wirthlin, Andrew M. Keller, Chase McCloskey, Parker Ridd, David S. Lee, Jeffrey Draper	SEU Mitigation and Validation of the LEON3 Soft Processor Using Triple Modular Redundancy for Space Processing.	FPGA	2016	DBLP DOI BibTeX RDF
1	David Boland	Reducing Memory Requirements for High-Performance and Numerically Stable Gaussian Elimination.	FPGA	2016	DBLP DOI BibTeX RDF
1	Li Ting, Harri Wijaya, Nachiket Kapre	Machine-Learning driven Auto-Tuning of High-Level Synthesis for FPGAs (Abstract Only).	FPGA	2016	DBLP DOI BibTeX RDF
1	Mohammed Alawad, Mingjie Lin	Stochastic-Based Convolutional Networks with Reconfigurable Logic Fabric (Abstract Only).	FPGA	2016	DBLP DOI BibTeX RDF
1	Jing Ye 0001, Yu Hu 0001, Xiaowei Li 0001	DCPUF: Placement and Routing Constraint based Dynamically Configured Physical Unclonable Function on FPGA (Abstact Only).	FPGA	2016	DBLP DOI BibTeX RDF
1	Yu-Ting Chen, Jason Cong, Zhenman Fang, Peipei Zhou 0001	ARAPrototyper: Enabling Rapid Prototyping and Evaluation for Accelerator-Rich Architecture (Abstact Only).	FPGA	2016	DBLP DOI BibTeX RDF
1	Ehsan Ghasemi, Paul Chow	A Scalable Heterogeneous Dataflow Architecture For Big Data Analytics Using FPGAs (Abstract Only).	FPGA	2016	DBLP DOI BibTeX RDF
1	Shih-Hao Hung, Min-Yu Tsai, Bo-Yi Huang, Chia-Heng Tu	A Platform-Oblivious Approach for Heterogeneous Computing: A Case Study with Monte Carlo-based Simulation for Medical Applications.	FPGA	2016	DBLP DOI BibTeX RDF
1	Deming Chen, Jonathan W. Greene (eds.)	Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Monterey, CA, USA, February 21-23, 2016	FPGA	2016	DBLP DOI BibTeX RDF
1	Nadesh Ramanathan, John Wickerson, Felix Winterstein, George A. Constantinides	A Case for Work-stealing on FPGAs with OpenCL Atomics.	FPGA	2016	DBLP DOI BibTeX RDF
1	Ralf Salomon, Ralf Joost, Matthias Hinkfoth	Platform-Independent Gigabit Communication for Low-Cost FPGAs (Abstract Only).	FPGA	2015	DBLP DOI BibTeX RDF
1	Joshua S. Monson, Brad L. Hutchings	Using Source-Level Transformations to Improve High-Level Synthesis Debug and Validation on FPGAs.	FPGA	2015	DBLP DOI BibTeX RDF
1	Eric Matthews, Nicholas C. Doyle, Lesley Shannon	Design Space Exploration of L1 Data Caches for FPGA-Based Multiprocessor Systems.	FPGA	2015	DBLP DOI BibTeX RDF
1	Elias Vansteenkiste, Berg Severens, Dirk Stroobandt	Logic Gates in the routing network of FPGAs (Abstract Only).	FPGA	2015	DBLP DOI BibTeX RDF
1	Leibo Liu, Yingjie Victor Chen, Dong Wang 0040, Min Zhu 0001, Shouyi Yin, Shaojun Wei	A Mixed-Grained Reconfigurable Computing Platform for Multiple-Standard Video Decoding (Abstract Only).	FPGA	2015	DBLP DOI BibTeX RDF
1	James Chacko, Cem Sahin, Douglas Pfiel, Nagarajan Kandasamy, Kapil R. Dandekar	Rapid Prototyping of Wireless Physical Layer Modules Using Flexible Software/Hardware Design Flow.	FPGA	2015	DBLP DOI BibTeX RDF
1	Michaela E. Amoo, Youngsoo Kim, Vance Alford, Shrikant Jadhav, Naser I. El-Bathy, Clay S. Gloster Jr.	An Automated Design Framework for Floating Point Scientific Algorithms using Field Programmable Gate Arrays (FPGAs) (Abstract Only).	FPGA	2015	DBLP DOI BibTeX RDF
1	Eddie Hung, Joshua M. Levine, Edward A. Stott, George A. Constantinides, Wayne Luk	Delay-Bounded Routing for Shadow Registers.	FPGA	2015	DBLP DOI BibTeX RDF
1	Jie Wang 0022, Jason Cong	Customizable and High Performance Matrix Multiplication Kernel on FPGA (Abstract Only).	FPGA	2015	DBLP DOI BibTeX RDF
1	Chen Chang	The BEEcube Story: Lessons Learned from Running a FPGA Startup for the Past 7 Years.	FPGA	2015	DBLP DOI BibTeX RDF
1	Youngsoo Kim, William Harding, Clay S. Gloster Jr., Winser E. Alexander	Acceleration of Synthetic Aperture Radar (SAR) Algorithms using Field Programmable Gate Arrays (FPGAs) (Abstract Only).	FPGA	2015	DBLP DOI BibTeX RDF
1	Mohamed S. Abdelfattah, Andrew Bitar, Vaughn Betz	Take the Highway: Design for Embedded NoCs on FPGAs.	FPGA	2015	DBLP DOI BibTeX RDF
1	Paulo Matias, Rafael Tuma Guariento, Lírio Onofre Baptista de Almeida, Jan Frans Willem Slaets	Low-Resource Bluespec Design of a Modular Acquisition and Stimulation System for Neuroscience (Abstract Only).	FPGA	2015	DBLP DOI BibTeX RDF
1	Xinyu Niu, Wayne Luk, Yu Wang 0002	EURECA: On-Chip Configuration Generation for Effective Dynamic Data Access.	FPGA	2015	DBLP DOI BibTeX RDF
1	Siddhartha 0001, Nachiket Kapre	FPGA Acceleration of Irregular Iterative Computations using Criticality-Aware Dataflow Optimizations (Abstract Only).	FPGA	2015	DBLP DOI BibTeX RDF
1	Fernando Martinez-Vallina, Henry Styles	Unlocking FPGAs Using High Level Synthesis Compiler Technologies.	FPGA	2015	DBLP DOI BibTeX RDF
1	Shant Chandrakar, Dinesh Gaitonde, Trevor Bauer	Enhancements in UltraScale CLB Architecture.	FPGA	2015	DBLP DOI BibTeX RDF
1	Keerthan Jaic, Melissa C. Smith	Enhancing Hardware Design Flows with MyHDL.	FPGA	2015	DBLP DOI BibTeX RDF
1	Hichem Ben Fekih, Ahmed Elhossini, Ben H. H. Juurlink	An Efficient and Flexible FPGA Implementation of a Face Detection System (Abstract Only).	FPGA	2015	DBLP DOI BibTeX RDF
1	Deshanand P. Singh, Bogdan Pasca 0001, Tomasz S. Czajkowski	High-Level Design Tools for Floating Point FPGAs.	FPGA	2015	DBLP DOI BibTeX RDF
1	Felix Winterstein, Kermin Fleming, Hsin-Jung Yang, Samuel Bayliss, George A. Constantinides	MATCHUP: Memory Abstractions for Heap Manipulating Programs.	FPGA	2015	DBLP DOI BibTeX RDF
1	Alex Rodionov, David Biancolin, Jonathan Rose	Fine-Grained Interconnect Synthesis.	FPGA	2015	DBLP DOI BibTeX RDF
1	Gregory Ford, Aswin Krishna, Jacob A. Abraham, Daniel G. Saab	Formal Verification ATPG Search Engine Emulator (Abstract Only).	FPGA	2015	DBLP DOI BibTeX RDF
1	Shao Lin S. T. Tang, Guy Lemieux	Area Optimization of Arithmetic Units by Component Sharing for FPGAs (Abstract Only).	FPGA	2015	DBLP DOI BibTeX RDF
1	Evan Wegley, Qinhai Zhang	Application of Specific Delay Window Routing for Timing Optimization in FPGA Designs.	FPGA	2015	DBLP DOI BibTeX RDF
1	Amir Momeni, Hamed Tabkhi, Gunar Schirner, David R. Kaeli	Bridging Architecture and Programming for Throughput-Oriented Vision Processing (Abstract Only).	FPGA	2015	DBLP DOI BibTeX RDF
1	John Lockwood, Michael Adler, Dan Mansur, Derek Chiou, Mike Strickland, Jason Cong, Steve Teig	Growing a Healthy FPGA Ecosystem.	FPGA	2015	DBLP DOI BibTeX RDF
1	Navid Rahmanikia, Amirali Amiri, Hamid Noori, Farhad Mehdipour	Exploring Efficiency of Ring Oscillator-Based Temperature Sensor Networks on FPGAs (Abstract Only).	FPGA	2015	DBLP DOI BibTeX RDF
1	Martinianos Papadopoulos, Christos Ttofis, Christos Kyrkou, Theocharis Theocharides	Real-Time Obstacle Avoidance for Mobile Robots via Stereoscopic Vision Using Reconfigurable Hardware (Abstract Only).	FPGA	2015	DBLP DOI BibTeX RDF
1	Stuart Byma, Naif Tarafdar, Talia Xu, Hadi Bannazadeh, Alberto Leon-Garcia, Paul Chow	Expanding OpenFlow Capabilities with Virtualized Reconfigurable Hardware.	FPGA	2015	DBLP DOI BibTeX RDF
1	Junbin Wang, Leibo Liu, Jianfeng Zhu 0001, Shouyi Yin, Shaojun Wei	A Novel Composite Method to Accelerate Control Flow on Reconfigurable Architecture (Abstract Only).	FPGA	2015	DBLP DOI BibTeX RDF
1	Wei Wu, Peng Gu, Yen-Lung Chen, Chien-Nan Liu, Sudhakar Pamarti, Chang Wu, Lei He 0001	Toward Wave Digital Filter based Analog Circuit Emulation on FPGA (Abstract Only).	FPGA	2015	DBLP DOI BibTeX RDF
1	Zhuo Qian, Martin Margala	A Novel Coefficient Address Generation Algorithm for Split-Radix FFT (Abstract Only).	FPGA	2015	DBLP DOI BibTeX RDF
1	Pierre-Emmanuel Gaillardon, Gain Kim, Xifan Tang, Luca Gaetano Amarù, Giovanni De Micheli	Towards More Efficient Logic Blocks By Exploiting Biconditional Expansion (Abstract Only).	FPGA	2015	DBLP DOI BibTeX RDF
1	Yu Bai 0004, Mingjie Lin	Energy-Efficient Discrete Signal Processing with Field Programmable Analog Arrays (FPAAs).	FPGA	2015	DBLP DOI BibTeX RDF
1	Nasibeh Nasiri, Oren Segal, Martin Margala, Wim Vanderbauwhede, Sai Rahul Chalamalasetti	High Level Programming of Document Classification Systems for Heterogeneous Environments using OpenCL (Abstract Only).	FPGA	2015	DBLP DOI BibTeX RDF
1	Dmitry Burlyaev, Pascal Fradet, Alain Girault	Automatic Time-Redundancy Transformation for Fault-Tolerant Circuits.	FPGA	2015	DBLP DOI BibTeX RDF
1	Hui Yan Cheah, Suhaib A. Fahmy, Nachiket Kapre	On Data Forwarding in Deeply Pipelined Soft Processors.	FPGA	2015	DBLP DOI BibTeX RDF
1	Xitong Gao, George A. Constantinides	Numerical Program Optimization for High-Level Synthesis.	FPGA	2015	DBLP DOI BibTeX RDF
1	Nachiket Kapre, Harnhua Ng, Kirvy Teo, Jaco Naude	InTime: A Machine Learning Approach for Efficient Selection of FPGA CAD Tool Parameters.	FPGA	2015	DBLP DOI BibTeX RDF
1	Chen Yang 0005, Leibo Liu, Shouyi Yin, Shaojun Wei	Cost-Effective Memory Architecture to Achieve Flexible Configuration and Efficient Data Transmission for Coarse-Grained Reconfigurable Array (Abstract Only).	FPGA	2015	DBLP DOI BibTeX RDF
1	Lei Chen 0010, Yuanfu Zhao, Zhiping Wen 0001, Jing Zhou, Xuewu Li, Yanlong Zhang, Huabo Sun	300 Thousand Gates Single Event Effect Hardened SRAM-based FPGA for Space Application (Abstract Only).	FPGA	2015	DBLP DOI BibTeX RDF

Publications at "FPGA"( http://dblp.L3S.de/Venues/FPGA )