Search results for "HDL"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
10	Sanggyu Park, Sang-yong Yoon, Soo-Ik Chae	A Mixed-Level Virtual Prototyping Environment for Refinement-Based Design Environment.	IEEE International Workshop on Rapid System Prototyping	2006	DBLP DOI BibTeX RDF
10	Hadi Esmaeilzadeh, A. Moghimi, Eiman Ebrahimi, Caro Lucas, Zainalabedin Navabi, A. M. Fakhraie	DCim++: a C++ library for object oriented hardware design and distributed simulation.	ISCAS	2006	DBLP DOI BibTeX RDF
10	Pawel Garstecki, Adam Luczak, Marta Stepniewska	A bit-serial implementation of mode decision algorithm for AVC encoders.	ISCAS	2006	DBLP DOI BibTeX RDF
10	Wei Wang 0252, I-Chyn Wey, Chia-Tsun Wu, An-Yeu Wu	A portable all-digital pulsewidth control loop for SOC applications.	ISCAS	2006	DBLP DOI BibTeX RDF
10	Kimo Kim, In-Cheol Park	Combined image signal processing for CMOS image sensors.	ISCAS	2006	DBLP DOI BibTeX RDF
10	Tim Schattkowsky, Jan Hendrik Hausmann, Gregor Engels	Using UML Activities for System-on-Chip Design and Synthesis.	MoDELS	2006	DBLP DOI BibTeX RDF
10	Mustafa Parlak, Ilker Hamzaoglu	An Efficient Hardware Architecture for H.264 Adaptive Deblocking Filter.	AHS	2006	DBLP DOI BibTeX RDF
10	Stefanos Skoulaxinos	SW-HW Co-design and Fault Tolerant Implementation for the LRID Wireless Communication System.	AHS	2006	DBLP DOI BibTeX RDF
10	Namrata Shekhar, Priyank Kalla, M. Brandon Meredith, Florian Enescu	Simulation Bounds for Equivalence Verification of Arithmetic Datapaths with Finite Word-Length Operands.	FMCAD	2006	DBLP DOI BibTeX RDF
10	Robin J. Bruce, Richard Chamberlain, Malachy Devlin, Stephen Marshall	Poster reception - Implementing algorithms on FPGAs using high-level languages and low-level libraries.	SC	2006	DBLP DOI BibTeX RDF
10	Junhao Zheng, Di Wu 0022, Lei Deng 0007, Don Xie, Wen Gao 0001	A Motion Vector Predictor Architecture for AVS and MPEG-2 HDTV Decoder.	PCM	2006	DBLP DOI BibTeX RDF	Motion vector prediction, MPEG, Motion compensation, VLSI architecture, AVS
10	Chung-Ho Chen, Yi-Cheng Chung, Chen-Hua Wang, Han-Chiang Chen	Design of a Giga-bit Hardware Accelerator for the iSCSI Initiator.	LCN	2006	DBLP DOI BibTeX RDF
10	Duo Sheng, Ching-Che Chung, Chen-Yi Lee	A Fast-Lock-In ADPLL with High-Resolution and Low-Power DCO for SoC Applications.	APCCAS	2006	DBLP DOI BibTeX RDF
10	Shen-Fu Hsiao, Ming-Yu Tsai, Chia-Sheng Wen	Efficient Pass-Transistor-Logic Synthesis for Sequential Circuits.	APCCAS	2006	DBLP DOI BibTeX RDF
10	Wonwoo Jang, Hyunsik Kim, Sungmok Lee, Jooyoung Ha, Bongsoon Kang	Implementation of the Gamma Line System Similar to Non-linear Gamma Curve with 2bit Error(LSB).	APCCAS	2006	DBLP DOI BibTeX RDF
10	Xiaoying Li, Fuming Sun, Enhua Wu	A Simulink-to-FPGA Co-Design of Encryption Module.	APCCAS	2006	DBLP DOI BibTeX RDF
10	Yu-Chin Hsu, Fur-Shing Tsai, Wells Jong, Ying-Tsai Chang	Visibility enhancement for silicon debug.	DAC	2006	DBLP DOI BibTeX RDF	silicon validation, functional verification, silicon debug
10	Insu Song, Guido Governatori	Designing agent chips.	AAMAS	2006	DBLP DOI BibTeX RDF	agent chips, agent architecture, agent programming languages
10	Wei Lu, Xiu-Tao Yang, Tao Lv 0001, Xiaowei Li 0001	An Efficient Evaluation and Vector Generation Method for Observability-Enhanced Statement Coverage.	J. Comput. Sci. Technol.	2005	DBLP DOI BibTeX RDF	simulation, observability, design verification, coverage metrics, vector generation
10	Jung L. Lee, Myung Hoon Sunwoo	Implementation of a Wireless Multimedia DSP Chip for Mobile Applications.	J. VLSI Signal Process.	2005	DBLP DOI BibTeX RDF	multimedia, DSP, instruction
10	Guillermo Payá Vayá, Javier Martín-Langerwerf, Peter Pirsch	RAPANUI: Rapid Prototyping for Media Processor Architecture Exploration.	SAMOS	2005	DBLP DOI BibTeX RDF
10	Shuqing Zhao, Daniel D. Gajski	Structural operational semantics for supporting multi-cycle operations in RTL HDLs.	MEMOCODE	2005	DBLP DOI BibTeX RDF
10	Nirav Dave, Man Cheuk Ng, Arvind	Automatic synthesis of cache-coherence protocol processors using Bluespec.	MEMOCODE	2005	DBLP DOI BibTeX RDF
10	Bo Yang 0010, Nikhil Joshi, Ramesh Karri	A constant array multiplier core generator with dynamic partial evaluation architecture selection (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
10	Yujia Jin, William Plishker, Kaushik Ravindran, Nadathur Satish, Kurt Keutzer	Soft multiprocessor systems for network applications (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
10	Shuqing Zhao, Daniel D. Gajski	Defining an Enhanced RTL Semantics.	DATE	2005	DBLP DOI BibTeX RDF
10	Christian Jacobi 0002, Kai Weber 0001, Viresh Paruthi, Jason Baumgartner	Automatic Formal Verification of Fused-Multiply-Add FPUs.	DATE	2005	DBLP DOI BibTeX RDF
10	Sandro V. Silva, Sergio Bampi	Area and Throughput Trade-Offs in the Design of Pipelined Discrete Wavelet Transform Architectures.	DATE	2005	DBLP DOI BibTeX RDF
10	Franco Fummi, Mirko Loghi, Stefano Martini, Marco Monguzzi, Giovanni Perbellini, Massimo Poncino	Virtual Hardware Prototyping through Timed Hardware-Software Co-Simulation.	DATE	2005	DBLP DOI BibTeX RDF
10	Nicolas Genko, David Atienza, Giovanni De Micheli, Jose Manuel Mendias, Román Hermida, Francky Catthoor	A Complete Network-On-Chip Emulation Framework.	DATE	2005	DBLP DOI BibTeX RDF
10	Cyrus Bazeghi, Francisco J. Mesa-Martinez, Jose Renau	uComplexity: Estimating Processor Design Effort.	MICRO	2005	DBLP DOI BibTeX RDF
10	Saranyan A. Vigraham, John C. Gallagher	A space saving digital VLSI evolutionary engine for CTRNN-EH devices.	Congress on Evolutionary Computation	2005	DBLP DOI BibTeX RDF
10	Norihiro Fujii, Nobuhiko Koike	A New Remote Laboratory for Hardware Experiment with Shared Resources and Service Management.	ICITA (2)	2005	DBLP DOI BibTeX RDF	Hardware Experiment, Shared-Lab, Web services, Distance learning, Remote laboratory, shared service
10	Rajeev Madhavan	Silicon compilation: the answer to reducing IC development costs.	ASP-DAC	2005	DBLP DOI BibTeX RDF
10	Jaehwan John Lee, Vincent John Mooney III	A novel O(n) parallel banker's algorithm for System-on-a-Chip.	ASP-DAC	2005	DBLP DOI BibTeX RDF
10	Subramanian K. Iyer, Jawahar Jain, Debashis Sahoo, Takeshi Shimizu	Verification of Industrial Designs Using A Computing Grid With More than 100 Nodes.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
10	Amir Hekmatpour, Azadeh Salehi	Block-based Schema-driven Assertion Generation for Functional Verification.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
10	Mukesh Chugh, Dinesh Bhatia, Poras T. Balsara	Design and Implementation of Configurable W-CDMA Rake Receiver Architectures on FPGA.	IPDPS	2005	DBLP DOI BibTeX RDF
10	John A. Nestor	Teaching Computer Organization with HDLs: An Incremental Approach.	MSE	2005	DBLP DOI BibTeX RDF
10	Wayne P. Burleson, Sheng Xu	Digital Systems Design with ASIC and FPGA: A Novel Course Using CD/DVD and On-Line Formats.	MSE	2005	DBLP DOI BibTeX RDF
10	Hugo Hedberg, Joachim Neves Rodrigues, Fredrik Kristensen, Henrik Svensson, Matthias Kamuf, Viktor Öwall	Teaching Digital ASIC Design to Students with Heterogeneous Previous Knowledge.	MSE	2005	DBLP DOI BibTeX RDF
10	Michael A. Shanblatt, Brian Foulds	A Simulink-to-FPGA Implementation Tool for Enhanced Design Flow.	MSE	2005	DBLP DOI BibTeX RDF
10	Johannes Grad, James E. Stine, David D. Neiman	Real World SOC Experience for the Classroom.	MSE	2005	DBLP DOI BibTeX RDF
10	Mathias Halbach, Rolf Hoffmann	Optimal Behavior of a Moving Creature in the Cellular Automata Model.	PaCT	2005	DBLP DOI BibTeX RDF
10	Stephen A. Edwards, Olivier Tardieu	SHIM: a deterministic model for heterogeneous embedded systems.	EMSOFT	2005	DBLP DOI BibTeX RDF	deterministic model of computation, hardware/software codesign, software synthesis, hardware synthesis
10	Gyu-Sung Yeon, Chi-Hun Jun, Tae-Jin Hwang, Seongsoo Lee, Jae-Kyung Wee	Low-Power MPEG-4 Motion Estimator Design for Deep Sub-Micron Multimedia SoC.	KES (3)	2005	DBLP DOI BibTeX RDF
10	Nikolaos Kostaras, Haridimos T. Vergos	KoVer: A Sophisticated Residue Arithmetic Core Generator.	IEEE International Workshop on Rapid System Prototyping	2005	DBLP DOI BibTeX RDF
10	Etienne Bergeron, Xavier Saint-Mleux, Marc Feeley, Jean-Pierre David	High Level Synthesis for Data-Driven Applications.	IEEE International Workshop on Rapid System Prototyping	2005	DBLP DOI BibTeX RDF
10	Leandro Soares Indrusiak, Romualdo Begale Prudencio, Manfred Glesner	Modeling and Prototyping of Communication Systems Using Java: A Case Study.	IEEE International Workshop on Rapid System Prototyping	2005	DBLP DOI BibTeX RDF
10	Hua Li, Jianzhou Li	A High Performance Sub-Pipelined Architecture for AES.	ICCD	2005	DBLP DOI BibTeX RDF	sub-pipelined architecture, FPGA, cryptography, AES
10	Tadashi Saito, Moto Maeda, Tetsuo Hironaka, Kazuya Tanigawa, Tetsuya Sueyoshi, Ken-ichi Aoyama, Tetsushi Koide, Hans Jürgen Mattausch	Design of superscalar processor with multi-bank register file.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
10	Yasuhiro Takahashi, Michio Yokoyama	New cost-effective VLSI implementation of multiplierless FIR filter using common subexpression elimination.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
10	Shen-Fu Hsiao, Ming-Yu Tsai, Ming-Chih Chen, Chia-Sheng Wen	An efficient pass-transistor-logic synthesizer using multiplexers and inverters only.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
10	Nicolas Genko, David Atienza, Giovanni De Micheli, Luca Benini, Jose Manuel Mendias, Román Hermida, Francky Catthoor	A novel approach for network on chip emulation.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
10	Donghyun Kim, Kangmin Lee, Se-Joong Lee, Hoi-Jun Yoo	A reconfigurable crossbar switch with adaptive bandwidth control for networks-on-chip.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
10	Ping Dong, Xiangdong Shi, Jiehui Yang	Design of a New Kind of Encryption Kernel Based on RSA Algorithm.	CIS (2)	2005	DBLP DOI BibTeX RDF
10	Ivan Blunno, Luciano Lavagno	Designing an asynchronous microcontroller using Pipefitter.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
10	Byung Cheol Song, Kang Wook Chun	Multi-resolution block matching algorithm and its VLSI architecture for fast motion estimation in an MPEG-2 video encoder.	IEEE Trans. Circuits Syst. Video Technol.	2004	DBLP DOI BibTeX RDF
10	Bin Sheng, Wen Gao 0001, Di Wu 0022	An implemented architecture of deblocking filter for H.264/AVC.	ICIP	2004	DBLP DOI BibTeX RDF
10	Zhi Guo, Betul Buyukkurt, Walid A. Najjar	Input data reuse in compiling window operations onto reconfigurable hardware.	LCTES	2004	DBLP DOI BibTeX RDF	reuse analysis, compilation, high-level synthesis, VHDL, reconfigurable computing
10	Daniel Große, Rolf Drechsler	Checkers for SystemC designs.	MEMOCODE	2004	DBLP DOI BibTeX RDF
10	Andreas Wortmann 0002, Sven Simon 0001, Matthias Müller 0002	A High-Speed Transceiver Architecture Implementable as Synthesizable IP Core.	DATE	2004	DBLP DOI BibTeX RDF
10	Mikael Millberg, Erland Nilsson, Rikard Thid, Axel Jantsch	Guaranteed Bandwidth Using Looped Containers in Temporally Disjoint Networks within the Nostrum Network on Chip.	DATE	2004	DBLP DOI BibTeX RDF
10	Doris Ching, Patrick Schaumont, Ingrid Verbauwhede	Integrated Modeling and Generation of a Reconfigurable Network-on-Chip.	IPDPS	2004	DBLP DOI BibTeX RDF
10	Shinya Honda, Takayuki Wakabayashi, Hiroyuki Tomiyama, Hiroaki Takada	RTOS-centric hardware/software cosimulator for embedded system design.	CODES+ISSS	2004	DBLP DOI BibTeX RDF	embedded Systems, RTOS, cosimulation
10	Young-Il Kim, Chong-Min Kyung	Automatic translation of behavioral testbench for fully accelerated simulation.	ICCAD	2004	DBLP DOI BibTeX RDF
10	Jun Wang, Carl Tropper	Nicarus: A Distributed Verilog Compiler.	ICPP Workshops	2004	DBLP DOI BibTeX RDF
10	Kazuya Ishida, Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi 0001	Design and Verification of Parallel Multipliers Using Arithmetic Description Language: ARITH.	ISMVL	2004	DBLP DOI BibTeX RDF
10	Jan Borgosz, Boguslaw Cyganek	Proposal of the Programming Rules for VHDL Designs.	International Conference on Computational Science	2004	DBLP DOI BibTeX RDF
10	Roland E. Wunderlich, James C. Hoe	In-System FPGA Prototyping of an Itanium Microarchitecture.	ICCD	2004	DBLP DOI BibTeX RDF
10	Ammar Aljer, Philippe Devienne	Co-Design and Refinement for Safety Critical Systems.	DFT	2004	DBLP DOI BibTeX RDF
10	Siddika Berna Örs, Frank K. Gürkaynak, Elisabeth Oswald, Bart Preneel	Power-Analysis Attack on an ASIC AES implementation.	ITCC (2)	2004	DBLP DOI BibTeX RDF	AES, power analysis attack
10	Ole Blaurock	A SystemC-Based Modular Design and Verification Framework for C-Model Reuse in a HW/SW-Co-Design Flow.	ICDCS Workshops	2004	DBLP DOI BibTeX RDF
10	T. Salim, John C. Devlin, Jim Whittington	Analog Conversion for FPGA Implementation of the TIGER Transmitter using a 14 bit DAC.	DELTA	2004	DBLP DOI BibTeX RDF
10	Vijay D'Silva, S. Ramesh 0001, Arcot Sowmya	Bridge Over Troubled Wrappers: Automated Interface Synthesis.	VLSI Design	2004	DBLP DOI BibTeX RDF
10	Tun Li, Yang Guo 0003, Sikun Li	Design and Implementation of a Parallel Verilog Simulator: PVSim.	VLSI Design	2004	DBLP DOI BibTeX RDF
10	Hoonmo Yang, Moonkey Lee	Design of a Cycle-Accurate User-Retargetable Instruction-Set Simulator Using Process-Based Scheduling Scheme.	CIS	2004	DBLP DOI BibTeX RDF
10	Xizhi Li, Tiecai Li	ECOMIPS: An Economic MIPS CPU Design on FPGA.	IWSOC	2004	DBLP DOI BibTeX RDF
10	Young-Su Kwon, Young-Il Kim, Chong-Min Kyung	Systematic functional coverage metric synthesis from hierarchical temporal event relation graph.	DAC	2004	DBLP DOI BibTeX RDF	semi-formal verification, temporal event, functional coverage
10	Adrian J. Hilton, Jon G. Hall	High-Integrity Interfacing to Programmable Logic with Ada.	Ada-Europe	2004	DBLP DOI BibTeX RDF
10	Gaye Lightbody, Roger F. Woods, Richard L. Walke	Design of a parameterizable silicon intellectual property core for QR-based RLS filtering.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
10	Jen-Shiun Chiang, Min-Shiou Tsai	A Radix-4 New Svobota-Tung Divider with Constant Timing Complexity for Prescaling.	J. VLSI Signal Process.	2003	DBLP DOI BibTeX RDF	floating-point division, new Svoboda-Tung division, radix-4, Svoboda-Tung division, computer arithmetic, prescaling, signed digit number system
10	Jae Sung Lee, Myung Hoon Sunwoo	Design of New DSP Instructions and Their Hardware Architecture for High-Speed FFT.	J. VLSI Signal Process.	2003	DBLP DOI BibTeX RDF	application specific digital signal processor, DMT, fast Fourier transform, OFDM
10	Raul Baños, Consolación Gil, Maria Dolores Gil Montoya, Julio Ortega Lopera	A Parallel Evolutionary Algorithm for Circuit Partitioning.	PDP	2003	DBLP DOI BibTeX RDF
10	Paul Flugger	RTL-Based Signal Statistics Calculation Facilitates Low Power Design Approaches.	PATMOS	2003	DBLP DOI BibTeX RDF
10	Hamid R. Zarandi, Seyed Ghassem Miremadi, Ali Reza Ejlali	Fault Injection into Verilog Models for Dependability Evaluation of Digital Systems.	ISPDC	2003	DBLP DOI BibTeX RDF
10	Eduardo Ros 0001, Rodrigo Agís, Richard R. Carrillo, Eva M. Ortigosa	Post-synaptic Time-Dependent Conductances in Spiking Neurons: FPGA Implementation of a Flexible Cell Model.	IWANN (2)	2003	DBLP DOI BibTeX RDF
10	Ashraf Salem	Formal Semantics of Synchronous SystemC.	DATE	2003	DBLP DOI BibTeX RDF
10	Petros Oikonomakos, Mark Zwolinski, Bashir M. Al-Hashimi	Versatile High-Level Synthesis of Self-Checking Datapaths Using an On-Line Testability Metric.	DATE	2003	DBLP DOI BibTeX RDF
10	Rafael Castro-López, Francisco V. Fernández 0001, Fernando Medeiro, Ángel Rodríguez-Vázquez	Behavioural Modelling and Simulation of SigmaDelta Modulators Using Hardware Description Languages.	DATE	2003	DBLP DOI BibTeX RDF
10	Tun Li, Yang Guo 0003, Sikun Li	An Automatic Circuit Extractor for RTL Verification.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
10	Tao Lv 0001, Jianping Fan 0002, Xiaowei Li 0001	An Efficient Observability Evaluation Algorithm Based on Factored Use-Def Chains.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
10	Miroslav Lícko, Jan Schier, Milan Tichý, Markus Kühl	MATLAB/Simulink Based Methodology for Rapid-FPGA-Prototyping.	FPL	2003	DBLP DOI BibTeX RDF
10	Amir K. Daneshbeh, M. Anwarul Hasan	A Unidirectional Bit Serial Systolic Architecture for Double-Basis Division over GF(2m).	IEEE Symposium on Computer Arithmetic	2003	DBLP DOI BibTeX RDF
10	Zdenek Pohl, Jan Schier, Miroslav Lícko, Antonin Hermanek, Milan Tichý, Rudolf Matousek, Jiri Kadlec	Logarithmic Arithmetic for Real Data Types and Support for Matlab/Simulink Based Rapid-FPGA-Prototyping.	IPDPS	2003	DBLP DOI BibTeX RDF
10	Volnei A. Pedroni	Teaching Design-Oriented VHDL.	MSE	2003	DBLP DOI BibTeX RDF
10	Michael J. C. Gordon, Joe Hurd, Konrad Slind	Executing the Formal Semantics of the Accellera Property Specification Language by Mechanised Theorem Proving.	CHARME	2003	DBLP DOI BibTeX RDF
10	Won Jay Song, Won Hee Kim, Bo Gwan Kim, Byung-Ha Ahn, Mun Kee Choi, Minho Kang	Smart Card Terminal Systems Using ISO/IEC 7816-3 Interface and 8051 Microprocessor Based on the System-on-Chip.	ISCIS	2003	DBLP DOI BibTeX RDF
10	Won Jay Song, Won Hee Kim, Bo Gwan Kim, Byung-Ha Ahn, Mun Kee Choi, Minho Kang	Conditional Access Module Systems for Digital Contents Protection Based on Hybrid/Fiber/Coax CATV Networks.	ISCIS	2003	DBLP DOI BibTeX RDF
10	Gérard Berry, Michael Kishinevsky, Satnam Singh	System Level Design and Verification Using a Synchronous Language.	ICCAD	2003	DBLP DOI BibTeX RDF