Search results for "ISPASS"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Veerle Desmet, Sylvain Girbal, Olivier Temam	ArchExplorer.org: A methodology for facilitating a fair Comparison of research ideas.	ISPASS	2010	DBLP DOI BibTeX RDF
1	Harold W. Cain, Priya Nagpurkar	Runahead execution vs. conventional data prefetching in the IBM POWER6 microprocessor.	ISPASS	2010	DBLP DOI BibTeX RDF
1	David Shaw	Using special-purpose hardware to achieve a hundred-fold speedup in molecular dynamics simulations of proteins.	ISPASS	2010	DBLP DOI BibTeX RDF
1	Nikolas Ladas, Yiannakis Sazeides, Veerle Desmet	Performance-effective operation below Vcc-min.	ISPASS	2010	DBLP DOI BibTeX RDF
1	Jianmin Chen, Zhuo Huang, Feiqi Su, Jih-Kwon Peir, Jeff Ho, Lu Peng 0001	Weak execution ordering - exploiting iterative methods on many-core GPUs.	ISPASS	2010	DBLP DOI BibTeX RDF
1	Simone Secchi, Paolo Meloni, Luigi Raffo	Exploiting FPGAs for technology-aware system-level evaluation of multi-core architectures.	ISPASS	2010	DBLP DOI BibTeX RDF
1	Karthik Ganesan 0006, Jungho Jo, Lizy K. John	Synthesizing memory-level parallelism aware miniature clones for SPEC CPU2006 and ImplantBench workloads.	ISPASS	2010	DBLP DOI BibTeX RDF
1	Donald E. Porter, Emmett Witchel	Understanding transactional memory performance.	ISPASS	2010	DBLP DOI BibTeX RDF
1	Parijat Dube, Michael Tsao, Dan E. Poff, Li Zhang 0002, Alan Bivens	Program behavior characterization in large memory systems.	ISPASS	2010	DBLP DOI BibTeX RDF
1	Yan Cui 0002, Yu Chen 0004, Yuanchun Shi	Scaling OLTP applications on commodity multi-core platforms.	ISPASS	2010	DBLP DOI BibTeX RDF
1	Vladimir Subotic, Jesús Labarta, Mateo Valero	Simulation environment for studying overlap of communication and computation.	ISPASS	2010	DBLP DOI BibTeX RDF
1	Ryan E. Grant, Pavan Balaji, Ahmad Afsahi	A study of hardware assisted IP over InfiniBand and its impact on enterprise data center performance.	ISPASS	2010	DBLP DOI BibTeX RDF
1	David W. Nellans, Kshitij Sudan, Rajeev Balasubramonian, Erik Brunvand	Hardware prediction of OS run-length for fine-grained resource customization.	ISPASS	2010	DBLP DOI BibTeX RDF
1	Aaron Ariel, Wilson W. L. Fung, Andrew E. Turner, Tor M. Aamodt	Visualizing complex dynamics in many-core accelerator architectures.	ISPASS	2010	DBLP DOI BibTeX RDF
1	Alex Skaletsky, Tevi Devor, Nadav Chachmon, Robert S. Cohn, Kim M. Hazelwood, Vladimir Vladimirov, Moshe Bach	Dynamic program analysis of Microsoft Windows applications.	ISPASS	2010	DBLP DOI BibTeX RDF
1	Celal Öztürk, Resit Sendag	An analysis of hard to predict branches.	ISPASS	2010	DBLP DOI BibTeX RDF
1	Andrea Adamoli, Milan Jovic, Matthias Hauswirth	LagAlyzer: A latency profile analysis and visualization tool.	ISPASS	2010	DBLP DOI BibTeX RDF
1	Jean-Charles Tournier, Martin Naef	Influences of SIMD architectures for scattered data interpolation algorithm.	ISPASS	2010	DBLP DOI BibTeX RDF
1	Paul J. Drongowski, Lei Yu, Frank Swehosky, Suravee Suthikulpanit, Robert Richter	Incorporating Instruction-Based Sampling into AMD CodeAnalyst.	ISPASS	2010	DBLP DOI BibTeX RDF
1	Chi Xu, Xi Chen 0068, Robert P. Dick, Zhuoqing Morley Mao	Cache contention and application performance prediction for multi-core systems.	ISPASS	2010	DBLP DOI BibTeX RDF
1	Anirban Mandal, Rob Fowler, Allan Porterfield	Modeling memory concurrency for multi-socket multi-core systems.	ISPASS	2010	DBLP DOI BibTeX RDF
1	Yan Cui 0002, Yu Chen 0004, Yuanchun Shi, Qingbo Wu 0003	Scalability comparison of commodity operating systems on multi-cores.	ISPASS	2010	DBLP DOI BibTeX RDF
1	David Eklov, Erik Hagersten	StatStack: Efficient modeling of LRU caches.	ISPASS	2010	DBLP DOI BibTeX RDF
1		IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2010, 28-30 March 2010, White Plains, NY, USA	ISPASS	2010	DBLP BibTeX RDF
1	Vladimir Uzelac, Aleksandar Milenkovic	Experiment flows and microbenchmarks for reverse engineering of branch predictor structures.	ISPASS	2009	DBLP DOI BibTeX RDF
1	Dmitrijs Zaparanuks, Milan Jovic, Matthias Hauswirth	Accuracy of performance counter measurements.	ISPASS	2009	DBLP DOI BibTeX RDF
1	Randy Smith, Neelam Goyal, Justin Ormont, Karthikeyan Sankaralingam, Cristian Estan	Evaluating GPUs for network packet signature matching.	ISPASS	2009	DBLP DOI BibTeX RDF
1	Joel S. Emer	Accelerating architecture research.	ISPASS	2009	DBLP DOI BibTeX RDF
1	Jeff Ringenberg, Trevor N. Mudge	SuiteSpecks and SuiteSpots: A methodology for the automatic conversion of benchmarking programs into intrinsically checkpointed assembly code.	ISPASS	2009	DBLP DOI BibTeX RDF
1	Jaideep Moses, Konstantinos Aisopos, Aamer Jaleel, Ravi R. Iyer 0001, Ramesh Illikkal, Donald Newell, Srihari Makineni	CMPSched$im: Evaluating OS/CMP interaction on shared cache management.	ISPASS	2009	DBLP DOI BibTeX RDF
1	Moriyoshi Ohara, Priya Nagpurkar, Yohei Ueda, Kazuaki Ishizaki	The data-centricity of Web 2.0 workloads and its impact on server performance.	ISPASS	2009	DBLP DOI BibTeX RDF
1	Haoqiang Zheng, Jason Nieh	WARP: Enabling fast CPU scheduler development and evaluation.	ISPASS	2009	DBLP DOI BibTeX RDF
1	Dileep Bhandarkar	Performance analysis in the real world of on line services.	ISPASS	2009	DBLP DOI BibTeX RDF
1	Jeffrey J. Cook, Craig B. Zilles	Characterizing and optimizing the memory footprint of de novo short read DNA sequence assembly.	ISPASS	2009	DBLP DOI BibTeX RDF
1	Pierre Michaud	Online compression of cache-filtered address traces.	ISPASS	2009	DBLP DOI BibTeX RDF
1	Gabriel H. Loh, Samantika Subramaniam, Yuejian Xie	Zesto: A cycle-level simulator for highly detailed microarchitecture exploration.	ISPASS	2009	DBLP DOI BibTeX RDF
1	Julio Merino, Lluc Alvarez, Marisa Gil, Nacho Navarro	Cetra: A trace and analysis framework for the evaluation of Cell BE systems.	ISPASS	2009	DBLP DOI BibTeX RDF
1	Armin Heindl, Gilles Pokam, Ali-Reza Adl-Tabatabai	An analytic model of optimistic Software Transactional Memory.	ISPASS	2009	DBLP DOI BibTeX RDF
1		IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2009, April 26-28, 2009, Boston, Massachusetts, USA, Proceedings	ISPASS	2009	DBLP BibTeX RDF
1	Kiyeon Lee, Shayne Evans, Sangyeun Cho	Accurately approximating superscalar processor performance from traces.	ISPASS	2009	DBLP DOI BibTeX RDF
1	Ali Bakhoda, George L. Yuan, Wilson W. L. Fung, Henry Wong, Tor M. Aamodt	Analyzing CUDA workloads using a detailed GPU simulator.	ISPASS	2009	DBLP DOI BibTeX RDF
1	Venkatesan Packirisamy, Antonia Zhai, Wei-Chung Hsu, Pen-Chung Yew, Tin-Fook Ngai	Exploring speculative parallelism in SPEC2006.	ISPASS	2009	DBLP DOI BibTeX RDF
1	Yu Zhang, Berkin Özisikyilmaz, Gokhan Memik, John Kim, Alok N. Choudhary	Analyzing the impact of on-chip network traffic on program phases for CMPs.	ISPASS	2009	DBLP DOI BibTeX RDF
1	Milind Kulkarni 0001, Martin Burtscher, Calin Cascaval, Keshav Pingali	Lonestar: A suite of parallel irregular programs.	ISPASS	2009	DBLP DOI BibTeX RDF
1	Dam Sunwoo, Joonsoo Kim, Derek Chiou	QUICK: A flexible full-system functional model.	ISPASS	2009	DBLP DOI BibTeX RDF
1	Bin Lin 0002, Arindam Mallik, Peter A. Dinda, Gokhan Memik, Robert P. Dick	User- and process-driven dynamic voltage and frequency scaling.	ISPASS	2009	DBLP DOI BibTeX RDF
1	Nitya Ranganathan, Doug Burger, Stephen W. Keckler	Analysis of the TRIPS prototype block predictor.	ISPASS	2009	DBLP DOI BibTeX RDF
1	Wei Huang 0004, Kevin Skadron, Sudhanva Gurumurthi, Robert J. Ribando, Mircea R. Stan	Differentiating the roles of IR measurement and simulation for power and temperature-aware design.	ISPASS	2009	DBLP DOI BibTeX RDF
1	Niket Agarwal, Tushar Krishna, Li-Shiuan Peh, Niraj K. Jha	GARNET: A detailed on-chip network model inside a full-system simulator.	ISPASS	2009	DBLP DOI BibTeX RDF
1	Qiming Teng, Peter F. Sweeney, Evelyn Duesterwald	Understanding the cost of thread migration for multi-threaded Java applications running on a multicore platform.	ISPASS	2009	DBLP DOI BibTeX RDF
1	Jiangtian Li, Xiaosong Ma, Karan Singh, Martin Schulz 0001, Bronis R. de Supinski, Sally A. McKee	Machine learning based online performance prediction for runtime parallelization and task scheduling.	ISPASS	2009	DBLP DOI BibTeX RDF
1	Lee Baugh, Craig B. Zilles	An Analysis of I/O And Syscalls In Critical Sections And Their Implications For Transactional Memory.	ISPASS	2008	DBLP DOI BibTeX RDF
1	Derek L. Schuff, Yung Ryn Choe, Vijay S. Pai	Conservative vs. Optimistic Parallelization of Stateful Network Intrusion Detection.	ISPASS	2008	DBLP DOI BibTeX RDF
1	Valentina Salapura, Karthik Ganesan 0006, Alan Gara, Michael Gschwind, James C. Sexton, Robert Walkup	Next-Generation Performance Counters: Towards Monitoring Over Thousand Concurrent Events.	ISPASS	2008	DBLP DOI BibTeX RDF
1	Paruj Ratanaworabhan, Martin Burtscher	Program Phase Detection based on Critical Basic Block Transitions.	ISPASS	2008	DBLP DOI BibTeX RDF
1	Osman Hasan, Sofiène Tahar	Performance Analysis of ARQ Protocols using a Theorem Prover.	ISPASS	2008	DBLP DOI BibTeX RDF
1	Jizhu Lu, Michael Perrone, Kursad Albayraktaroglu, Manoj Franklin	HMMer-Cell: High Performance Protein Profile Searching on the Cell/B.E. Processor.	ISPASS	2008	DBLP DOI BibTeX RDF
1	ElMoustapha Ould-Ahmed-Vall, Kshitij A. Doshi, Charles Yount, James Woodlee	Characterization of SPEC CPU2006 and SPEC OMP2001: Regression Models and their Transferability.	ISPASS	2008	DBLP DOI BibTeX RDF
1	Hashem Hashemi Najaf-abadi, Eric Rotenberg	Configurational Workload Characterization.	ISPASS	2008	DBLP DOI BibTeX RDF
1	William R. Dieter, Henry G. Dietz	Computer Aided Engineering of Cluster Computers.	ISPASS	2008	DBLP DOI BibTeX RDF
1	Omid Azizi, Jamison D. Collins, Dinesh Patil, Hong Wang 0003, Mark Horowitz	Processor Performance Modeling using Symbolic Simulation.	ISPASS	2008	DBLP DOI BibTeX RDF
1	Pradeep Ramachandran, Sarita V. Adve, Pradip Bose, Jude A. Rivers	Metrics for Architecture-Level Lifetime Reliability Analysis.	ISPASS	2008	DBLP DOI BibTeX RDF
1	Ali G. Saidi, Nathan L. Binkert, Steven K. Reinhardt, Trevor N. Mudge	Full-System Critical Path Analysis.	ISPASS	2008	DBLP DOI BibTeX RDF
1	Vassilios N. Christopoulos, David J. Lilja, Paul R. Schrater, Apostolos P. Georgopoulos	Independent Component Analysis and Evolutionary Algorithms for Building Representative Benchmark Subsets.	ISPASS	2008	DBLP DOI BibTeX RDF
1	Marina Biberstein, Uzi Shvadron, Javier Turek, Bilha Mendelson, Moon S. Chang	Trace-based Performance Analysis on Cell BE.	ISPASS	2008	DBLP DOI BibTeX RDF
1		IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2008, April 20-22, 2008, Austin, Texas, USA, Proceedings	ISPASS	2008	DBLP BibTeX RDF
1	Jun Yang 0002, Xiuyi Zhou, Marek Chrobak, Youtao Zhang, Lingling Jin	Dynamic Thermal Management through Task Scheduling.	ISPASS	2008	DBLP DOI BibTeX RDF
1	Ayose Falcón, Paolo Faraboschi, Daniel Ortega	An Adaptive Synchronization Technique for Parallel Simulation of Networked Clusters.	ISPASS	2008	DBLP DOI BibTeX RDF
1	Ying Zhang 0032, Xuejun Yang, Guibin Wang, Ian Rogers, Gen Li 0002, Yu Deng 0001, Xiaobo Yan	Scientific Computing Applications on a Stream Processor.	ISPASS	2008	DBLP DOI BibTeX RDF
1	Collin McCurdy, Alan L. Cox, Jeffrey S. Vetter	Investigating the TLB Behavior of High-end Scientific Applications on Commodity Microprocessors.	ISPASS	2008	DBLP DOI BibTeX RDF
1	Kaushik Kumar Ram, Ian C. Fedeli, Alan L. Cox, Scott Rixner	Explaining the Impact of Network Transport Protocols on SIP Proxy Performance.	ISPASS	2008	DBLP DOI BibTeX RDF
1	Gabriel Marin, John M. Mellor-Crummey	Pinpointing and Exploiting Opportunities for Enhancing Data Reuse.	ISPASS	2008	DBLP DOI BibTeX RDF
1	Kenneth Hoste, Lieven Eeckhout	Characterizing the Unique and Diverse Behaviors in Existing and Emerging General-Purpose and Domain-Specific Benchmark Suites.	ISPASS	2008	DBLP DOI BibTeX RDF
1	Michael Pellauer, Muralidaran Vijayaraghavan, Michael Adler, Arvind, Joel S. Emer	Quick Performance Models Quickly: Closely-Coupled Partitioned Simulation on FPGAs.	ISPASS	2008	DBLP DOI BibTeX RDF
1	Mauricio Alvarez 0001, Esther Salamí, Alex Ramírez, Mateo Valero	Performance Impact of Unaligned Memory Operations in SIMD Extensions for Video Codec Applications.	ISPASS	2007	DBLP DOI BibTeX RDF	auto vectorizing compiler, unaligned memory operations, SIMD extensions, video codec applications, unaligned memory accesses, H.264/AVC media codec, memory architecture, data level parallelism
1	Yefim Shuf, Ian M. Steiner	Characterizing a Complex J2EE Workload: A Comprehensive Analysis and Opportunities for Optimizations.	ISPASS	2007	DBLP DOI BibTeX RDF	J2EE workload, Java benchmarks, SPECjvm98, SPECjbb2000, Java 2 Enterprise Edition, SPECjAppServer2004, systems research, software research, cache-to-cache modified data transfers, intelligent thread co-scheduling, Java heap, bursty data cache, Java virtual method calls, optimizations, performance analysis, garbage collection, instruction cache, data prefetching, commercial workload
1	Michael Ferdman, Babak Falsafi	Last-Touch Correlated Data Streaming.	ISPASS	2007	DBLP DOI BibTeX RDF	predictor lookahead, last-touch correlated data streaming, address-correlating predictor, cache block address identification, correlation data storage, program active memory footprint, prediction lookahead, off-chip correlation data lookup, scalable on-chip table, low-latency lookup, on-chip storage, last-touch predictor, prefetch, superscalar processor, cycle-accurate simulation
1	Karthikeyan Vaidyanathan, Dhabaleswar K. Panda 0001	Benefits of I/O Acceleration Technology (I/OAT) in Clusters.	ISPASS	2007	DBLP DOI BibTeX RDF	concurrent thread, I/O acceleration technology, TCP/IP stack, multigigabit data rate, packet processing overhead, multitier data center, CPU utilization, central processing unit, network bandwidth performance, transmission control protocol, transport protocol, Internet protocol, parallel virtual file system
1	Younggyun Koh, Rob C. Knauerhase, Paul Brett, Mic Bowman, Zhihua Wen, Calton Pu	An Analysis of Performance Interference Effects in Virtual Environments.	ISPASS	2007	DBLP DOI BibTeX RDF	performance interference, system-level workload characteristics, runtime characteristics, Ken hypervisor, virtual environment, virtual machines, virtualization, data analysis, performance metrics, performance isolation, system throughput
1	Andrew Over, Bill Clarke, Peter E. Strazdins	A Comparison of Two Approaches to Parallel Simulation of Multiprocessors.	ISPASS	2007	DBLP DOI BibTeX RDF	speedup analysis, Sparc Sulima, UltraSPARC IIICu-based multiprocessor systems, careful locking, simulation time quantum, serial simulation, load-balancing, parallel simulation, parallel discrete event simulation, interconnect model, NAS parallel benchmarks
1	ElMoustapha Ould-Ahmed-Vall, James Woodlee, Charles Yount, Kshitij A. Doshi, Seth Abraham	Using Model Trees for Computer Architecture Performance Analysis of Software Applications.	ISPASS	2007	DBLP DOI BibTeX RDF	superscalar machine, computer architecture performance analysis, tuning software, statistical regression modeling, M5' algorithm, SPEC CPU2006 suite, performance model tree, prefetching, software application
1	Wenlong Li, Eric Q. Li, Aamer Jaleel, Jiulong Shan, Yurong Chen 0001, Qigang Wang, Ravi R. Iyer 0001, Ramesh Illikkal, Yimin Zhang 0002, Dong Liu, Michael Liao, Wei Wei, Jinhua Du	Understanding the Memory Performance of Data-Mining Workloads on Small, Medium, and Large-Scale CMPs Using Hardware-Software Co-simulation.	ISPASS	2007	DBLP DOI BibTeX RDF	DRAM caches, small-scale CMP, medium-scale CMP, large-scale CMP, hardware-software co-simulation, terabyte-level workloads, multithreaded data mining applications, cache design, memory performance, multicore systems, memory system performance
1	William Lloyd Bircher, Lizy K. John	Complete System Power Estimation: A Trickle-Down Approach Based on Performance Events.	ISPASS	2007	DBLP DOI BibTeX RDF	power sensing hardware, complete system power estimation, microprocessor performance event, microprocessor performance counter, online measurement, complete system power consumption, microprocessor power, on-chip performance event counter, system power consumption estimation, power model
1	Wangyuan Zhang, Xin Fu, Tao Li 0006, José A. B. Fortes	An Analysis of Microarchitecture Vulnerability to Soft Errors on Simultaneous Multithreaded Architectures.	ISPASS	2007	DBLP DOI BibTeX RDF	thread-aware reliability optimization, microarchitecture vulnerability, simultaneous multithreaded architecture, semiconductor transient fault, microprocessor reliability, processor throughput, soft error vulnerability analysis, SPEC CPU 2000 benchmark, microarchitecture structure, microarchitecture reliability profile, fetch policy, thread-level parallelism, multithreading architecture
1	Paul D. Bryan, Michel C. Rosier, Thomas M. Conte	Reverse State Reconstruction for Sampled Microarchitectural Simulation.	ISPASS	2007	DBLP DOI BibTeX RDF	reverse state reconstruction, sampled microarchitectural simulation, processor simulation
1		2007 IEEE International Symposium on Performance Analysis of Systems and Software, April 25-27, 2007, San Jose, California, USA, Proceedings	ISPASS	2007	DBLP BibTeX RDF
1	Ke Meng, Frank Huebbers, Russ Joseph, Yehea I. Ismail	Modeling and Characterizing Power Variability in Multicore Architectures.	ISPASS	2007	DBLP DOI BibTeX RDF	mal-fabricated chip, VariPower, project power variability, microarchitectural block, power variability characterization, statistical analysis, multicore processor, multicore architecture, technology scaling, parameter variation, SPICE simulation
1	Jiang Lin, Hongzhong Zheng, Zhichun Zhu, Zhao Zhang 0010, Howard David	DRAM-Level Prefetching for Fully-Buffered DIMM: Design, Performance and Power Saving.	ISPASS	2007	DBLP DOI BibTeX RDF	channel bandwidth utilization, DRAM-level prefetching, dynamic random access memory, fully-buffered DIMM, dual in-line memory module, redundant bandwidth, memory block, L2 cache block, DRAM power consumption, SPEC2000 program, software cache prefetching, idle memory latency, power saving, multicore processor, memory controller, interconnect structure, DRAM chip
1	Chang-Burm Cho, Tao Li 0006	Using Wavelet Domain Workload Execution Characteristics to Improve Accuracy, Scalability and Robustness in Program Phase Analysis.	ISPASS	2007	DBLP DOI BibTeX RDF	program execution variability, workload execution statistics, program phase analysis, computer architecture design, computer architecture optimization, program execution statistics, SPEC CPU 2000 benchmark, wavelet domain phase analysis, runtime workload execution characteristics, scalable phase analysis, sampled workload statistics, phase classification accuracy, wavelet transform, time domain, wavelet denoising
1	Xudong Shi 0003, Feiqi Su, Jih-Kwon Peir, Ye Xia 0001, Zhen Yang	Modeling and Single-Pass Simulation of CMP Cache Capacity and Accessibility.	ISPASS	2007	DBLP DOI BibTeX RDF	multiple cache organization, single-pass simulation, on-chip storage space, on-chip cache capacity, single-pass stack simulation, global stack, shared stack, per-core private stack, single simulation pass, average memory access time, chip-multiprocessor, data replication, data accessibility, abstract model, reuse distances
1	Ayose Falcón, Paolo Faraboschi, Daniel Ortega	Combining Simulation and Virtualization through Dynamic Sampling.	ISPASS	2007	DBLP DOI BibTeX RDF	code caching, dynamic sampling, fast timing simulation, virtual machines, virtualization
1	Leslie Barnes	Performance Modeling and Analysis for AMD's High Performance Microprocessors.	ISPASS	2007	DBLP DOI BibTeX RDF
1	Erez Perelman, Jeremy Lau, Harish Patil, Aamer Jaleel, Greg Hamerly, Brad Calder	Cross Binary Simulation Points.	ISPASS	2007	DBLP DOI BibTeX RDF	cross binary simulation point, SimPoint, architectural design space exploration, compiler optimization evaluation, program execution, program evaluation
1	Daniel Jiménez-González, Xavier Martorell, Alex Ramírez	Performance Analysis of Cell Broadband Engine for High Memory Bandwidth Applications.	ISPASS	2007	DBLP DOI BibTeX RDF	arithmetic performance analysis, memory bandwidth application, synergistic processor element, DMA controller, direct memory access, element interconnect bus, bandwidth performance peak, processor component, message passing interface, data stream, single instruction multiple data, cell broadband engine, streaming programming model, processor speed
1	Dhiraj D. Kalamkar, Mainak Chaudhuri, Mark A. Heinrich	Simplifying Active Memory Clusters by Leveraging Directory Protocol Threads.	ISPASS	2007	DBLP DOI BibTeX RDF	active memory cluster, directory protocol thread, active memory address remapping, parallel reduction, coherence protocol extension, software protocol, multi-threaded node, dual-core node, active memory architecture, distributed shared memory, multiprocessor architecture, memory controller, matrix transpose
1	Joshua L. Kihm, Samuel D. Strom, Daniel A. Connors	Phase-Guided Small-Sample Simulation.	ISPASS	2007	DBLP DOI BibTeX RDF	SpedOOO benchmark suite, phase-guided small-sample simulation, sampled simulation, phase-based simulation, benchmark evaluation suite, execution-aware sampling-based simulation, design space exploration, sampling method, processor design, cycle-accurate simulation
1	Seongbeom Kim, Fang Liu, Yan Solihin, Ravi R. Iyer 0001, Li Zhao 0002, W. Cohen	Accelerating Full-System Simulation through Characterizing and Predicting Operating System Performance.	ISPASS	2007	DBLP DOI BibTeX RDF	memory hierarchy model, full-system simulation acceleration, operating system performance characterization, operating system performance prediction, computer hardware complexity, cycle-accurate processor system simulation overheads, system libraries, OS service performance behavior, processor hierarchy model, Linux, software complexity
1	Mahesh Bhat, John Crawford, Ricardo Morin, Kumar Shiv	Performance Characterization of Decimal Arithmetic in Commercial Java Workloads.	ISPASS	2007	DBLP DOI BibTeX RDF	software decimal implementations, commercial Java workloads, binary floating-point numbers, special decimal representations, optimized hardware support, decimal math, BigDecimal class, scale manipulation, SPECjbb2005, SPECjAppServer2004, mission-critical financial workload, Trade Completion, hashing, performance characterization, decimal arithmetic, format conversion
1	Donald Newell	Workloads, Scalability, and QoS Considerations in CMP Platforms.	ISPASS	2007	DBLP DOI BibTeX RDF
1	Matt T. Yourst	PTLsim: A Cycle Accurate Full System x86-64 Microarchitectural Simulator.	ISPASS	2007	DBLP DOI BibTeX RDF	client-server networked benchmark, PTLsim, cycle accurate full system, x86-64 microarchitectural simulator, superscalar x86-64 processor core, full-speed native execution, microarchitectural simulators, x86 ISA, microoperation level, multiprocessor capable simulation, Xen hypervisor, AMD Athlon 64 machine, virtual machine

Publications at "ISPASS"( http://dblp.L3S.de/Venues/ISPASS )