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Results
Found 1972 publication records. Showing 1972 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Telajala Venkata Mahendra, Sheikh Wasmir Hussain, Sandeep Mishra, Anup Dandapat |
Low discharge precharge free matchline structure for energy-efficient search using CAM.  |
Integr.  |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Leilei Wang, Cheng Zhuo, Pingqiang Zhou |
Run-time demand estimation and modulation of on-chip decaps at system level for leakage power reduction in multicore chips. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Dengli Bu, Pengjun Wang |
An improved KFDD based reversible circuit synthesis method. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Xueyan Wang, Qiang Zhou 0001, Yici Cai, Gang Qu 0001 |
Parallelizing SAT-based de-camouflaging attacks by circuit partitioning and conflict avoiding. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Chase Cook, Hengyang Zhao, Takashi Sato, Masayuki Hiromoto, Sheldon X.-D. Tan |
GPU-based Ising computing for solving max-cut combinatorial optimization problems. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Hossein Sariri, Pooya Torkzadeh, Sirus Sadughi |
A novel design of hybrid-time-interleaved current steering digital to analog converter and its behavioral simulation considering non-ideal effects. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Varsha Agarwal, Ananya Singla, Mahammad Samiuddin, Sudip Roy 0001, Tsung-Yi Ho, Indranil Sengupta 0001, Bhargab B. Bhattacharya |
Scheduling algorithms for reservoir- and mixer-aware sample preparation with microfluidic biochips. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Roberto Sierra, Carlos Carreras, Gabriel Caffarena |
Witelo: Automated generation and timing characterization of distributed-control macroblocks for high-performance FPGA designs. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Soheil Salehi, Navid Khoshavi, Ramtin Zand, Ronald F. DeMara |
Self-Organized Sub-bank SHE-MRAM-based LLC: An energy-efficient and variation-immune read and write architecture. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Haoyi Wang, Chenguang Wang 0003, Yici Cai, Qiang Zhou 0001 |
A high-level information flow tracking method for detecting information leakage. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Victor Hugo Carbajal-Gomez, Esteban Tlelo-Cuautle, Jesús M. Muñoz-Pacheco, Luis Gerardo de la Fraga, Carlos Sánchez-López, Francisco Vidal Fernández Fernández |
Optimization and CMOS design of chaotic oscillators robust to PVT variations: INVITED. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Gereon Führ, Ahmed Hallawa, Rainer Leupers, Gerd Ascheid, Juan Fernando Eusse |
Multi-objective optimisation of software application mappings on heterogeneous MPSoCs: TONPET versus R2-EMOA. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrea Ragni, Giuseppe Sciortino, Marco Sampietro, Giorgio Ferrari, Dario Polli |
Multi-channel lock-in based differential front-end for broadband Raman spectroscopy. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Dongjin Lee, Sourav Das, Partha Pratim Pande |
Analyzing power-thermal-performance trade-offs in a high-performance 3D NoC architecture. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | M. Savitha, R. Venkat Siva Reddy |
Dual split-three segment capacitor array Design Based Successive approximation ADC for Io-T ecosystem. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Young-Ho Seo, Sung-Ho Park, Dong-Wook Kim |
High-level hardware design of digital comparator with multiple inputs. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Julián Caba, Fernando Rincón, Julio Dondo, Jesús Barba, Manuel J. Abaldea, Juan Carlos López 0001 |
Testing framework for on-board verification of HLS modules using grey-box technique and FPGA overlays. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Hamed Fatemi, Andrew B. Kahng, Hyein Lee 0001, Jiajia Li 0002, José Pineda de Gyvez |
Enhancing sensitivity-based power reduction for an industry IC design context. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Boran Wen, Qisheng Zhang, Xiao Zhao, Xiaolong Lv, Yongqing Wang |
Trade-offs among power consumption and other design parameters of two-stage recycling folded cascode OTA that using embedded cascode current buffer compensation technology. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Qingli Guo, Jing Ye 0001, Bing Li 0017, Yu Hu 0001, Xiaowei Li 0001, Yazhu Lan, Guohe Zhang |
PUFPass: A password management mechanism based on software/hardware codesign. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Lennart Bamberg, Jan Moritz Joseph, Thilo Pionteck, Alberto García Ortiz |
Crosstalk optimization for through-silicon vias by exploiting temporal signal misalignment. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Baolin Wei, Tian Chen, Chao Lu 0005, Weilin Xu, Yuanzhi Zhang, Xueming Wei, Hongwei Yue, Jihai Duan |
An all-digital frequency tunable IR-UWB transmitter with an approximate 15th derivative Gaussian pulse generator. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Remi Dekimpe, Pengcheng Xu 0002, Maxime Schramme, Pierre Gérard, Denis Flandre, David Bol |
A battery-less BLE smart sensor for room occupancy tracking supplied by 2.45-GHz wireless power transfer. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Jinglei Huang, Xiaodong Xu, Nan Wang, Song Chen 0001 |
Reconfigurable topology synthesis for application-specific NoC on partially dynamically reconfigurable systems. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Tohid Aghaei, Ali Naderi Saatlo |
A new strategy to design low power translinear based CMOS analog multiplier. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | M. Reza Sadeghifar, Håkan Bengtsson, J. Jacob Wikner, Oscar Gustafsson |
Direct digital-to-RF converter employing semi-digital FIR voltage-mode RF DAC. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Zahra Shirmohammadi |
OP-Fibo: An efficient Forbidden Pattern Free CAC design. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Farzad Daryabari, Abdulhamid Zahedi, Abbas Rezaei, Mohsen Hayati |
Gain-controlled noise-reduction LNA design using source-bulk resistors and double common-source topology. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Leila Bagheriye, Siroos Toofan, Roghayeh Saeidi, Farshad Moradi |
Highly stable, low power FinFET SRAM cells with exploiting dynamic back-gate biasing. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Sarah Azimi, Boyang Du, Luca Sterpone, David Merodio Codinachs, Raoul Grimoldi, L. Cattaneo |
A new CAD tool for Single Event Transient Analysis and mitigation on Flash-based FPGAs. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Chase Cook, Sheriff Sadiqbatcha, Zeyu Sun 0001, Sheldon X.-D. Tan |
Reliability based hardware Trojan design using physics-based electromigration models. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Puneeth Kumar, S. Rekha |
Fast start crystal oscillator design with negative resistance control. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Lawrence T. Clark, James Adams, Keith E. Holbert |
Reliable techniques for integrated circuit identification and true random number generation using 1.5-transistor flash memory. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Yan Li, Zhiwei Li, Chen Yang, Wei Zhong, Song Chen 0001 |
High throughput hardware architecture for accurate semi-global matching. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Monir Zaman, Mustafa M. Shihab, Ayse K. Coskun, Yiorgos Makris |
CAPE: A cross-layer framework for accurate microprocessor power estimation. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Manish Kumar Jaiswal, Hayden Kwok-Hay So |
Design of quadruple precision multiplier architectures with SIMD single and double precision support. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Thawra Kadeed, Sebastian Tobuschat, Adam Kostrzewa, Rolf Ernst |
Safe and efficient power management of hard real-time networks-on-chip. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Sachin Maheshwari, Vivian A. Bartlett, Izzet Kale |
Modelling, simulation and verification of 4-phase adiabatic logic design: A VHDL-Based approach. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Manan Mewada, Mazad Zaveri, Rajesh Amratlal Thakker |
Improving the performance of transmission gate and hybrid CMOS Full Adders in chain and tree structure architectures. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Anushree Mahapatra, Benjamin Carrión Schäfer |
VeriIntel2C: Abstracting RTL to C to maximize High-Level Synthesis Design Space Exploration. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Kunwar Singh, Satish Chandra Tiwari, Maneesha Gupta |
A closed-loop ASIC design approach based on logical effort theory and artificial neural networks. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Kiran Kumar Matam, Mohammad Abdel-Majeed, Murali Annavaram |
Efficient automatic parallelization of a single GPU program for a multiple GPU system. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Muhammed Ceylan Morgül, Mustafa Altun |
Optimal and heuristic algorithms to synthesize lattices of four-terminal switches. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Yu-Fan Chiang, Wei-Yu Chien, Yue-Der Chih, Jonathan Chang, Chrong Jung Lin, Ya-Chin King |
FinFET CMOS logic gates with non-volatile states for reconfigurable computing systems. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Soraya Aghnout, Gholamreza Karimi |
Modeling triplet spike timing dependent plasticity using a hybrid TFT-memristor neuromorphic synapse. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Chihiro Matsui, Ken Takeuchi |
Step-by-Step Design of memory hierarchy for heterogeneously-integrated SCM/NAND flash storage. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Masanori Hashimoto, Kazutoshi Kobayashi, Jun Furuta, Shin-ichiro Abe, Yukinobu Watanabe |
Characterizing SRAM and FF soft error rates with measurement and simulation. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Xin Feng, Youni Jiang, Xuejiao Yang, Ming Du, Xin Li 0001 |
Computer vision algorithms and hardware implementations: A survey. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Yiming Ouyang, Zhe Li, Jianhua Li 0003, Chenglong Sun, Huaguo Liang, Gaoming Du |
CPCA: An efficient wireless routing algorithm in WiNoC for cross path congestion awareness. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Semih Turk, Alexander Schug, Reinhard Viga, Andreas Jupe, Holger Vogt |
Optimization of the dielectric layer for electrowetting on dielectric. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiangwei Cai, Jieming Yin, Pingqiang Zhou |
An orchestrated NoC prioritization mechanism for heterogeneous CPU-GPU systems. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Dawei Li, Xiaowei Xu 0004, Leibo Liu, Li Zhang 0021, Cheng Zhuo, Yiyu Shi 0001 |
Optimal design of a low-power, phase-switching modulator for implantable medical applications. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Lucas Lui Motta, Byron Alejandro Acuña Acurio, Nathália Figueiredo Tinoco Aniceto, Luís Geraldo P. Meloni |
Design and implementation of a digital down/up conversion directly from/to RF channels in HDL. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Prathiba Ashok, Kanchana Bhaaskaran Vettuvanam Somasundaram |
Hardware footprints of S-box in lightweight symmetric block ciphers for IoT and CPS information security systems. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Mario Cofano, Marco Vacca, Giulia Santoro, Giovanni Causapruno, Giovanna Turvani, Mariagrazia Graziano |
Exploiting the Logic-In-Memory paradigm for speeding-up data-intensive algorithms. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Eric Schneider, Hans-Joachim Wunderlich |
Multi-level timing and fault simulation on GPUs. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Siva Satyendra Sahoo, Tuan D. A. Nguyen, Bharadwaj Veeravalli, Akash Kumar 0001 |
Multi-objective design space exploration for system partitioning of FPGA-based Dynamic Partially Reconfigurable Systems. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Huyen Pham Thi, Hanho Lee, Xuan Nghia Pham |
Half-row modified two-extra-column trellis min-max decoder architecture for nonbinary LDPC codes. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Tengfei Wang, Wei Guo, Jizeng Wei |
Highly-parallel hardware implementation of optimal ate pairing over Barreto-Naehrig curves. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Himadri Singh Raghav, Izzet Kale |
A balanced power analysis attack resilient adiabatic logic using single charge sharing transistor. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Sherif F. Nafea, Ahmed A. S. Dessouki, S. El-Rabaie 0001, Basem E. Elnaghi, Yehea Ismail, Hassan Mostafa |
An accurate model of domain-wall-based spintronic memristor. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Ferdinando Costanzo, Rocco Giofrè, Antonino Massari, Marziale Feudale, Andrea Suriani, Ernesto Limiti |
A MMIC power amplifier in GaN on Si technology for next generation Q band high throughput satellite systems. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Nan Wang 0003, Song Chen 0001, Zhiyuan Ma, Xiaofeng Ling, Yu Zhu |
Integrating operation scheduling and binding for functional unit power-gating in high-level synthesis. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Raffaele De Rose, Paul Romero, Marco Lanuzza |
Double-precision Dual Mode Logic carry-save multiplier. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Anindita Chakraborty, Vivek Saurabh, Partha Sarathi Gupta, Rituraj Kumar, Saikat Majumdar, Smriti Das, Hafizur Rahaman 0001 |
In-memory designing of Delay and Toggle flip-flops utilizing Memristor Aided loGIC (MAGIC). |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Nguyen Van Toan, Dam Minh Tung, Jeong-Gun Lee |
A GALS design based on multi-frequency clocking for digital switching noise reduction. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Pietro Burrascano, Giulia Di Capua, Nicola Femia, Stefano Laureti, Marco Ricci 0001 |
A Pulse Compression procedure for power inductors modeling up to moderate non-linearity. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Sasan Nikseresht, Seyed Javad Azhari |
A new current-mode computational analog block free from the body-effect. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Manas Kumar Hati, Tarun Kanti Bhattacharyya |
A constant loop bandwidth in delta sigma fractional-N PLL frequency synthesizer with phase noise cancellation. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Jan Moritz Joseph, Lennart Bamberg, Imad Hajjar, Robert Schmidt 0003, Thilo Pionteck, Alberto García Ortiz |
Simulation environment for link energy estimation in networks-on-chip with virtual channels. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Zhen Wang, Jianhui Jiang, Tao Wang |
Failure probability analysis and critical node determination for approximate circuits. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Zhufei Chu, Lei Shi, Lun-Yao Wang, Yinshui Xia |
Multi-objective algebraic rewriting in XOR-majority graphs. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Ke Du 0001, Stéphane Domas, Michel Lenczner |
Actors with stretchable access patterns. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Ji Li 0006, Zihao Yuan, Zhe Li 0001, Ao Ren, Caiwen Ding, Jeffrey Draper, Shahin Nazarian, Qinru Qiu, Bo Yuan 0001, Yanzhi Wang |
Normalization and dropout for stochastic computing-based deep convolutional neural networks. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Azad Mahmoudi, Pooya Torkzadeh, Massoud Dousti |
A study of analog decision feedback equalization for ADC-Based serial link receivers. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Teng Xu 0001, Miodrag Potkonjak |
Circuit power optimization using pipelining and dual-supply voltage assignment. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohd Syafiq Mispan, Shengyu Duan, Basel Halak, Mark Zwolinski |
A reliable PUF in a dual function SRAM. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Kashif Nawaz, Léopold Van Brandt, Itamar Levi, François-Xavier Standaert, Denis Flandre |
A security oriented transient-noise simulation methodology: Evaluation of intrinsic physical noise of cryptographic designs. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Junjun Hu, Zhijing Li 0002, Meng Yang, Zixin Huang, Weikang Qian |
A high-accuracy approximate adder with correct sign calculation. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Abderrazak Arabi, Nacerdine Bourouba, Abdesslam Belaout, Mouloud Ayad |
An accurate classifier based on adaptive neuro-fuzzy and features selection techniques for fault classification in analog circuits. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Lennart Bamberg, Amir Najafi 0001, Alberto García Ortiz |
Edge effect aware low-power crosstalk avoidance technique for 3D integration. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Lihuan Wang, Shuyan Jiang, Shuyu Chen, Junshi Wang, Letian Huang |
Optimized mapping algorithm to extend lifetime of both NoC and cores in many-core system. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Ata Khorami, Roghayeh Saeidi, Manoj Sachdev, Mohammad Sharifkhani |
A low-power dynamic comparator for low-offset applications. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Jiangwei Zhang, Donald Kline Jr., Liang Fang, Rami G. Melhem, Alex K. Jones |
Yielding optimized dependability assurance through bit inversion. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Maedeh Hemmat, Azadeh Davoodi |
Power-efficient ReRAM-aware CNN model generation. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Nikolaos Kefalas, George Theodoridis |
Low-memory and high-performance architectures for the CCSDS 122.0-B-1 compression standard. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Naci Pekcokguler, Günhan Dündar, Catherine Dehollain |
Analysis, modeling and design of a CMOS Super-Regenerative Receiver for implanted medical devices under square and sinusoidal quench signals. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Cheng Zhuo, Baixin Chen |
System-level design consideration and optimization of through-silicon-via inductor. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Barend Harris, Inpyo Bae, Bernhard Egger 0002 |
Architectures and algorithms for on-device user customization of CNNs. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Asghar Bahramali, Marisa López-Vallejo |
A low power RFID based energy harvesting temperature resilient CMOS-only reference voltage. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Sarang Kazeminia |
A real-time pseudo-background gain calibration strategy for residue amplifiers of pipeline ADCs. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Filipe Guimarães Russo Ramos, Thiago P. Mussolini, Robson Luiz Moreno, Tales Cleber Pimenta |
A CMOS temperature-independent current reference optimized for mixed-signal applications. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Xing Wei, Haigang Yang, Wei Li 0008, Zhihong Huang, Tao Yin, Le Yu |
A reconfigurable 4-GS/s power-efficient floating-point FFT processor design and implementation based on single-sided binary-tree decomposition. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Wei Gao 0024, Zhiliang Qian, Pingqiang Zhou |
Reliability- and performance-driven mapping for regular 3D NoCs using a novel latency model and Simulated Allocation. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Shuyan Jiang, Qiong Wu, Shuyu Chen, Junkai Zhan, Junshi Wang, Masoumeh Ebrahimi, Letian Huang |
Testing aware dynamic mapping for path-centric network-on-chip test. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Francisco Veirano, Lirida A. B. Naviner, Fernando Silveira |
Optimal asymmetrical back plane biasing for energy efficient digital circuits in 28 nm UTBB FD-SOI. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Anthony G. Scanlan |
Low power & mobile hardware accelerators for deep convolutional neural networks. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Jeremy Scerri, Ivan Grech, Edward Gatt, Owen Casha |
Dimensional optimisation of a MEMS BPSK to ASK converter in SOIMUMPs. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Ahmad N. Abdulfattah, Charalampos C. Tsimenidis, Alex Yakovlev |
Ultra-low power m-sequence code generator for body sensor node applications. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera |
Area-efficient fully digital memory using minimum height standard cells for near-threshold voltage computing. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
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