Search results for "NoC"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
17	Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi	An evolutionary approach to network-on-chip mapping problem.	Congress on Evolutionary Computation	2005	DBLP DOI BibTeX RDF
17	Rutuparna Tamhankar, Srinivasan Murali, Giovanni De Micheli	Performance driven reliable link design for networks on chips.	ASP-DAC	2005	DBLP DOI BibTeX RDF	aggressive design, performance, reliability, networks on chips, link
17	Huy Nam Nguyen, Vu-Duc Ngo, Hae-Wook Choi	Realization of Video Object Plane Decoder on On-Chip Network Architecture.	ICESS	2005	DBLP DOI BibTeX RDF
17	Leonel Tedesco, Aline Mello 0001, Diego Garibotti, Ney Calazans, Fernando Moraes 0001	Traffic generation and performance evaluation for mesh-based NoCs.	SBCCI	2005	DBLP DOI BibTeX RDF	performance evaluation, networks on chip, traffic modeling
17	Francesco Lertora, Michele Borgatti	Handling Different Computational Granularity by a Reconfigurable IC Featuring Embedded FPGAs and a Network-on-Chip.	FCCM	2005	DBLP DOI BibTeX RDF
17	Jin-Ho Ahn, Byung In Moon, Sungho Kang	A Practical Test Scheduling Using Network-Based TAM in Network on Chip Architecture.	Asia-Pacific Computer Systems Architecture Conference	2005	DBLP DOI BibTeX RDF
17	Matthieu Briere, Emmanuel Drouard, Fabien Mieyeville, David Navarro, Ian O'Connor, Frédéric Gaffiot	Heterogeneous Modelling of an Optical Network-on-Chip with SystemC.	IEEE International Workshop on Rapid System Prototyping	2005	DBLP DOI BibTeX RDF
17	Nicolas Genko, David Atienza, Giovanni De Micheli, Luca Benini, Jose Manuel Mendias, Román Hermida, Francky Catthoor	A novel approach for network on chip emulation.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
17	Kwanho Kim, Se-Joong Lee, Kangmin Lee, Hoi-Jun Yoo	An arbitration look-ahead scheme for reducing end-to-end latency in networks on chip.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
17	Ümit Y. Ogras, Jingcao Hu, Radu Marculescu	Communication-Centric SoC Design for Nanoscale Domain.	ASAP	2005	DBLP DOI BibTeX RDF
17	Hsin-Chou Chi, Chia-Ming Wu	Efficient Switches for Network-on-Chip Based Embedded Systems.	EUC	2005	DBLP DOI BibTeX RDF
17	Chunsheng Liu, Vikram Iyengar, Jiangfan Shi, Érika F. Cota	Power-Aware Test Scheduling in Network-on-Chip Using Variable-Rate On-Chip Clocking.	VTS	2005	DBLP DOI BibTeX RDF
17	Randeep Bhatia, Nicole Immorlica, Tracy Kimbrel, Vahab S. Mirrokni, Seffi Naor, Baruch Schieber	Traffic engineering of management flows by link augmentations on confluent trees.	SPAA	2005	DBLP DOI BibTeX RDF	approximation algorithms, network management, traffic engineering
17	Zhonghai Lu, Axel Jantsch	Traffic Configuration for Evaluating Networks on Chips.	IWSOC	2005	DBLP DOI BibTeX RDF
17	Erno Salminen, Vesa Lahtinen, Tero Kangas, Jouni Riihimäki, Kimmo Kuusilinna, Timo D. Hämäläinen	HIBI v.2 Communication Network for System-on-Chip.	SAMOS	2004	DBLP DOI BibTeX RDF
17	Jiang Xu 0001, Wayne H. Wolf, Jörg Henkel, Srimat T. Chakradhar, Tiehan Lv	A Case Study in Networks-on-Chip Design for Embedded Video.	DATE	2004	DBLP DOI BibTeX RDF
17	Aline Mello 0001, Leandro Möller, Ney Calazans, Fernando Gehm Moraes	MultiNoC: A Multiprocessing System Enabled by a Network on Chip.	DATE	2004	DBLP DOI BibTeX RDF
17	Jingcao Hu, Radu Marculescu	Energy-Aware Communication and Task Scheduling for Network-on-Chip Architectures under Real-Time Constraints.	DATE	2004	DBLP DOI BibTeX RDF
17	Rodrigo Soares, Ivan Saraiva Silva, Arnaldo Azevedo	When reconfigurable architecture meets network-on-chip.	SBCCI	2004	DBLP DOI BibTeX RDF	multiprocessor, system on chip, network on chip, reconfigurable architecture
17	Erland Nilsson, Johnny Öberg	Reducing power and latency in 2-D mesh NoCs using globally pseudochronous locally synchronous clocking.	CODES+ISSS	2004	DBLP DOI BibTeX RDF	hot-potato, pseudochronous, network on chip, mesh, clocking, GALS, GPLS
17	Dongkun Shin, Jihong Kim 0001	Power-aware communication optimization for networks-on-chips with voltage scalable links.	CODES+ISSS	2004	DBLP DOI BibTeX RDF	real-time systems, network-on-chip, low-power design
17	Lukasz Masko	Program Graph Scheduling for SMP Clusters with Communication on-the-Fly Based on Extended DS Approach.	PARELEC	2004	DBLP DOI BibTeX RDF
17	Mikael Millberg, Erland Nilsson, Rikard Thid, Shashi Kumar, Axel Jantsch	The Nostrum Backbone - a Communication Protocol Stack for Networks on Chip.	VLSI Design	2004	DBLP DOI BibTeX RDF
17	Edwin Rijpkema, Kees G. W. Goossens, Andrei Radulescu, John Dielissen, Jef L. van Meerbergen, Paul Wielage, Erwin Waterlander	Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip.	DATE	2003	DBLP DOI BibTeX RDF
17	Erland Nilsson, Mikael Millberg, Johnny Öberg, Axel Jantsch	Load Distribution with the Proximity Congestion Awareness in a Network on Chip.	DATE	2003	DBLP DOI BibTeX RDF
17	Axel Jantsch	NoCs: A new Contract between Hardware and Software.	DSD	2003	DBLP DOI BibTeX RDF
17	Matteo Dall'Osso, Gianluca Biccari, Luca Giovannini, Davide Bertozzi, Luca Benini	xpipes: a Latency Insensitive Parameterized Network-on-chip Architecture For Multi-Processor SoCs.	ICCD	2003	DBLP DOI BibTeX RDF
17	Jian Liu, Li-Rong Zheng 0001, Dinesh Pamunuwa, Hannu Tenhunen	A global wire planning scheme for Network-on-Chip.	ISCAS (4)	2003	DBLP DOI BibTeX RDF
17	Juha-Pekka Soininen, Axel Jantsch, Martti Forsell, Antti Pelkonen, Jari Kreku, Shashi Kumar	Extending Platform-Based Design to Network on Chip Systems.	VLSI Design	2003	DBLP DOI BibTeX RDF
17	Praveen Bhojwani, Rabi N. Mahapatra	Interfacing Cores with On-chip Packet-Switched Networks.	VLSI Design	2003	DBLP DOI BibTeX RDF
17	Li-Wei Wu, Wei-Xiang Tang, Yarsun Hsu	A Novel Architecture and Routing Algorithm for Dynamic Reconfigurable Network-on-Chip.	ISPA	2011	DBLP DOI BibTeX RDF	north-last weave, dynamic reconfigurable, NoC
17	Khalid Latif 0002, Tiberiu Seceleanu, Hannu Tenhunen	Power and Area Efficient Design of Network-on-Chip Router through Utilization of Idle Buffers.	ECBS	2010	DBLP DOI BibTeX RDF	Segbus, Virtual Channel, NoC
17	Daniel Gebhardt, JunBok You, Kenneth S. Stevens	Comparing Energy and Latency of Asynchronous and Synchronous NoCs for Embedded SoCs.	NOCS	2010	DBLP DOI BibTeX RDF	network, CAD, SoC, topology, asynchronous, floorplan, router, EDA, NoC, GALS
17	Tushar N. K. Jain, Paul V. Gratz, Alexander Sprintson, Gwan Choi	Asynchronous Bypass Channels: Improving Performance for Multi-synchronous NoCs.	NOCS	2010	DBLP DOI BibTeX RDF	asynchronous interconnect, NoC, GALS, on-chip networks
17	Jonas Diemer, Rolf Ernst	Back Suction: Service Guarantees for Latency-Sensitive On-chip Networks.	NOCS	2010	DBLP DOI BibTeX RDF	Latency-Sensitive, Quality of Service, QoS, Real-Time, NoC, Manycore
17	Yuri Nishikawa, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano	A Deadlock-Free Non-minimal Fully Adaptive Routing Using Virtual Cut-Through Switching.	NAS	2010	DBLP DOI BibTeX RDF	non-minimal fully adaptive routing, NoC, deadlock-free routing, SAN, turn-model, virtual cut-through
17	Dawid Zydek, Henry Selvaraj, Laxmi P. Gewali	Synthesis of Processor Allocator for Torus-Based Chip MultiProcessors.	ITNG	2010	DBLP DOI BibTeX RDF	FPGA, CMP, mesh, NoC, torus, hardware implementation, processor allocator
17	Jochen Strunk, Toni Volkmer, Wolfgang Rehm, Heiko Schick	Design and Performance of a Grid of Asynchronously Clocked Run-Time Reconfigurable Modules on a FPGA.	ReConFig	2009	DBLP DOI BibTeX RDF	asynchronous FIFO, FPGA, grid, dynamic reconfiguration, NoC, run-time reconfiguration
17	Julien Delorme, Amor Nafkha, Pierre Leray, Christophe Moy	New OPBHWICAP Interface for Realtime Partial Reconfiguration of FPGA.	ReConFig	2009	DBLP DOI BibTeX RDF	FPGA, NoC, SDR, Partial Reconfiguration
17	Ashwini Raina, Venkatesan Muthukumar	Traffic Aware Scheduling Algorithm for Network on Chip.	ITNG	2009	DBLP DOI BibTeX RDF	Scheduling, Mapping, NoC, Simulation framework
17	Ashwini Raina, Venkatesan Muthukumar	Fuse-N: Framework for Unified Simulation Environment for Network-on-Chip.	ITNG	2009	DBLP DOI BibTeX RDF	task scheduling and mapping, NoC, Simulation framework
17	Young Hoon Kang, Jeff Sondeen, Jeffrey T. Draper	Multicast routing with dynamic packet fragmentation.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	on-chip router, interconnection network, NoC
17	Eby G. Friedman	Design challenges in high performance three-dimensional circuits.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	VLSI, NOC, 3-D, clock distribution
17	Yuri Nishikawa, Michihiro Koibuchi, Masato Yoshimi, Akihiro Shitara, Kenichi Miura, Hideharu Amano	Performance Analysis of ClearSpeed's CSX600 Interconnects.	ISPA	2009	DBLP DOI BibTeX RDF	ClearSpeed, CSX600, performance evaluation, SIMD, NoC
17	Shu-Hsuan Chou, Chien-Chih Chen, Chi-Neng Wen, Yi-Chao Chan, Tien-Fu Chen, Chao-Ching Wang, Jinn-Shyan Wang	No cache-coherence: a single-cycle ring interconnection for multi-core L1-NUCA sharing on 3D chips.	DAC	2009	DBLP DOI BibTeX RDF	level-1 non-uniform cache architecture, ring interconnection, single-cycle transactions, multi-core, NOC, SOC, arbitration, memory structure
17	Kwang-Ting (Tim) Cheng	From the EIC.	IEEE Des. Test Comput.	2008	DBLP DOI BibTeX RDF	Chris Rowen, runtime power monitoring, NoC, hybrid approach, simultaneous switching noise, RFIC
17	Ivan Miro Panades, Fabien Clermidy, Pascal Vivet, Alain Greiner	Physical Implementation of the DSPIN Network-on-Chip in the FAUST Architecture.	NOCS	2008	DBLP DOI BibTeX RDF	DSPIN, ANOC, physical implementation, FAUST, bi-synchronous FIFO, network-on-chip, NoC
17	Hiroki Matsutani, Michihiro Koibuchi, Daihan Wang, Hideharu Amano	Adding Slow-Silent Virtual Channels for Low-Power On-Chip Networks.	NOCS	2008	DBLP DOI BibTeX RDF	low power, Network-on-Chip, virtual channels, NoC, DVFS, power gating
17	Yaoting Jiao, Mei Yang, Yingtao Jiang, Yulu Yang, Xiao-chun Yun	Deadlock-Free Multi-Path Routing for Torus-Based NoCs.	ITNG	2008	DBLP DOI BibTeX RDF	deadlock, NoC, MPR
17	Hazem Moussa, Amer Baghdadi, Michel Jézéquel	Binary de Bruijn on-chip network for a flexible multiprocessor LDPC decoder.	DAC	2008	DBLP DOI BibTeX RDF	flexible LDPC decoder, multiprocessor, NoC, de Bruijn graph
17	Erik Jan Marinissen, Axel Jantsch, Nicola Nicolici	DATE 07 workshop on diagnostic services in NoCs.	IEEE Des. Test Comput.	2007	DBLP DOI BibTeX RDF	diagnostic services, DATE 2007, network on chip, NoC
17	Christophe Bobda, Thomas Haller, Felix Mühlbauer, Dennis Rech, Simon Jung	Design of adaptive multiprocessor on chip systems.	SBCCI	2007	DBLP DOI BibTeX RDF	FPGA, reconfigurability, MPSoC, NoC
17	Praveen Bhojwani, Jason D. Lee, Rabi N. Mahapatra	SAPP: scalable and adaptable peak power management in nocs.	ISLPED	2007	DBLP DOI BibTeX RDF	network-on-chip, NoC, peak power
17	Shyam R. Chidamber, David P. Darcy, Chris F. Kemerer	Managerial Use of Metrics for Object-Oriented Software: An Exploratory Analysis.	IEEE Trans. Software Eng.	1998	DBLP DOI BibTeX RDF	SLOC, WMC, DIT, LCOM, CBO, RFC, design, object-orientation, reuse, project management, Software metrics, productivity, NOC, programmer, effort
16	Chifeng Wang, Wen-Hsiang Hu, Seung Eun Lee, Nader Bagherzadeh	Area and Power-efficient Innovative Network-on-Chip Architecurte.	PDP	2010	DBLP DOI BibTeX RDF	interconnection network, system-on-chip (SoC), power-efficient, power-optimization, Network-on-Chip (NoC), area-efficient
16	Somayyeh Koohi, Shaahin Hessabi	Hierarchical on-Chip Routing of Optical Packets in Large Scale MPSoCs.	PDP	2010	DBLP DOI BibTeX RDF	optical NoC, contention-free, scalable, hierarchical
16	Chi-Fu Chang, Yarsun Hsu	A System Exploration Platform for Network-on-Chip.	ISPA	2010	DBLP DOI BibTeX RDF	NoC simulator, Application-driven design, Network on chip, Simulation framework
16	Zheng Liu, Jueping Cai, Ming Du, Lei Yao, Zan Li	Hybrid Communication Reconfigurable Network on Chip for MPSoC.	AINA	2010	DBLP DOI BibTeX RDF	HCR-NoC, low power, interconnection, MPSoC
16	Arghavan Asad, Amir Ehsani Zonouz, Mehrdad Seyrafi, Mohsen Soryani, Mahmood Fathy	Modeling and Analyzing of Blocking Time Effects on Power Consumption in Network-on-Chips.	ReConFig	2009	DBLP DOI BibTeX RDF	Network on Chip(NoC), High Traffic Regions, Packet Blocking Power Consumption, Blocking Time
16	Gerard J. M. Smit, André B. J. Kokkeler, Pascal T. Wolkotte, Marcel D. van de Burgwal	Multi-core architectures and streaming applications.	SLIP	2008	DBLP DOI BibTeX RDF	NoC design, multi-core SoC design, system design, streaming applications
16	Vassos Soteriou, Noel Eisley, Li-Shiuan Peh	Software-directed power-aware interconnection networks.	CASES	2005	DBLP DOI BibTeX RDF	dynamic voltage, networks on-a-chip (NoC), software-directed power reduction, simulation, interconnection networks, scaling, communication links
16	Alexandre M. Amory, Érika F. Cota, Marcelo Lubaszewski, Fernando Gehm Moraes	Reducing test time with processor reuse in network-on-chip based systems.	SBCCI	2004	DBLP DOI BibTeX RDF	NoC testing, computer-aided test (CAT), software-based test, network-on-chip, SoC test, core-based test
16	Peter Zipf, Heiko Hinkelmann, Adeel Ashraf, Manfred Glesner	A switch architecture and signal synchronization for GALS system-on-chips.	SBCCI	2004	DBLP DOI BibTeX RDF	NoC switch, clock stretching, synchronization, GALS
16	Jiang Xu 0001, Wayne H. Wolf	Wave pipelining for application-specific networks-on-chips.	CASES	2002	DBLP DOI BibTeX RDF	system-on-chip (SoC), interconnection, networks-on-chip (NoC), wave pipelining, coupling capacitance
12	Susana Ortega-Cisneros	Design and Implementation of an NoC-Based Convolution Architecture With GEMM and Systolic Arrays.	IEEE Embed. Syst. Lett.	2024	DBLP DOI BibTeX RDF
12	Siyue Li, Shize Zhou, Yongqi Xue, Wenjie Fan, Tong Cheng, Jinlun Ji, Chenyang Dai, Wenqing Song, Qinyu Chen, Chang Gao, Li Li 0003, Yuxiang Fu	HAS-RL: A Hierarchical Approximate Scheme Optimized With Reinforcement Learning for NoC-Based NN Accelerators.	IEEE Trans. Circuits Syst. I Regul. Pap.	2024	DBLP DOI BibTeX RDF
12	Ali M. Al Shahrani, Ali Rizwan, Abdullah Algarni, Khalid A. Alissa, Mohammad Shabaz, Bhupesh Kumar Singh, John Zaki	A Deep Learning Network-on-Chip (NoC)-Based Switch-Router to Enhance Information Security in Resource-Constrained Devices.	J. Circuits Syst. Comput.	2024	DBLP DOI BibTeX RDF
12	Syam Sankar, Ruchika Gupta, John Jose, Sukumar Nandi	TROP: TRust-aware OPportunistic Routing in NoC with Hardware Trojans.	ACM Trans. Design Autom. Electr. Syst.	2024	DBLP DOI BibTeX RDF
12	Maico Cassel dos Santos, Tianyu Jia, Joseph Zuckerman, Martin Cochet, Davide Giri, Erik Jens Loscalzo, Karthik Swaminathan, Thierry Tambe, Jeff Jun Zhang, Alper Buyuktosunoglu, Kuan-Lin Chiu, Giuseppe Di Guglielmo, Paolo Mantovani, Luca Piccolboni, Gabriele Tombesi, David Trilla, John-David Wellman, En-Yu Yang, Aporva Amarnath, Ying Jing, Bakshree Mishra, Joshua Park, Vignesh Suresh, Sarita V. Adve, Pradip Bose, David Brooks 0001, Luca P. Carloni, Kenneth L. Shepard, Gu-Yeon Wei	14.5 A 12nm Linux-SMP-Capable RISC-V SoC with 14 Accelerator Types, Distributed Hardware Power Management and Flexible NoC-Based Data Orchestration.	ISSCC	2024	DBLP DOI BibTeX RDF
12	Seena Vazifedunn, Akram Reza, Midia Reshadi	Low-cost regional-based congestion-aware routing algorithm for 2D mesh NoC.	Int. J. Commun. Syst.	2023	DBLP DOI BibTeX RDF
12	Anurag Kar, Xueyang Liu, Yonghae Kim, Gururaj Saileshwar, Hyesoon Kim, Tushar Krishna	Mitigating Timing-Based NoC Side-Channel Attacks With LLC Remapping.	IEEE Comput. Archit. Lett.	2023	DBLP DOI BibTeX RDF
12	João Fellipe Uller, João Vicente Souto, Pedro Henrique Penna, Márcio Castro 0001, Henrique Cota de Freitas, Jean-François Méhaut	LWMPI: An MPI library for NoC-based lightweight manycore processors with on-chip memory constraints.	Concurr. Comput. Pract. Exp.	2023	DBLP DOI BibTeX RDF
12	Poornima Narayanasamy, Seetharaman Gopalakrishnan	Novel fault tolerance topology using corvus seek algorithm for application specific NoC.	Integr.	2023	DBLP DOI BibTeX RDF
12	Majid Nezarat, Hadi Shahriar Shahhoseini, Masoomeh Momeni	Thermal-aware routing algorithm in partially connected 3D NoC with dynamic availability for elevators.	J. Ambient Intell. Humaniz. Comput.	2023	DBLP DOI BibTeX RDF
12	Rafael Follmann Faccenda, Gustavo Comarú, Luciano Lores Caimi, Fernando Gehm Moraes	A Comprehensive Framework for Systemic Security Management in NoC-Based Many-Cores.	IEEE Access	2023	DBLP DOI BibTeX RDF
12	Williams Yohanna Yerima, Khanh N. Dang, Abderazek Ben Abdallah	R-MaS3N: Robust Mapping of Spiking Neural Networks to 3D-NoC-Based Neuromorphic Systems for Enhanced Reliability.	IEEE Access	2023	DBLP DOI BibTeX RDF
12	Waqar Amin, Fawad Hussain, Sheraz Anjum, Sharoon Saleem, Waqar Ahmad, Mubashir Hussain	HyDra: Hybrid Task Mapping Application Framework for NOC-Based MPSoCs.	IEEE Access	2023	DBLP DOI BibTeX RDF
12	Khanh N. Dang, Nguyen Anh Vu Doan, Ngo-Doanh Nguyen, Abderazek Ben Abdallah	HeterGenMap: An Evolutionary Mapping Framework for Heterogeneous NoC-Based Neuromorphic Systems.	IEEE Access	2023	DBLP DOI BibTeX RDF
12	Yousif Raad Muhsen, Nor Azura Husin, Maslina Binti Zolkepli, Noridayu Bt Manshor, Ahmed Abbas Jasim Al-Hchaimi, Hussein Mohammed Ridha	Enhancing NoC-Based MPSoC Performance: A Predictive Approach With ANN and Guaranteed Convergence Arithmetic Optimization Algorithm.	IEEE Access	2023	DBLP DOI BibTeX RDF
12	Yousif Raad Muhsen, Nor Azura Husin, Maslina Binti Zolkepli, Noridayu Bt Manshor, Ahmed Abbas Jasim Al-Hchaimi	Evaluation of the Routing Algorithms for NoC-Based MPSoC: A Fuzzy Multi-Criteria Decision-Making Approach.	IEEE Access	2023	DBLP DOI BibTeX RDF
12	Williams Yohanna Yerima, Ogbodo Mark Ikechukwu, Khanh N. Dang, Abderazek Ben Abdallah	Fault-Tolerant Spiking Neural Network Mapping Algorithm and Architecture to 3D-NoC-Based Neuromorphic Systems.	IEEE Access	2023	DBLP DOI BibTeX RDF
12	Kun-Chih Chen, Yuan-Hao Liao, Cheng-Ting Chen, Leiqi Wang	Adaptive Machine Learning-Based Proactive Thermal Management for NoC Systems.	IEEE Trans. Very Large Scale Integr. Syst.	2023	DBLP DOI BibTeX RDF
12	Yiming Ouyang, Jiaxin Wang, Chenglong Sun, Qi Wang 0027, Huaguo Liang	URMP: using reconfigurable multicast path for NoC-based deep neural network accelerators.	J. Supercomput.	2023	DBLP DOI BibTeX RDF
12	Cong Thuan Do, Cheol Hong Kim, Sung Woo Chung	Correction to: Aggressive GPU cache bypassing with monolithic 3D-based NoC.	J. Supercomput.	2023	DBLP DOI BibTeX RDF
12	Somnath Mazumdar, Alberto Scionti, Stéphane Zuckerman, Antoni Portero	NoC-based hardware software co-design framework for dataflow thread management.	J. Supercomput.	2023	DBLP DOI BibTeX RDF
12	Cong Thuan Do, Cheol Hong Kim, Sung Woo Chung	Aggressive GPU cache bypassing with monolithic 3D-based NoC.	J. Supercomput.	2023	DBLP DOI BibTeX RDF
12	Sonal Yadav, Vijay Laxmi, Hemangee K. Kapoor, Manoj Singh Gaur, Amit Kumar	Adaptive distribution of control messages for improving bandwidth utilization in multiple NoC.	J. Supercomput.	2023	DBLP DOI BibTeX RDF
12	Sidhartha Sankar Rout, Badri M, Mitali Sinha, Sujay Deb	ReDeSIGN: Reuse of Debug Structures for Improvement in Performance Gain of NoC Based MPSoCs.	IEEE Trans. Emerg. Top. Comput.	2023	DBLP DOI BibTeX RDF
12	Nima Jafarzadeh, Ahmad Jalili, Jafar Ahmad Abed Alzubi, Khosro Rezaee, Yang Liu 0039, Mehdi Gheisari, Bahram Sadeghi Bigham, Amir Javadpour	A novel buffering fault-tolerance approach for network on chip (NoC).	IET Circuits Devices Syst.	2023	DBLP DOI BibTeX RDF
12	Weng Xiaodong, Yi Liu 0060, Changqing Xu, Xiaoling Lin, Linjun Zhan, Shunyao Wang, Dongdong Chen 0010, Yintang Yang	A Machine Learning Mapping Algorithm for NoC Optimization.	Symmetry	2023	DBLP DOI BibTeX RDF
12	Jianwen Luo 0004, Xinzhe Liu, Fupeng Chen, Yajun Ha	HRFF: Hierarchical and Recursive Floorplanning Framework for NoC-Based Scalable Multidie FPGAs.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
12	Yang Li, Pingqiang Zhou	Fast and Accurate NoC Latency Estimation for Application-Specific Traffics via Machine Learning.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
12	Gomatheeshwari B, K. Gopi, Ajisha Mathias	Low-complex resource mapping heuristics for mobile and iot workloads on NoC-HMPSoC architecture.	Microprocess. Microsystems	2023	DBLP DOI BibTeX RDF
12	Anugrah Jain, Vijay Laxmi, Manoj Singh Gaur, Ashish Sharma 0005	An improved reconfiguration algorithm for handling 1-point NoC failures.	Microprocess. Microsystems	2023	DBLP DOI BibTeX RDF
12	Xingyu Meng, Kshitij Raj, Sandip Ray, Kanad Basu	SeVNoC: Security Validation of System-on-Chip Designs With NoC Fabrics.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2023	DBLP DOI BibTeX RDF
12	Zhe Jiang 0004, Xiaotian Dai 0001, Ran Wei, Ian Gray, Zonghua Gu 0001, Qingling Zhao, Shuai Zhao 0004	NPRC-I/O: An NoC-Based Real-Time I/O System With Reduced Contention and Enhanced Predictability.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2023	DBLP DOI BibTeX RDF
12	Afshan Amin Khan, Roohie Naaz Mir, Najeeb-ud-Din Hakim	Scheduling Strategies and Future Directions for NoC: A Systematic Literature Review.	Autom. Control. Comput. Sci.	2023	DBLP DOI BibTeX RDF
12	Dipika Deb, John Jose	ZPP: A Dynamic Technique to Eliminate Cache Pollution in NoC based MPSoCs.	ACM Trans. Embed. Comput. Syst.	2023	DBLP DOI BibTeX RDF
12	Aruru Sai Kumar, B. Naresh Kumar Reddy	An Efficient Real-Time Embedded Application Mapping for NoC Based Multiprocessor System on Chip.	Wirel. Pers. Commun.	2023	DBLP DOI BibTeX RDF
12	T. Nagalaxmi, E. Sreenivasa Rao, P. Chandrasekhar	Design and Performance Analysis of Low Latency Routing Algorithm based NoC for MPSoC.	Int. J. Commun. Networks Inf. Secur.	2023	DBLP DOI BibTeX RDF