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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 1003 occurrences of 375 keywords
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Results
Found 2678 publication records. Showing 2674 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
17 | Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi |
An evolutionary approach to network-on-chip mapping problem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Congress on Evolutionary Computation ![In: Proceedings of the IEEE Congress on Evolutionary Computation, CEC 2005, 2-4 September 2005, Edinburgh, UK, pp. 112-119, 2005, IEEE, 0-7803-9363-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Rutuparna Tamhankar, Srinivasan Murali, Giovanni De Micheli |
Performance driven reliable link design for networks on chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 749-754, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
aggressive design, performance, reliability, networks on chips, link |
17 | Huy Nam Nguyen, Vu-Duc Ngo, Hae-Wook Choi |
Realization of Video Object Plane Decoder on On-Chip Network Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICESS ![In: Embedded Software and Systems, Second International Conference, ICESS 2005, Xi'an, China, December 16-18, 2005, Proceedings, pp. 256-264, 2005, Springer, 3-540-30881-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Leonel Tedesco, Aline Mello 0001, Diego Garibotti, Ney Calazans, Fernando Moraes 0001 |
Traffic generation and performance evaluation for mesh-based NoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2005, Florianolpolis, Brazil, September 4-7, 2005, pp. 184-189, 2005, ACM. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
performance evaluation, networks on chip, traffic modeling |
17 | Francesco Lertora, Michele Borgatti |
Handling Different Computational Granularity by a Reconfigurable IC Featuring Embedded FPGAs and a Network-on-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 13th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2005), 17-20 April 2005, Napa, CA, USA, Proceedings, pp. 45-54, 2005, IEEE Computer Society, 0-7695-2445-1. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Jin-Ho Ahn, Byung In Moon, Sungho Kang |
A Practical Test Scheduling Using Network-Based TAM in Network on Chip Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asia-Pacific Computer Systems Architecture Conference ![In: Advances in Computer Systems Architecture, 10th Asia-Pacific Conference, ACSAC 2005, Singapore, October 24-26, 2005, Proceedings, pp. 614-624, 2005, Springer, 3-540-29643-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Matthieu Briere, Emmanuel Drouard, Fabien Mieyeville, David Navarro, Ian O'Connor, Frédéric Gaffiot |
Heterogeneous Modelling of an Optical Network-on-Chip with SystemC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE International Workshop on Rapid System Prototyping ![In: 16th IEEE International Workshop on Rapid System Prototyping (RSP 2005), 8-10 June 2005, Montreal, Canada, pp. 10-16, 2005, IEEE Computer Society, 0-7695-2361-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Nicolas Genko, David Atienza, Giovanni De Micheli, Luca Benini, Jose Manuel Mendias, Román Hermida, Francky Catthoor |
A novel approach for network on chip emulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 2365-2368, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Kwanho Kim, Se-Joong Lee, Kangmin Lee, Hoi-Jun Yoo |
An arbitration look-ahead scheme for reducing end-to-end latency in networks on chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 2357-2360, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Ümit Y. Ogras, Jingcao Hu, Radu Marculescu |
Communication-Centric SoC Design for Nanoscale Domain. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 16th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2005), 23-25 July 2005, Samos, Greece, pp. 73-78, 2005, IEEE Computer Society, 0-7695-2407-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Hsin-Chou Chi, Chia-Ming Wu |
Efficient Switches for Network-on-Chip Based Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUC ![In: Embedded and Ubiquitous Computing - EUC 2005, International Conference EUC 2005, Nagasaki, Japan, December 6-9, 2005, Proceedings, pp. 67-76, 2005, Springer, 3-540-30807-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Chunsheng Liu, Vikram Iyengar, Jiangfan Shi, Érika F. Cota |
Power-Aware Test Scheduling in Network-on-Chip Using Variable-Rate On-Chip Clocking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 23rd IEEE VLSI Test Symposium (VTS 2005), 1-5 May 2005, Palm Springs, CA, USA, pp. 349-354, 2005, IEEE Computer Society, 0-7695-2314-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Randeep Bhatia, Nicole Immorlica, Tracy Kimbrel, Vahab S. Mirrokni, Seffi Naor, Baruch Schieber |
Traffic engineering of management flows by link augmentations on confluent trees. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPAA ![In: SPAA 2005: Proceedings of the 17th Annual ACM Symposium on Parallelism in Algorithms and Architectures, July 18-20, 2005, Las Vegas, Nevada, USA, pp. 289-298, 2005, ACM, 1-58113-986-1. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
approximation algorithms, network management, traffic engineering |
17 | Zhonghai Lu, Axel Jantsch |
Traffic Configuration for Evaluating Networks on Chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWSOC ![In: Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 20-24 July 2004, Banff, Alberta, Canada, pp. 535-540, 2005, IEEE Computer Society, 0-7695-2403-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Erno Salminen, Vesa Lahtinen, Tero Kangas, Jouni Riihimäki, Kimmo Kuusilinna, Timo D. Hämäläinen |
HIBI v.2 Communication Network for System-on-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Computer Systems: Architectures, Modeling, and Simulation, Third and Fourth International Workshops, SAMOS 2003 and SAMOS 2004, Samos, Greece, July 21-23, 2003 and July 19-21, 2004, Proceedings, pp. 413-422, 2004, Springer, 3-540-22377-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Jiang Xu 0001, Wayne H. Wolf, Jörg Henkel, Srimat T. Chakradhar, Tiehan Lv |
A Case Study in Networks-on-Chip Design for Embedded Video. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 770-777, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Aline Mello 0001, Leandro Möller, Ney Calazans, Fernando Gehm Moraes |
MultiNoC: A Multiprocessing System Enabled by a Network on Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 234-239, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Jingcao Hu, Radu Marculescu |
Energy-Aware Communication and Task Scheduling for Network-on-Chip Architectures under Real-Time Constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 234-239, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Rodrigo Soares, Ivan Saraiva Silva, Arnaldo Azevedo |
When reconfigurable architecture meets network-on-chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2004, Pernambuco, Brazil, September 7-11, 2004, pp. 216-221, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
multiprocessor, system on chip, network on chip, reconfigurable architecture |
17 | Erland Nilsson, Johnny Öberg |
Reducing power and latency in 2-D mesh NoCs using globally pseudochronous locally synchronous clocking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2004, Stockholm, Sweden, September 8-10, 2004, pp. 176-181, 2004, ACM, 1-58113-937-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
hot-potato, pseudochronous, network on chip, mesh, clocking, GALS, GPLS |
17 | Dongkun Shin, Jihong Kim 0001 |
Power-aware communication optimization for networks-on-chips with voltage scalable links. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2004, Stockholm, Sweden, September 8-10, 2004, pp. 170-175, 2004, ACM, 1-58113-937-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
real-time systems, network-on-chip, low-power design |
17 | Lukasz Masko |
Program Graph Scheduling for SMP Clusters with Communication on-the-Fly Based on Extended DS Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PARELEC ![In: 2004 International Conference on Parallel Computing in Electrical Engineering (PARELEC 2004), 7-10 September 2004, Dresden, Germany, pp. 65-70, 2004, IEEE Computer Society, 0-7695-2080-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Mikael Millberg, Erland Nilsson, Rikard Thid, Shashi Kumar, Axel Jantsch |
The Nostrum Backbone - a Communication Protocol Stack for Networks on Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 17th International Conference on VLSI Design (VLSI Design 2004), with the 3rd International Conference on Embedded Systems Design, 5-9 January 2004, Mumbai, India, pp. 693-696, 2004, IEEE Computer Society, 0-7695-2072-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Edwin Rijpkema, Kees G. W. Goossens, Andrei Radulescu, John Dielissen, Jef L. van Meerbergen, Paul Wielage, Erwin Waterlander |
Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany, pp. 10350-10355, 2003, IEEE Computer Society, 0-7695-1870-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Erland Nilsson, Mikael Millberg, Johnny Öberg, Axel Jantsch |
Load Distribution with the Proximity Congestion Awareness in a Network on Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany, pp. 11126-11127, 2003, IEEE Computer Society, 0-7695-1870-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Axel Jantsch |
NoCs: A new Contract between Hardware and Software. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 2003 Euromicro Symposium on Digital Systems Design (DSD 2003), Architectures, Methods and Tools, 3-5 September 2003, Belek-Antalya, Turkey, pp. 10-16, 2003, IEEE Computer Society, 0-7695-2003-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Matteo Dall'Osso, Gianluca Biccari, Luca Giovannini, Davide Bertozzi, Luca Benini |
xpipes: a Latency Insensitive Parameterized Network-on-chip Architecture For Multi-Processor SoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 21st International Conference on Computer Design (ICCD 2003),VLSI in Computers and Processors, 13-15 October 2003, San Jose, CA, USA, Proceedings, pp. 536-, 2003, IEEE Computer Society, 0-7695-2025-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Jian Liu, Li-Rong Zheng 0001, Dinesh Pamunuwa, Hannu Tenhunen |
A global wire planning scheme for Network-on-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 892-895, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Juha-Pekka Soininen, Axel Jantsch, Martti Forsell, Antti Pelkonen, Jari Kreku, Shashi Kumar |
Extending Platform-Based Design to Network on Chip Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 16th International Conference on VLSI Design (VLSI Design 2003), 4-8 January 2003, New Delhi, India, pp. 401-, 2003, IEEE Computer Society, 0-7695-1868-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Praveen Bhojwani, Rabi N. Mahapatra |
Interfacing Cores with On-chip Packet-Switched Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 16th International Conference on VLSI Design (VLSI Design 2003), 4-8 January 2003, New Delhi, India, pp. 382-387, 2003, IEEE Computer Society, 0-7695-1868-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Li-Wei Wu, Wei-Xiang Tang, Yarsun Hsu |
A Novel Architecture and Routing Algorithm for Dynamic Reconfigurable Network-on-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPA ![In: IEEE International Symposium on Parallel and Distributed Processing with Applications, ISPA 2011, Busan, Korea, 26-28 May, 2011, pp. 177-182, 2011, IEEE Computer Society, 978-1-4577-0391-1. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
north-last weave, dynamic reconfigurable, NoC |
17 | Khalid Latif 0002, Tiberiu Seceleanu, Hannu Tenhunen |
Power and Area Efficient Design of Network-on-Chip Router through Utilization of Idle Buffers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECBS ![In: 17th IEEE International Conference and Workshops on the Engineering of Computer-Based Systems, ECBS 2010, Oxford, England, UK, 22-26 March 2010, pp. 131-138, 2010, IEEE Computer Society, 978-0-7695-4005-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
Segbus, Virtual Channel, NoC |
17 | Daniel Gebhardt, JunBok You, Kenneth S. Stevens |
Comparing Energy and Latency of Asynchronous and Synchronous NoCs for Embedded SoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NOCS ![In: NOCS 2010, Fourth ACM/IEEE International Symposium on Networks-on-Chip, Grenoble, France, May 3-6, 2010, pp. 115-122, 2010, IEEE Computer Society, 978-0-7695-4053-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
network, CAD, SoC, topology, asynchronous, floorplan, router, EDA, NoC, GALS |
17 | Tushar N. K. Jain, Paul V. Gratz, Alexander Sprintson, Gwan Choi |
Asynchronous Bypass Channels: Improving Performance for Multi-synchronous NoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NOCS ![In: NOCS 2010, Fourth ACM/IEEE International Symposium on Networks-on-Chip, Grenoble, France, May 3-6, 2010, pp. 51-58, 2010, IEEE Computer Society, 978-0-7695-4053-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
asynchronous interconnect, NoC, GALS, on-chip networks |
17 | Jonas Diemer, Rolf Ernst |
Back Suction: Service Guarantees for Latency-Sensitive On-chip Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NOCS ![In: NOCS 2010, Fourth ACM/IEEE International Symposium on Networks-on-Chip, Grenoble, France, May 3-6, 2010, pp. 155-162, 2010, IEEE Computer Society, 978-0-7695-4053-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
Latency-Sensitive, Quality of Service, QoS, Real-Time, NoC, Manycore |
17 | Yuri Nishikawa, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano |
A Deadlock-Free Non-minimal Fully Adaptive Routing Using Virtual Cut-Through Switching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NAS ![In: Fifth International Conference on Networking, Architecture, and Storage, NAS 2010, Macau, China, July 15-17, 2010, pp. 431-438, 2010, IEEE Computer Society, 978-0-7695-4134-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
non-minimal fully adaptive routing, NoC, deadlock-free routing, SAN, turn-model, virtual cut-through |
17 | Dawid Zydek, Henry Selvaraj, Laxmi P. Gewali |
Synthesis of Processor Allocator for Torus-Based Chip MultiProcessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITNG ![In: Seventh International Conference on Information Technology: New Generations, ITNG 2010, Las Vegas, Nevada, USA, 12-14 April 2010, pp. 13-18, 2010, IEEE Computer Society, 978-0-7695-3984-3. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
FPGA, CMP, mesh, NoC, torus, hardware implementation, processor allocator |
17 | Jochen Strunk, Toni Volkmer, Wolfgang Rehm, Heiko Schick |
Design and Performance of a Grid of Asynchronously Clocked Run-Time Reconfigurable Modules on a FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ReConFig ![In: ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, Cancun, Quintana Roo, Mexico, 9-11 December 2009, Proceedings, pp. 392-397, 2009, IEEE Computer Society, 978-0-7695-3917-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
asynchronous FIFO, FPGA, grid, dynamic reconfiguration, NoC, run-time reconfiguration |
17 | Julien Delorme, Amor Nafkha, Pierre Leray, Christophe Moy |
New OPBHWICAP Interface for Realtime Partial Reconfiguration of FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ReConFig ![In: ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, Cancun, Quintana Roo, Mexico, 9-11 December 2009, Proceedings, pp. 386-391, 2009, IEEE Computer Society, 978-0-7695-3917-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
FPGA, NoC, SDR, Partial Reconfiguration |
17 | Ashwini Raina, Venkatesan Muthukumar |
Traffic Aware Scheduling Algorithm for Network on Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITNG ![In: Sixth International Conference on Information Technology: New Generations, ITNG 2009, Las Vegas, Nevada, USA, 27-29 April 2009, pp. 877-882, 2009, IEEE Computer Society, 978-0-7695-3596-8. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Scheduling, Mapping, NoC, Simulation framework |
17 | Ashwini Raina, Venkatesan Muthukumar |
Fuse-N: Framework for Unified Simulation Environment for Network-on-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITNG ![In: Sixth International Conference on Information Technology: New Generations, ITNG 2009, Las Vegas, Nevada, USA, 27-29 April 2009, pp. 871-876, 2009, IEEE Computer Society, 978-0-7695-3596-8. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
task scheduling and mapping, NoC, Simulation framework |
17 | Young Hoon Kang, Jeff Sondeen, Jeffrey T. Draper |
Multicast routing with dynamic packet fragmentation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009, pp. 113-116, 2009, ACM, 978-1-60558-522-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
on-chip router, interconnection network, NoC |
17 | Eby G. Friedman |
Design challenges in high performance three-dimensional circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009, pp. 281-282, 2009, ACM, 978-1-60558-522-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
VLSI, NOC, 3-D, clock distribution |
17 | Yuri Nishikawa, Michihiro Koibuchi, Masato Yoshimi, Akihiro Shitara, Kenichi Miura, Hideharu Amano |
Performance Analysis of ClearSpeed's CSX600 Interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPA ![In: IEEE International Symposium on Parallel and Distributed Processing with Applications, ISPA 2009, Chengdu, Sichuan, China, 10-12 August 2009, pp. 203-210, 2009, IEEE Computer Society, 978-0-7695-3747-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
ClearSpeed, CSX600, performance evaluation, SIMD, NoC |
17 | Shu-Hsuan Chou, Chien-Chih Chen, Chi-Neng Wen, Yi-Chao Chan, Tien-Fu Chen, Chao-Ching Wang, Jinn-Shyan Wang |
No cache-coherence: a single-cycle ring interconnection for multi-core L1-NUCA sharing on 3D chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 587-592, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
level-1 non-uniform cache architecture, ring interconnection, single-cycle transactions, multi-core, NOC, SOC, arbitration, memory structure |
17 | Kwang-Ting (Tim) Cheng |
From the EIC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 25(1), pp. 4, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Chris Rowen, runtime power monitoring, NoC, hybrid approach, simultaneous switching noise, RFIC |
17 | Ivan Miro Panades, Fabien Clermidy, Pascal Vivet, Alain Greiner |
Physical Implementation of the DSPIN Network-on-Chip in the FAUST Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NOCS ![In: Second International Symposium on Networks-on-Chips, NOCS 2008, 5-6 April 2008, Newcastle University, UK. Proceedings, pp. 139-148, 2008, IEEE Computer Society, 978-0-7695-3098-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
DSPIN, ANOC, physical implementation, FAUST, bi-synchronous FIFO, network-on-chip, NoC |
17 | Hiroki Matsutani, Michihiro Koibuchi, Daihan Wang, Hideharu Amano |
Adding Slow-Silent Virtual Channels for Low-Power On-Chip Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NOCS ![In: Second International Symposium on Networks-on-Chips, NOCS 2008, 5-6 April 2008, Newcastle University, UK. Proceedings, pp. 23-32, 2008, IEEE Computer Society, 978-0-7695-3098-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
low power, Network-on-Chip, virtual channels, NoC, DVFS, power gating |
17 | Yaoting Jiao, Mei Yang, Yingtao Jiang, Yulu Yang, Xiao-chun Yun |
Deadlock-Free Multi-Path Routing for Torus-Based NoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITNG ![In: Fifth International Conference on Information Technology: New Generations (ITNG 2008), 7-8 April 2008, Las Vegas, Nevada, USA, pp. 253-258, 2008, IEEE Computer Society, 978-0-7695-3099-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
deadlock, NoC, MPR |
17 | Hazem Moussa, Amer Baghdadi, Michel Jézéquel |
Binary de Bruijn on-chip network for a flexible multiprocessor LDPC decoder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 429-434, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
flexible LDPC decoder, multiprocessor, NoC, de Bruijn graph |
17 | Erik Jan Marinissen, Axel Jantsch, Nicola Nicolici |
DATE 07 workshop on diagnostic services in NoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 24(5), pp. 510, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
diagnostic services, DATE 2007, network on chip, NoC |
17 | Christophe Bobda, Thomas Haller, Felix Mühlbauer, Dennis Rech, Simon Jung |
Design of adaptive multiprocessor on chip systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2007, Copacabana, Rio de Janeiro, Brazil, September 3-6, 2007, pp. 177-183, 2007, ACM, 978-1-59593-816-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
FPGA, reconfigurability, MPSoC, NoC |
17 | Praveen Bhojwani, Jason D. Lee, Rabi N. Mahapatra |
SAPP: scalable and adaptable peak power management in nocs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007, Portland, OR, USA, August 27-29, 2007, pp. 340-345, 2007, ACM, 978-1-59593-709-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
network-on-chip, NoC, peak power |
17 | Shyam R. Chidamber, David P. Darcy, Chris F. Kemerer |
Managerial Use of Metrics for Object-Oriented Software: An Exploratory Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 24(8), pp. 629-639, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
SLOC, WMC, DIT, LCOM, CBO, RFC, design, object-orientation, reuse, project management, Software metrics, productivity, NOC, programmer, effort |
16 | Chifeng Wang, Wen-Hsiang Hu, Seung Eun Lee, Nader Bagherzadeh |
Area and Power-efficient Innovative Network-on-Chip Architecurte. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDP ![In: Proceedings of the 18th Euromicro Conference on Parallel, Distributed and Network-based Processing, PDP 2010, Pisa, Italy, February 17-19, 2010, pp. 533-539, 2010, IEEE Computer Society, 978-0-7695-3939-3. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
interconnection network, system-on-chip (SoC), power-efficient, power-optimization, Network-on-Chip (NoC), area-efficient |
16 | Somayyeh Koohi, Shaahin Hessabi |
Hierarchical on-Chip Routing of Optical Packets in Large Scale MPSoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDP ![In: Proceedings of the 18th Euromicro Conference on Parallel, Distributed and Network-based Processing, PDP 2010, Pisa, Italy, February 17-19, 2010, pp. 515-524, 2010, IEEE Computer Society, 978-0-7695-3939-3. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
optical NoC, contention-free, scalable, hierarchical |
16 | Chi-Fu Chang, Yarsun Hsu |
A System Exploration Platform for Network-on-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPA ![In: IEEE International Symposium on Parallel and Distributed Processing with Applications, ISPA 2010, Taipei, Taiwan, 6-9 September 2010, pp. 359-366, 2010, IEEE Computer Society, 978-1-4244-8095-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
NoC simulator, Application-driven design, Network on chip, Simulation framework |
16 | Zheng Liu, Jueping Cai, Ming Du, Lei Yao, Zan Li |
Hybrid Communication Reconfigurable Network on Chip for MPSoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AINA ![In: 24th IEEE International Conference on Advanced Information Networking and Applications, AINA 2010, Perth, Australia, 20-13 April 2010, pp. 356-361, 2010, IEEE Computer Society, 978-0-7695-4018-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
HCR-NoC, low power, interconnection, MPSoC |
16 | Arghavan Asad, Amir Ehsani Zonouz, Mehrdad Seyrafi, Mohsen Soryani, Mahmood Fathy |
Modeling and Analyzing of Blocking Time Effects on Power Consumption in Network-on-Chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ReConFig ![In: ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, Cancun, Quintana Roo, Mexico, 9-11 December 2009, Proceedings, pp. 290-295, 2009, IEEE Computer Society, 978-0-7695-3917-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Network on Chip(NoC), High Traffic Regions, Packet Blocking Power Consumption, Blocking Time |
16 | Gerard J. M. Smit, André B. J. Kokkeler, Pascal T. Wolkotte, Marcel D. van de Burgwal |
Multi-core architectures and streaming applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Tenth International Workshop on System-Level Interconnect Prediction (SLIP 2008), Newcastle, UK, April 5-8, 2008, Proceedings, pp. 35-42, 2008, ACM, 978-1-59593-918-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
NoC design, multi-core SoC design, system design, streaming applications |
16 | Vassos Soteriou, Noel Eisley, Li-Shiuan Peh |
Software-directed power-aware interconnection networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2005 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2005, San Francisco, California, USA, September 24-27, 2005, pp. 274-285, 2005, ACM, 1-59593-149-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
dynamic voltage, networks on-a-chip (NoC), software-directed power reduction, simulation, interconnection networks, scaling, communication links |
16 | Alexandre M. Amory, Érika F. Cota, Marcelo Lubaszewski, Fernando Gehm Moraes |
Reducing test time with processor reuse in network-on-chip based systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2004, Pernambuco, Brazil, September 7-11, 2004, pp. 111-116, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
NoC testing, computer-aided test (CAT), software-based test, network-on-chip, SoC test, core-based test |
16 | Peter Zipf, Heiko Hinkelmann, Adeel Ashraf, Manfred Glesner |
A switch architecture and signal synchronization for GALS system-on-chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2004, Pernambuco, Brazil, September 7-11, 2004, pp. 210-215, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
NoC switch, clock stretching, synchronization, GALS |
16 | Jiang Xu 0001, Wayne H. Wolf |
Wave pipelining for application-specific networks-on-chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2002, Greenoble, France, October 8-11, 2002, pp. 198-201, 2002, ACM, 1-58113-575-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
system-on-chip (SoC), interconnection, networks-on-chip (NoC), wave pipelining, coupling capacitance |
12 | Susana Ortega-Cisneros |
Design and Implementation of an NoC-Based Convolution Architecture With GEMM and Systolic Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Embed. Syst. Lett. ![In: IEEE Embed. Syst. Lett. 16(1), pp. 49-52, March 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
12 | Siyue Li, Shize Zhou, Yongqi Xue, Wenjie Fan, Tong Cheng, Jinlun Ji, Chenyang Dai, Wenqing Song, Qinyu Chen, Chang Gao, Li Li 0003, Yuxiang Fu |
HAS-RL: A Hierarchical Approximate Scheme Optimized With Reinforcement Learning for NoC-Based NN Accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 71(4), pp. 1863-1875, April 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
12 | Ali M. Al Shahrani, Ali Rizwan, Abdullah Algarni, Khalid A. Alissa, Mohammad Shabaz, Bhupesh Kumar Singh, John Zaki |
A Deep Learning Network-on-Chip (NoC)-Based Switch-Router to Enhance Information Security in Resource-Constrained Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 33(4), pp. 2450064:1-2450064:30, March 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
12 | Syam Sankar, Ruchika Gupta, John Jose, Sukumar Nandi |
TROP: TRust-aware OPportunistic Routing in NoC with Hardware Trojans. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 29(2), pp. 34:1-34:25, March 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
12 | Maico Cassel dos Santos, Tianyu Jia, Joseph Zuckerman, Martin Cochet, Davide Giri, Erik Jens Loscalzo, Karthik Swaminathan, Thierry Tambe, Jeff Jun Zhang, Alper Buyuktosunoglu, Kuan-Lin Chiu, Giuseppe Di Guglielmo, Paolo Mantovani, Luca Piccolboni, Gabriele Tombesi, David Trilla, John-David Wellman, En-Yu Yang, Aporva Amarnath, Ying Jing, Bakshree Mishra, Joshua Park, Vignesh Suresh, Sarita V. Adve, Pradip Bose, David Brooks 0001, Luca P. Carloni, Kenneth L. Shepard, Gu-Yeon Wei |
14.5 A 12nm Linux-SMP-Capable RISC-V SoC with 14 Accelerator Types, Distributed Hardware Power Management and Flexible NoC-Based Data Orchestration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: IEEE International Solid-State Circuits Conference, ISSCC 2024, San Francisco, CA, USA, February 18-22, 2024, pp. 262-264, 2024, IEEE, 979-8-3503-0620-0. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
12 | Seena Vazifedunn, Akram Reza, Midia Reshadi |
Low-cost regional-based congestion-aware routing algorithm for 2D mesh NoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Commun. Syst. ![In: Int. J. Commun. Syst. 36(1), 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
12 | Anurag Kar, Xueyang Liu, Yonghae Kim, Gururaj Saileshwar, Hyesoon Kim, Tushar Krishna |
Mitigating Timing-Based NoC Side-Channel Attacks With LLC Remapping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Comput. Archit. Lett. ![In: IEEE Comput. Archit. Lett. 22(1), pp. 53-56, January - June 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
12 | João Fellipe Uller, João Vicente Souto, Pedro Henrique Penna, Márcio Castro 0001, Henrique Cota de Freitas, Jean-François Méhaut |
LWMPI: An MPI library for NoC-based lightweight manycore processors with on-chip memory constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Concurr. Comput. Pract. Exp. ![In: Concurr. Comput. Pract. Exp. 35(17), 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
12 | Poornima Narayanasamy, Seetharaman Gopalakrishnan |
Novel fault tolerance topology using corvus seek algorithm for application specific NoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 89, pp. 146-154, March 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
12 | Majid Nezarat, Hadi Shahriar Shahhoseini, Masoomeh Momeni |
Thermal-aware routing algorithm in partially connected 3D NoC with dynamic availability for elevators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Ambient Intell. Humaniz. Comput. ![In: J. Ambient Intell. Humaniz. Comput. 14(8), pp. 10731-10744, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
12 | Rafael Follmann Faccenda, Gustavo Comarú, Luciano Lores Caimi, Fernando Gehm Moraes |
A Comprehensive Framework for Systemic Security Management in NoC-Based Many-Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 11, pp. 131836-131847, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
12 | Williams Yohanna Yerima, Khanh N. Dang, Abderazek Ben Abdallah |
R-MaS3N: Robust Mapping of Spiking Neural Networks to 3D-NoC-Based Neuromorphic Systems for Enhanced Reliability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 11, pp. 94664-94678, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
12 | Waqar Amin, Fawad Hussain, Sheraz Anjum, Sharoon Saleem, Waqar Ahmad, Mubashir Hussain |
HyDra: Hybrid Task Mapping Application Framework for NOC-Based MPSoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 11, pp. 52309-52326, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
12 | Khanh N. Dang, Nguyen Anh Vu Doan, Ngo-Doanh Nguyen, Abderazek Ben Abdallah |
HeterGenMap: An Evolutionary Mapping Framework for Heterogeneous NoC-Based Neuromorphic Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 11, pp. 144095-144112, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
12 | Yousif Raad Muhsen, Nor Azura Husin, Maslina Binti Zolkepli, Noridayu Bt Manshor, Ahmed Abbas Jasim Al-Hchaimi, Hussein Mohammed Ridha |
Enhancing NoC-Based MPSoC Performance: A Predictive Approach With ANN and Guaranteed Convergence Arithmetic Optimization Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 11, pp. 90143-90157, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
12 | Yousif Raad Muhsen, Nor Azura Husin, Maslina Binti Zolkepli, Noridayu Bt Manshor, Ahmed Abbas Jasim Al-Hchaimi |
Evaluation of the Routing Algorithms for NoC-Based MPSoC: A Fuzzy Multi-Criteria Decision-Making Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 11, pp. 102806-102827, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
12 | Williams Yohanna Yerima, Ogbodo Mark Ikechukwu, Khanh N. Dang, Abderazek Ben Abdallah |
Fault-Tolerant Spiking Neural Network Mapping Algorithm and Architecture to 3D-NoC-Based Neuromorphic Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 11, pp. 52429-52443, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
12 | Kun-Chih Chen, Yuan-Hao Liao, Cheng-Ting Chen, Leiqi Wang |
Adaptive Machine Learning-Based Proactive Thermal Management for NoC Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 31(8), pp. 1114-1127, August 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
12 | Yiming Ouyang, Jiaxin Wang, Chenglong Sun, Qi Wang 0027, Huaguo Liang |
URMP: using reconfigurable multicast path for NoC-based deep neural network accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 79(13), pp. 14827-14847, September 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
12 | Cong Thuan Do, Cheol Hong Kim, Sung Woo Chung |
Correction to: Aggressive GPU cache bypassing with monolithic 3D-based NoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 79(6), pp. 7061, April 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
12 | Somnath Mazumdar, Alberto Scionti, Stéphane Zuckerman, Antoni Portero |
NoC-based hardware software co-design framework for dataflow thread management. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 79(16), pp. 17983-18020, November 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
12 | Cong Thuan Do, Cheol Hong Kim, Sung Woo Chung |
Aggressive GPU cache bypassing with monolithic 3D-based NoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 79(5), pp. 5421-5442, March 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
12 | Sonal Yadav, Vijay Laxmi, Hemangee K. Kapoor, Manoj Singh Gaur, Amit Kumar |
Adaptive distribution of control messages for improving bandwidth utilization in multiple NoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 79(15), pp. 17208-17246, October 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
12 | Sidhartha Sankar Rout, Badri M, Mitali Sinha, Sujay Deb |
ReDeSIGN: Reuse of Debug Structures for Improvement in Performance Gain of NoC Based MPSoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Emerg. Top. Comput. ![In: IEEE Trans. Emerg. Top. Comput. 11(2), pp. 432-447, April - June 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
12 | Nima Jafarzadeh, Ahmad Jalili, Jafar Ahmad Abed Alzubi, Khosro Rezaee, Yang Liu 0039, Mehdi Gheisari, Bahram Sadeghi Bigham, Amir Javadpour |
A novel buffering fault-tolerance approach for network on chip (NoC). ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Circuits Devices Syst. ![In: IET Circuits Devices Syst. 17(4), pp. 250-257, July 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
12 | Weng Xiaodong, Yi Liu 0060, Changqing Xu, Xiaoling Lin, Linjun Zhan, Shunyao Wang, Dongdong Chen 0010, Yintang Yang |
A Machine Learning Mapping Algorithm for NoC Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Symmetry ![In: Symmetry 15(3), pp. 593, February 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
12 | Jianwen Luo 0004, Xinzhe Liu, Fupeng Chen, Yajun Ha |
HRFF: Hierarchical and Recursive Floorplanning Framework for NoC-Based Scalable Multidie FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 70(11), pp. 4295-4308, November 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
12 | Yang Li, Pingqiang Zhou |
Fast and Accurate NoC Latency Estimation for Application-Specific Traffics via Machine Learning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 70(9), pp. 3569-3573, September 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
12 | Gomatheeshwari B, K. Gopi, Ajisha Mathias |
Low-complex resource mapping heuristics for mobile and iot workloads on NoC-HMPSoC architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 98, pp. 104802, April 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
12 | Anugrah Jain, Vijay Laxmi, Manoj Singh Gaur, Ashish Sharma 0005 |
An improved reconfiguration algorithm for handling 1-point NoC failures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 101, pp. 104910, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
12 | Xingyu Meng, Kshitij Raj, Sandip Ray, Kanad Basu |
SeVNoC: Security Validation of System-on-Chip Designs With NoC Fabrics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(2), pp. 672-682, February 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
12 | Zhe Jiang 0004, Xiaotian Dai 0001, Ran Wei, Ian Gray, Zonghua Gu 0001, Qingling Zhao, Shuai Zhao 0004 |
NPRC-I/O: An NoC-Based Real-Time I/O System With Reduced Contention and Enhanced Predictability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(12), pp. 4629-4642, December 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
12 | Afshan Amin Khan, Roohie Naaz Mir, Najeeb-ud-Din Hakim |
Scheduling Strategies and Future Directions for NoC: A Systematic Literature Review. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Autom. Control. Comput. Sci. ![In: Autom. Control. Comput. Sci. 57(4), pp. 413-421, August 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
12 | Dipika Deb, John Jose |
ZPP: A Dynamic Technique to Eliminate Cache Pollution in NoC based MPSoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 22(5s), pp. 118:1-118:25, October 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
12 | Aruru Sai Kumar, B. Naresh Kumar Reddy |
An Efficient Real-Time Embedded Application Mapping for NoC Based Multiprocessor System on Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Wirel. Pers. Commun. ![In: Wirel. Pers. Commun. 128(4), pp. 2937-2952, February 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
12 | T. Nagalaxmi, E. Sreenivasa Rao, P. Chandrasekhar |
Design and Performance Analysis of Low Latency Routing Algorithm based NoC for MPSoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Commun. Networks Inf. Secur. ![In: Int. J. Commun. Networks Inf. Secur. 14(1s), pp. 37-53, January 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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