Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
1 | Fabrice Guigues, Edith Kussener, Benjamin Duval, Hervé Barthélemy |
Moderate Inversion: Highlights for Low Voltage Design. |
PATMOS |
2007 |
DBLP DOI BibTeX RDF |
|
1 | Ani Nahapetian, Foad Dabiri, Miodrag Potkonjak, Majid Sarrafzadeh |
Optimization for Real-Time Systems with Non-convex Power Versus Speed Models. |
PATMOS |
2007 |
DBLP DOI BibTeX RDF |
|
1 | Foad Dabiri, Ani Nahapetian, Miodrag Potkonjak, Majid Sarrafzadeh |
Soft Error-Aware Power Optimization Using Gate Sizing. |
PATMOS |
2007 |
DBLP DOI BibTeX RDF |
|
1 | Sylvain Miermont, Pascal Vivet, Marc Renaudin |
A Power Supply Selector for Energy- and Area-Efficient Local Dynamic Voltage Scaling. |
PATMOS |
2007 |
DBLP DOI BibTeX RDF |
|
1 | Cosmin Popa |
Low-Voltage Low-Power Curvature-Corrected Voltage Reference Circuit Using DTMOSTs. |
PATMOS |
2007 |
DBLP DOI BibTeX RDF |
|
1 | Andrea Pugliese 0002, Gregorio Cappuccino, Giuseppe Cocorullo |
Settling Time Minimization of Operational Amplifiers. |
PATMOS |
2007 |
DBLP DOI BibTeX RDF |
|
1 | Paulo F. Butzen, André Inácio Reis, Chris H. Kim, Renato P. Ribas |
Subthreshold Leakage Modeling and Estimation of General CMOS Complex Gates. |
PATMOS |
2007 |
DBLP DOI BibTeX RDF |
|
1 | Francesco Centurelli, Luca Giancane, Mauro Olivieri, Giuseppe Scotti, Alessandro Trifiletti |
A Statistical Model of Logic Gates for Monte Carlo Simulation Including On-Chip Variations. |
PATMOS |
2007 |
DBLP DOI BibTeX RDF |
|
1 | Harry I. A. Chen, Edward K. W. Loo, James B. Kuo, Marek Syrzycki |
Triple-Threshold Static Power Minimization in High-Level Synthesis of VLSI CMOS. |
PATMOS |
2007 |
DBLP DOI BibTeX RDF |
|
1 | Mandeep Singh, Christophe Giacomotto, Bart R. Zeydel, Vojin G. Oklobdzija |
Logic Style Comparison for Ultra Low Power Operation in 65nm Technology. |
PATMOS |
2007 |
DBLP DOI BibTeX RDF |
|
1 | Saleh Abdel-Hafeez, Shadi M. Harb, William R. Eisenstadt |
Low-Power Content Addressable Memory With Read/Write and Matched Mask Ports. |
PATMOS |
2007 |
DBLP DOI BibTeX RDF |
pre-charge, sense amplifier, 6T-cell, 8T-cell, low power, CAM |
1 | Hendrik Eeckhaut, Harald Devos, Dirk Stroobandt |
The Energy Scalability of Wavelet-Based, Scalable Video Decoding. |
PATMOS |
2007 |
DBLP DOI BibTeX RDF |
|
1 | Nikolas Kroupis, Dimitrios Soudris |
Design Methodology and Software Tool for Estimation of Multi-level Instruction Cache Memory Miss Rate. |
PATMOS |
2007 |
DBLP DOI BibTeX RDF |
|
1 | Sven Rosinger, Domenik Helms, Wolfgang Nebel |
RTL Power Modeling and Estimation of Sleep Transistor Based Power Gating. |
PATMOS |
2007 |
DBLP DOI BibTeX RDF |
|
1 | Hong Luo, Yu Wang 0002, Ku He, Rong Luo, Huazhong Yang, Yuan Xie 0001 |
A Novel Gate-Level NBTI Delay Degradation Model with Stacking Effect. |
PATMOS |
2007 |
DBLP DOI BibTeX RDF |
|
1 | David Guerrero Martos, Alejandro Millán 0001, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Enrique Ostúa, Julian Viejo |
Static Power Consumption in CMOS Gates Using Independent Bodies. |
PATMOS |
2007 |
DBLP DOI BibTeX RDF |
|
1 | Henrik Eriksson |
Dependability Evaluation of Time-Redundancy Techniques in Integer Multipliers. |
PATMOS |
2007 |
DBLP DOI BibTeX RDF |
|
1 | Michalis D. Galanis, Grigoris Dimitroulakos, Costas E. Goutis |
Performance Optimization of Embedded Applications in a Hybrid Reconfigurable Platform. |
PATMOS |
2007 |
DBLP DOI BibTeX RDF |
|
1 | Behnam Ghavami, Hossein Pedram |
An Automatic Design Flow for Implementation of Side Channel Attacks Resistant Crypto-Chips. |
PATMOS |
2007 |
DBLP DOI BibTeX RDF |
|
1 | Alin Razafindraibe, Philippe Maurine |
A Model of DPA Syndrome and Its Application to the Identification of Leaking Gates. |
PATMOS |
2007 |
DBLP DOI BibTeX RDF |
|
1 | Nicolas Fournel, Antoine Fraboulet, Paul Feautrier |
Fast and Accurate Embedded Systems Energy Characterization Using Non-intrusive Measurements. |
PATMOS |
2007 |
DBLP DOI BibTeX RDF |
|
1 | Prassanna Sithambaram, Alberto Macii, Enrico Macii |
New Adaptive Encoding Schemes for Switching Activity Balancing in On-Chip Buses. |
PATMOS |
2007 |
DBLP DOI BibTeX RDF |
|
1 | Miguel Peón Quirós, Alexandros Bartzas, Stylianos Mamagkakis, Francky Catthoor, Jose Manuel Mendias, Dimitrios Soudris |
Direct Memory Access Optimization in Wireless Terminals for Reduced Memory Latency and Energy Consumption. |
PATMOS |
2007 |
DBLP DOI BibTeX RDF |
|
1 | Oscar Gustafsson, Saeeid Tahmasbi Oskuii, Kenny Johansson, Per Gunnar Kjeldsberg |
Switching Activity Reduction of MAC-Based FIR Filters with Correlated Input Data. |
PATMOS |
2007 |
DBLP DOI BibTeX RDF |
dual bit type, coefficient reordering, MAC, FIR filter, switching activity |
1 | Naotake Kamiura, Teijiro Isokawa, Nobuyuki Matsui |
On Two-Pronged Power-Aware Voltage Scheduling for Multi-processor Real-Time Systems. |
PATMOS |
2007 |
DBLP DOI BibTeX RDF |
voltage scheduling, dependent tasks, energy saving, hard real-time system |
1 | Charalambos Basetas, Ioannis Kouretas, Vassilis Paliouras |
Low-Power Digital Filtering Based on the Logarithmic Number System. |
PATMOS |
2007 |
DBLP DOI BibTeX RDF |
|
1 | Andrea Pugliese 0002, Gregorio Cappuccino, Giuseppe Cocorullo |
Correct Modelling of Nested Miller Compensated Amplifier for Discrete-Time Applications. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Philippe Grosse, Yves Durand, Paul Feautrier |
Power Modeling of a NoC Based Design for High Speed Telecommunication Systems. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Gurhan Kucuk, Can Basaran |
Reducing Energy Dissipation of Wireless Sensor Processors Using Silent-Store-Filtering MoteCache. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
1 | David Elléouet, Yannig Savary, Nathalie Julien |
An FPGA Power Aware Design Flow. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Jong-Pil Son, Kyu-Young Kim, Ji-Yong Jeong, Yogendera Kumar, Soo-Won Kim |
New Battery Status Checking Method for Implantable Biomedical Applications. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Alin Razafindraibe, Michel Robert, Philippe Maurine |
Formal Evaluation of the Robustness of Dual-Rail Logic Against DPA Attacks. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Ka-Ming Keung, Akhilesh Tyagi |
SRAM CP: A Charge Recycling Design Schema for SRAM. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Tudor Murgan, Petru Bogdan Bacinschi, Alberto García Ortiz, Manfred Glesner |
Partial Bus-Invert Bus Encoding Schemes for Low-Power DSP Systems Considering Inter-wire Capacitance. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Abbas Sheibanyrad, Alain Greiner |
Two Efficient Synchronous Û Asynchronous Converters Well-Suited for Network on Chip in GALS Architectures. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Eslam Yahya, Marc Renaudin |
QDI Latches Characteristics and Asynchronous Linear-Pipeline Performance Analysis. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Theodoros Giannopoulos, Vassilis Paliouras |
Low-Power Maximum Magnitude Computation for PAPR Reduction in OFDM Transmitters. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Toshinori Sato, Yuu Tanaka, Hidenori Sato, Toshimasa Funaki, Takenori Koushiro, Akihiro Chiyonobu |
Improving Energy Efficiency Via Speculative Multithreading on MultiCore Processors. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Felipe Machado, Teresa Riesgo, Yago Torroja |
A Method for Switching Activity Analysis of VHDL-RTL Combinatorial Circuits. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
1 | José Luis Rosselló, Carol de Benito, Sebastià A. Bota, Jaume Segura 0001 |
Leakage Power Characterization Considering Process Variations. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Reouven Elbaz, Lionel Torres, Gilles Sassatelli, Pierre Guillemin, Michel Bardouillet, Albert Martinez |
A Comparison of Two Approaches Providing Data Encryption and Authentication on a Processor Memory Bus. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
1 | David Atienza, Praveen Raghavan, José L. Ayala, Giovanni De Micheli, Francky Catthoor, Diederik Verkest, Marisa López-Vallejo |
Compiler-Driven Leakage Energy Reduction in Banked Register Files. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Toshiro Akino, Takashi Hamahata |
A Clock Generator Driven by a Unified-CBiCMOS Buffer Driver for High Speed and Low Energy Operation. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Sriram Sambamurthy, Jacob A. Abraham, Raghuram S. Tupuri |
Delay Constrained Register Transfer Level Dynamic Power Estimation. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Xiao Yan Yu, Robert K. Montoye, Kevin J. Nowka, Bart R. Zeydel, Vojin G. Oklobdzija |
Circuit Design Style for Energy Efficiency: LSDL and Compound Domino. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Hai Lin, Yu Wang 0002, Rong Luo, Huazhong Yang, Hui Wang 0004 |
IR-drop Reduction Through Combinational Circuit Partitioning. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
Static Timing Analysis, IR-drop, circuit partitioning |
1 | Diganchal Chakraborty, P. P. Chakrabarti 0001, Arijit Mondal, Pallab Dasgupta |
A Framework for Estimating Peak Power in Gate-Level Circuits. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Masayuki Kitamura, Masaaki Iijima, Kenji Hamada, Masahiro Numa, Hiromi Notani, Akira Tada, Shigeto Maegawa |
High Performance CMOS Circuit by Using Charge Recycling Active Body-Bias Controlled SOI. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Christophe Giacomotto, Nikola Nedovic, Vojin G. Oklobdzija |
Energy-Delay Space Analysis for Clocked Storage Elements Under Process Variations. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Saihua Lin, Hongli Gao, Huazhong Yang |
Low Clock Swing D Flip-Flops Design by Using Output Control and MTCMOS. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Raúl Jiménez, Pilar Parra Fernández, Javier Castro-Ramirez, Manuel Sanchez-Raya, Antonio J. Acosta 0001 |
Optimization of Master-Slave Flip-Flops for High-Performance Applications. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Francesco Pessolano |
The Holy Grail of Holistic Low-Power Design. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Kostas Siozios, Dimitrios Soudris, Antonios Thanailakis |
Designing Alternative FPGA Implementations Using Spatial Data from Hardware Resources. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Jianping Hu, Hong Li, Yangbo Wu |
Low-Power Register File Based on Adiabatic Logic Circuits. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Clemens Schlachta, Manfred Glesner |
A CMOS Compatible Charge Recovery Logic Family for Low Supply Voltages. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Bart R. Zeydel, Vojin G. Oklobdzija |
Methodology for Energy-Efficient Digital Circuit Sizing: Important Issues and Design Limitations. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Massimo Alioto, Massimo Poli, Santina Rocchi, Valerio Vignoli |
Power Modeling of Precharged Address Bus and Application to Multi-bit DPA Attacks to DES Algorithm. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Preetham Lakshmikanthan, Adrian Nunez |
A Novel Methodology to Reduce Leakage Power in CMOS Complementary Circuits. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Régis Roubadia, Sami Ajram, Guy Cathébras |
Low Power and Low Jitter Wideband Clock Synthesizers in CMOS ASICs. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Christophe Alexandre, Marek Sroka, Hugo Clément, Christian Masson |
Zephyr: A Static Timing Analyzer Integrated in a Trans-hierarchical Refinement Design Flow. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Abel G. Silva-Filho, Filipe R. Cordeiro, Remy Eskinazi Sant'Anna, Manoel Eusébio de Lima |
Heuristic for Two-Level Cache Hierarchy Exploration Considering Energy Consumption and Performance. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Peter A. Beerel |
Asynchronous Design for High-Speed and Low-Power Circuits. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Mini Nanua, David T. Blaauw |
Receiver Modeling for Static Functional Crosstalk Analysis. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Yijun Liu, Steve B. Furber, Zhenkun Li |
The Design of a Dataflow Coprocessor for Low Power Embedded Hierarchical Processing. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
1 | José Carlos S. Palma, Leandro Soares Indrusiak, Fernando Gehm Moraes, Alberto García Ortiz, Manfred Glesner, Ricardo A. L. Reis |
Adaptive Coding in Networks-on-Chip: Transition Activity Reduction Versus Power Overhead of the Codec Circuitry. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Daniele Paolo Scarpazza, Praveen Raghavan, David Novo, Francky Catthoor, Diederik Verkest |
Software Simultaneous Multi-Threading, a Technique to Exploit Task-Level Parallelism to Improve Instruction- and Data-Level Parallelism. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Andrea Pugliese 0002, Gregorio Cappuccino, Giuseppe Cocorullo |
A Simple MOSFET Parasitic Capacitance Model and Its Application to Repeater Insertion Technique. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Christian Piguet, Christian Schuster, Jean-Luc Nagel |
Static and Dynamic Power Reduction by Architecture Selection. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
1 | V. Migairou, Robin Wilson, Sylvain Engels, Nadine Azémard, Philippe Maurine |
Statistical Characterization of Library Timing Performance. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Massimo Alioto, Massimo Poli, Santina Rocchi, Valerio Vignoli |
Techniques to Enhance the Resistance of Precharged Busses to Differential Power Analysis. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
1 | B. Chung, J. B. Kuo |
Gate-Level Dual-Threshold Static Power Optimization Methodology (GDSPOM) Using Path-Based Static Timing Analysis (STA) Technique. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Ajoy Kumar Palit, Kishore K. Duganapalli, Walter Anheier |
Modeling of Crosstalk Fault in Defective Interconnects. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
defect-based-crosstalk fault model, signal integrity losses, aggres-sor-victim, ABCD-model, crosstalk-hazards |
1 | Stefan Cserveny |
Low-Power Adaptive Bias Amplifier for a Large Supply-Range Linear Voltage Regulator. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Giovanni De Micheli |
Nanoelectronics: Challenges and Opportunities. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Domenik Helms, Marko Hoyer, Wolfgang Nebel |
Accurate PTV, State, and ABB Aware RTL Blackbox Modeling of Subthreshold, Gate, and PN-Junction Leakage. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Milena Vratonjic, Bart R. Zeydel, Vojin G. Oklobdzija |
Circuit Sizing and Supply-Voltage Selection for Low-Power Digital Circuit Design. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Jürgen Rauscher, Hans-Jörg Pfleiderer |
Sensitivity of a Power Supply Damping Method to Resistance and Current Waveform Variations. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Tiago Dias 0001, Nuno Roma, Leonel Sousa |
Low Power Distance Measurement Unit for Real-Time Hardware Motion Estimators. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Benjamin Nicolle, William Tatinian, Jean Oudinot, Gilles Jacquemod |
Hierarchical Modeling of a Fractional Phase Locked Loop. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Daniel Lima Ferrão, Ricardo Reis 0001, José Luís Almada Güntzel |
Considering Zero-Arrival Time and Block-Arrival Time in Hierarchical Functional Timing Analysis. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Johan Vounckx, Nadine Azémard, Philippe Maurine (eds.) |
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006, Proceedings |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Francois Thomas |
The Power Forward Initiative. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Saihua Lin, Huazhong Yang |
Worst Case Crosstalk Noise Effect Analysis in DSM Circuits by ABCD Modeling. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Robin Wilson |
Design for Volume Manufacturing in the Deep Submicron ERA. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Vasily G. Moshnyaga, Hoa Vo, Glenn Reinman, Miodrag Potkonjak |
Handheld System Energy Reduction by OS-Driven Refresh. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Alberto Macii, Enrico Macii, Massimo Poncino |
Dynamic Management of Thermally-Induced Clock Skew: An Implementation Perspective. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Guadalupe Miñana, José Ignacio Hidalgo, Oscar Garnica, Juan Lanchares, José Manuel Colmenar, Sonia López |
A Technique to Reduce Static and Dynamic Power of Functional Units in High-Performance Processors. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Davide Pandini, Guido A. Repetto |
Spectral Analysis of the On-Chip Waveforms to Generate Guidelines for EMC-Aware Design. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Hanene Ben Fradj, Cécile Belleudy, Michel Auguin |
System Level Multi-bank Main Memory Configuration for Energy Reduction. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
1 | M. Hillers, Wolfgang Nebel |
Impact of Array Data Flow Analysis on the Design of Energy-Efficient Circuits. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Ji-Yong Jeong, Gil-Su Kim, Jong-Pil Son, Woo-Jin Rim, Soo-Won Kim |
Body Bias Generator for Leakage Power Reduction of Low-Voltage Digital Logic Circuits. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Anatoly Prihozhy, Daniel Mlynek |
Design of Parallel Implementations by Means of Abstract Dynamic Critical Path Based Profiling of Complex Sequential Algorithms. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Julien Mercier, Christian Dufaza, Mathieu Lisart |
Methodology for Dynamic Power Verification of Contactless Smartcards. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Oguz Ergin |
Exploiting Narrow Values for Energy Efficiency in the Register Files of Superscalar Microprocessors. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Kenichi Okada, Takumi Uezono, Kazuya Masu |
Estimation of Power Reduction by On-Chip Transmission Line for 45nm Technology. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Wen-Tsan Hsieh, Chi-Chia Yu, Chien-Nan Jimmy Liu, Yi-Fang Chiu |
A Scalable Power Modeling Approach for Embedded Memory Using LIB Format. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Jean Oudinot |
Top Verification of Low Power System with "Checkerboard" Approach. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Didier Van Reeth, Georges G. E. Gielen |
A CAD Platform for Sensor Interfaces in Low-Power Applications. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Minas Dasygenis, Erik Brockmeyer, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis |
Improving the Memory Bandwidth Utilization Using Loop Transformations. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Mustafa Aktan, Günhan Dündar |
Design of Digital Filters for Low Power Applications Using Integer Quadratic Programming. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|