Search results for "VLSI-SoC"

Hits ?▲	Authors	Title	Venue	Year	Link
40	Yiorgos I. Bontzios, Michael G. Dimopoulos, Alkis A. Hatzopoulos	Prospects of 3D inductors on through silicon vias processes for 3D ICs.	VLSI-SoC	2011	DBLP DOI BibTeX RDF
40	Manas Kumar Puthal, Virendra Singh, Manoj Singh Gaur, Vijay Laxmi	C-Routing: An adaptive hierarchical NoC routing methodology.	VLSI-SoC	2011	DBLP DOI BibTeX RDF
40	Zhiliang Qian, Ying Fei Teh, Chi-Ying Tsui	A fault-tolerant network-on-chip design using dynamic reconfiguration of partial-faulty routing resources.	VLSI-SoC	2011	DBLP DOI BibTeX RDF
40	Ying Fei Teh, Zhiliang Qian, Chi-Ying Tsui	A fault-tolerant NoC using combined link sharing and partial fault link utilization scheme.	VLSI-SoC	2011	DBLP DOI BibTeX RDF
40	Pascal Vivet, Denis Dutoit, Yvain Thonnart, Fabien Clermidy	3D NoC using through silicon Via: An asynchronous implementation.	VLSI-SoC	2011	DBLP DOI BibTeX RDF
40	Xiaojin Zhao, Amine Bermak, Farid Boussaïd	A low cost CMOS polarimetric ophthalmoscope scheme for cerebral malaria diagnostics.	VLSI-SoC	2011	DBLP DOI BibTeX RDF
40	Wei Jin 0004, Sheng Lu, Weifeng He, Zhigang Mao	A 230mV 8-bit sub-threshold microprocessor for wireless sensor network.	VLSI-SoC	2011	DBLP DOI BibTeX RDF
40	Jizeng Wei, Yisong Chang, Wei Guo 0005, Jizhou Sun	An optimized TTA-like vertex shader datapath for embedded 3D graphics processing unit.	VLSI-SoC	2011	DBLP DOI BibTeX RDF
40	Joseph Sankman, Dongsheng Ma 0001	A subthreshold digital maximum power point tracker for micropower piezoelectric energy harvesting applications.	VLSI-SoC	2011	DBLP DOI BibTeX RDF
40	Wenmin Hu, Zhonghai Lu, Axel Jantsch, Hengzhu Liu, Botao Zhang, Dongpei Liu	Network-on-Chip multicasting with low latency path setup.	VLSI-SoC	2011	DBLP DOI BibTeX RDF
40	Kai-Pui Lam, Terrence S. T. Mak, Chi-Sang Poon	Comparative ODE benchmarking of unidirectional and bidirectional DP networks for 3D-IC.	VLSI-SoC	2011	DBLP DOI BibTeX RDF
40	Haotian Liu, Fengrui Shi, Yuanzhe Wang, Ngai Wong	Frequency-domain transient analysis of multitime partial differential equation systems.	VLSI-SoC	2011	DBLP DOI BibTeX RDF
40	Sébastien Le Beux, Jelena Trajkovic, Ian O'Connor, Gabriela Nicolescu	Layout guidelines for 3D architectures including Optical Ring Network-on-Chip (ORNoC).	VLSI-SoC	2011	DBLP DOI BibTeX RDF
40	Yang Chai, Minghui Sun, Zhiyong Xiao, Yuan Li, Min Zhang 0041, Philip C. H. Chan	Towards future VLSI interconnects using aligned carbon nanotubes.	VLSI-SoC	2011	DBLP DOI BibTeX RDF
40	Marcel Veloso Campos, André Luís Fortunato, Carlos Alberto dos Reis Filho	New 12-bit source-follower track-and-hold circuit suitable for high-speed applications.	VLSI-SoC	2011	DBLP DOI BibTeX RDF
40	Wing-Hung Ki, Yan Lu 0002, Feng Su, Chi-Ying Tsui	Design and analysis of on-chip charge pumps for micro-power energy harvesting applications.	VLSI-SoC	2011	DBLP DOI BibTeX RDF
40	Masahiro Iida, Kazuki Inoue, Motoki Amagasaki, Toshinori Sueyoshi	An easily testable routing architecture of FPGA.	VLSI-SoC	2011	DBLP DOI BibTeX RDF
40	Jamshaid Sarwar Malik, Jameel Nawaz Malik, Ahmed Hemani, Nasirud Din Gohar	Generating high tail accuracy Gaussian Random Numbers in hardware using central limit theorem.	VLSI-SoC	2011	DBLP DOI BibTeX RDF
40	Pramod Kumar Meher, Yu Pan	MCM-based implementation of block FIR filters for high-speed and low-power applications.	VLSI-SoC	2011	DBLP DOI BibTeX RDF
40		VLSI-SoC: Advanced Topics on Systems on a Chip - A Selection of Extended Versions of the Best Papers of the Fourteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC2007), October 15-17, 2007, Atlanta, USA	VLSI-SoC (Selected Papers)	2009	DBLP DOI BibTeX RDF
40	Cyrus Bazeghi, Francisco J. Mesa-Martinez, Jose Renau	System and Procesor Design Effort Estimation.	VLSI-SoC (Selected Papers)	2007	DBLP DOI BibTeX RDF
40	Sameer Sharma, L. G. Johnson	First Order, Quasi-Static, SOI Charge Conserving Power Dissipation Model.	VLSI-SoC (Selected Papers)	2007	DBLP DOI BibTeX RDF
40	Robert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, Rolf Drechsler	SWORD: A SAT like Prover Using Word Level Information.	VLSI-SoC (Selected Papers)	2007	DBLP DOI BibTeX RDF
40	Julien Goulier, Eric André, Marc Renaudin	A new analytical approach of the impact of jitter on continuous time delta sigma converters.	VLSI-SoC (Selected Papers)	2007	DBLP DOI BibTeX RDF
40	Marco Paolieri, Ivano Bonesana, Marco D. Santambrogio	ReCPU: a Parallel and Pipelined Architecture for Regular Expression Matching.	VLSI-SoC (Selected Papers)	2007	DBLP DOI BibTeX RDF
40	Vincenzo Rana, Chiara Sandionigi, Marco D. Santambrogio, Donatella Sciuto	An adaptive genetic algorithm for dynamically reconfigurable modules allocation.	VLSI-SoC (Selected Papers)	2007	DBLP DOI BibTeX RDF
40	Julien Dalmasso, Marie-Lise Flottes, Bruno Rouzeyre	Compression-based SoC Test Infrastructures.	VLSI-SoC (Selected Papers)	2007	DBLP DOI BibTeX RDF
40	Antonio Carlos Schneider Beck, Luigi Carro	Reconfigurable Acceleration with Binary Compatibility for General Purpose Processors.	VLSI-SoC (Selected Papers)	2007	DBLP DOI BibTeX RDF
40	Jorge Fernandez Villena, Wil H. A. Schilders, L. Miguel Silveira	Parametric Structure-Preserving Model Order Reduction.	VLSI-SoC (Selected Papers)	2007	DBLP DOI BibTeX RDF
40	Aline Mello 0001, Ney Calazans, Fernando Moraes 0001	QoS in Networks-on-Chip - Beyond Priority and Circuit Switching Techniques.	VLSI-SoC (Selected Papers)	2007	DBLP DOI BibTeX RDF
40	Sheng-Yu Peng, Paul E. Hasler, David V. Anderson	A Programmable Multi-Dimensional Analog Radial-Basis- Function-Based Classifier.	VLSI-SoC (Selected Papers)	2007	DBLP DOI BibTeX RDF
40	Bassam Jamil Mohd, Earl E. Swartzlander Jr., Adnan Aziz	The Hazard-Free Superscalar Pipeline Fast Fourier Transform Architecture and Algorithm.	VLSI-SoC (Selected Papers)	2007	DBLP DOI BibTeX RDF
40	Osnat Keren, Ilya Levin, Radomir S. Stankovic	Use of Gray Decoding for Implementation of Symmetric Functions.	VLSI-SoC (Selected Papers)	2007	DBLP DOI BibTeX RDF
40	Almitra Pradhan, Ranga Vemuri	Accurate Performance Estimation using Circuit Matrix Models in Analog Circuit Synthesis.	VLSI-SoC (Selected Papers)	2007	DBLP DOI BibTeX RDF
40	Lucas Brusamarello, Roberto da Silva, Gilson I. Wirth, Ricardo Reis 0001	Statistical and Numerical Approach for a Computer efficient circuit yield analysis.	VLSI-SoC (Selected Papers)	2007	DBLP DOI BibTeX RDF
40	Gustavo Neuberger, Gilson I. Wirth, Fernanda Gusmão de Lima Kastensmidt, Ricardo Reis 0001	Statistical Analysis of Normality of Systematic and Random Variability of Flip-Flop Race Immunity in 130nm and 90nm CMOS Technologies.	VLSI-SoC (Selected Papers)	2007	DBLP DOI BibTeX RDF
32		31st IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2023, Dubai, United Arab Emirates, October 16-18, 2023	VLSI-SoC	2023	DBLP DOI BibTeX RDF
32	Kais Belwafi, Hamdan Alshamsi, Ashfaq Ahmed, Abdulhadi Shoufan	Zero-Trust Communication between Chips.	VLSI-SoC	2023	DBLP DOI BibTeX RDF
32	Shahid Jamil, Muhammad Usman, Muhammad Jawad Shakil, Jafar Hussain, Rashad Ramzan	Bi-Directional Time Domain Duplexing (TDD) Amplifier for 5G Applications.	VLSI-SoC	2023	DBLP DOI BibTeX RDF
32	Hanning Chen, Yeseong Kim, Elaheh Sadredini, Saransh Gupta, Hugo Latapie, Mohsen Imani	Sparsity Controllable Hyperdimensional Computing for Genome Sequence Matching Acceleration.	VLSI-SoC	2023	DBLP DOI BibTeX RDF
32	Imlijungla Longchar, Hemangee K. Kapoor	ADaMaT: Towards an Adaptive Dataflow for Maximising Throughput in Neural Network Inference.	VLSI-SoC	2023	DBLP DOI BibTeX RDF
32	Omar Numan, Martin Andraud, Kari Halonen	A Self-Calibrated Activation Neuron Topology for Efficient Resistive-Based In-Memory Computing.	VLSI-SoC	2023	DBLP DOI BibTeX RDF
32	Jean-Philippe Noël, E. Valea, Laurent Grenouillet, B. Chapuis, C. Fisher, A. Recoquillay, Bastien Giraud	Compute-In-Place Serial FeRAM: Enhancing Performance, Efficiency and Adaptability in Critical Embedded Systems.	VLSI-SoC	2023	DBLP DOI BibTeX RDF
32	Rebecca Pelke, Nils Bosbach, José Cubero-Cascante, Felix Staudigl, Rainer Leupers, Jan Moritz Joseph	Mapping of CNNs on multi-core RRAM-based CIM architectures.	VLSI-SoC	2023	DBLP DOI BibTeX RDF
32	Can Ayduman, Emre Koçer, Selim Kirbiyik, Ahmet Can Mert, Erkay Savas	Efficient Design-Time Flexible Hardware Architecture for Accelerating Homomorphic Encryption.	VLSI-SoC	2023	DBLP DOI BibTeX RDF
32	Shan-Hui Chou, Ting-Yun Hsiao, Jing-Yang Jou, Juinn-Dar Huang	An Evaluation and Architecture Exploration Engine for CNN Accelerators through Extensive Dataflow Analysis.	VLSI-SoC	2023	DBLP DOI BibTeX RDF
32	Siyi Wang, Anupam Chattopadhyay	Reducing Depth of Quantum Adder using Ling Structure.	VLSI-SoC	2023	DBLP DOI BibTeX RDF
32	Deepraj Soni, Mohammed Nabeel 0001, Ramesh Karri, Michail Maniatakos	Optimizing Constrained-Modulus Barrett Multiplier for Power and Flexibility.	VLSI-SoC	2023	DBLP DOI BibTeX RDF
32	Ankit Sirohi, Jawar Singh	A Steep Slope Sub-10nm Armchair Phosphorene Nanoribbon FET with Intrinsic Cold Contact.	VLSI-SoC	2023	DBLP DOI BibTeX RDF
32	Aishwarya Gupta, N. S. Aswathy, Hemangee K. Kapoor	Look before you leap: An Access-based Prudent Page Migration for Hybrid Memories.	VLSI-SoC	2023	DBLP DOI BibTeX RDF
32	Anjum Riaz, Gaurav Kumar, Pardeep Kumar, Yamuna Prasad, Satyadev Ahlawat	On Protecting IJTAG using an Inherently Secure SIB.	VLSI-SoC	2023	DBLP DOI BibTeX RDF
32	Dheemanth Joshi, Aniket Arun Gangotri, Sai Pranay Chennamsetti, Gautham Bolar, Ganesan Thiagarajan, Sanjeev Gurugopinath	A Two-Layer Connected Component Algorithm for Target Extraction Using K-means and Morphology.	VLSI-SoC	2023	DBLP DOI BibTeX RDF
32	Gabriel Rutsch, Konrad Maier, Wolfgang Ecker	FPGA-implementation techniques to efficiently test application readiness of mixed-signal products.	VLSI-SoC	2023	DBLP DOI BibTeX RDF
32	Lennart M. Reimann, Jonathan Wiesner, Dominik Sisejkovic, Farhad Merchant, Rainer Leupers	SoftFlow: Automated HW-SW Confidentiality Verification for Embedded Processors.	VLSI-SoC	2023	DBLP DOI BibTeX RDF
32	Paolo Bernardi, Giorgio Insinga, Nima Kolahimahmoudi	A Novel Approach to Extract Embedded Memory Design Parameter Through Irradiation Test.	VLSI-SoC	2023	DBLP DOI BibTeX RDF
32	Walaa Amer, Mariam Rakka, Rachid Karami, Minjun Seo, Mazen A. R. Saghir, Rouwaida Kanj, Fadi J. Kurdahi	Hardware Implementation and Evaluation of an Information Processing Factory.	VLSI-SoC	2023	DBLP DOI BibTeX RDF
32	Sejin Lim, Hyunjun Kim, Kyungbae Jang, Siyi Wang, Anubhab Baksi, Anupam Chattopadhyay, Hwajeong Seo	Optimized Quantum Circuit Implementation of Payoff Function.	VLSI-SoC	2023	DBLP DOI BibTeX RDF
32	Sagheer Ahmed, Jayesh Ambulkar, Debabrata Mondal, Ambika Prasad Shah	Soft Error Immune with Enhanced Critical Charge SIC14T SRAM Cell for Avionics Applications.	VLSI-SoC	2023	DBLP DOI BibTeX RDF
32	Rafael Medina, Darong Huang, Giovanni Ansaloni, Marina Zapater, David Atienza	REMOTE: Re-thinking Task Mapping on Wireless 2.5D Systems-on-Package for Hotspot Removal.	VLSI-SoC	2023	DBLP DOI BibTeX RDF
32	Shayesteh Masoumian, Roel Maes, Rui Wang, Karthik Keni Yerriswamy, Geert Jan Schrijen, Said Hamdioui, Mottaqiallah Taouil	Modeling and Analysis of SRAM PUF Bias Patterns in 14nm and 7nm FinFET Technology Nodes.	VLSI-SoC	2023	DBLP DOI BibTeX RDF
32	Klajd Zyla, Marco Liess, Thomas Wild, Andreas Herkersdorf	FlexPipe: Fast, Flexible and Scalable Packet Processing for High-Performance SmartNICs.	VLSI-SoC	2023	DBLP DOI BibTeX RDF
32	Hala Ibrahim, Haytham Azmi, M. Watheq El-Kharashi, Mona Safar	Hardware Security Analysis of Arbiters: Trojan Modeling and Formal Verification.	VLSI-SoC	2023	DBLP DOI BibTeX RDF
32	Yi Chen, Jie Lou, Christian Lanius, Florian Freye, Johnson Loh, Tobias Gemmeke	An Energy-Efficient and Area-Efficient Depthwise Separable Convolution Accelerator with Minimal On-Chip Memory Access.	VLSI-SoC	2023	DBLP DOI BibTeX RDF
32	Umair F. Siddiqi, Gary William Grewal, Shawki Areibi	A Deterministic Parallel Routing Approach for Accelerating Pathfinder-based Algorithms.	VLSI-SoC	2023	DBLP DOI BibTeX RDF
32	Hassen Aziza, Cristian Zambelli, Said Hamdioui, Sumit Diware, Rajendra Bishnoi, Anteneh Gebregiorgis	On the Reliability of RRAM-Based Neural Networks.	VLSI-SoC	2023	DBLP DOI BibTeX RDF
32	Giovani Britton, Salvador Mir, Estelle Lauga-Larroze, Benjamin Dormieu, Quentin Berlingard, Mikaël Cassé, Philippe Galy	Noise modeling using look-up tables and DC measurements for cryogenic applications.	VLSI-SoC	2023	DBLP DOI BibTeX RDF
32	Yiyang Yu, Atif Shamim	Gain Enhancement of Antenna-on-Chip at 94 GHz with an Integrated Artificial Magnetic Conductor for 6G System-on-Chip.	VLSI-SoC	2023	DBLP DOI BibTeX RDF
32	Suman Deb, Anupam Chattopadhyay, Avi Mendelson	A RISC-V SoC with Hardware Trojans: Case Study on Trojan-ing the On-Chip Protocol Conversion.	VLSI-SoC	2023	DBLP DOI BibTeX RDF
32	Robert Limas Sierra, Juan-David Guerrero-Balaguera, Josie E. Rodriguez Condia, Matteo Sonza Reorda	Analyzing the Impact of Different Real Number Formats on the Structural Reliability of TCUs in GPUs.	VLSI-SoC	2023	DBLP DOI BibTeX RDF
32	Esha Sarkar, Constantine Doumanidis, Michail Maniatakos	TRAPDOOR: Repurposing neural network backdoors to detect dataset bias in machine learning-based genomic analysis.	VLSI-SoC	2023	DBLP DOI BibTeX RDF
32	Cristiano Merio, Xavier Lesage, Ali Naimi, Sylvain Engels, Katell Morin-Allory, Laurent Fesquet	Method for Data-Driven Pruning in Micropipeline Circuits.	VLSI-SoC	2023	DBLP DOI BibTeX RDF
32	Cédric Marchand 0002, Alban Nicolas, Paul-Antoine Matrangolo, David Navarro, Alberto Bosio, Ian O'Connor	FeFET based Logic-in-Memory design methodologies, tools and open challenges.	VLSI-SoC	2023	DBLP DOI BibTeX RDF
32	Chun-Jen Tsai, Chun Wei Chao, Sheng-Di Hong	Integrated Dynamic Memory Manager for a RISC-V Processor.	VLSI-SoC	2023	DBLP DOI BibTeX RDF
32	Junjie Li, Youming Zhang, Yunqi Cao, Xusheng Tang, Fengyi Huang	A Unity Feedback Length-Extend Delta-Sigma Modulator for Fractional-N Frequency Synthesizer.	VLSI-SoC	2023	DBLP DOI BibTeX RDF
32	Safiullah Khan, Ayesha Khalid, Ciara Rafferty, Yasir Ali Shah, Máire O'Neill, Wai-Kong Lee, Seong Oun Hwang	Efficient, Error-Resistant NTT Architectures for CRYSTALS-Kyber FPGA Accelerators.	VLSI-SoC	2023	DBLP DOI BibTeX RDF
32	Mouli Venkata Prakash Pittala, Aditya Kalyani, Nagaveni S	Reconfigurable Rectifier for RF Energy Harvesting System at WiFi-6 Frequency Band for 2.5 V.	VLSI-SoC	2023	DBLP DOI BibTeX RDF
32	Shubham Kumar, Paul R. Genssler, Somaya Mansour, Yogesh Singh Chauhan, Hussam Amrouch	Frontiers in AI Acceleration: From Approximate Computing to FeFET Monolithic 3D Integration.	VLSI-SoC	2023	DBLP DOI BibTeX RDF
32	Jingbo Jiang, Xizi Chen, Chi-Ying Tsui	Accelerating Large Kernel Convolutions with Nested Winograd Transformation.	VLSI-SoC	2023	DBLP DOI BibTeX RDF
32	Rassul Bairamkulov, Alessandro Tempia Calvino, Giovanni De Micheli	Synthesis of SFQ Circuits with Compound Gates.	VLSI-SoC	2023	DBLP DOI BibTeX RDF
32	Gokulnath Rajendran, Furqan Zahoor, Simranjeet Singh, Farhad Merchant, Vikas Rana, Anupam Chattopadhyay	PR-PUF: A Reconfigurable Strong RRAM PUF.	VLSI-SoC	2023	DBLP DOI BibTeX RDF
32	Rupesh Raj Karn, Kashif Nawaz, Ibrahim Abe M. Elfadel	Post-Quantum, Order-Preserving Encryption for the Confidential Inference in Decision Trees: FPGA Design and Implementation.	VLSI-SoC	2023	DBLP DOI BibTeX RDF
32	Grégoire Eggermann, Marco Rios, Giovanni Ansaloni, Sani R. Nassif, David Atienza	A 16-bit Floating-Point Near-SRAM Architecture for Low-power Sparse Matrix-Vector Multiplication.	VLSI-SoC	2023	DBLP DOI BibTeX RDF
32	Muhammad Jawad Shakil, Uzair Ahmed, Jafar Hussain, Hassan Saif, Rashad Ramzan	A Bondwire Inductor Based Flash ADC Assisted DC-DC Buck Converter.	VLSI-SoC	2023	DBLP DOI BibTeX RDF
32	Foroozan Karimzadeh, Mohsen Imani, Bahar Asgari, Ningyuan Cao, Yingyan Lin, Yan Fang	Memory-Based Computing for Energy-Efficient AI: Grand Challenges.	VLSI-SoC	2023	DBLP DOI BibTeX RDF
32	Solomon Michael Serunjogi, Mihai Sanduleanu	3.125GS/s, 4.9 ENOB, 109 fJ/Conversion Time-Domain ADC for Backplane Interconnect.	VLSI-SoC	2023	DBLP DOI BibTeX RDF
32	Hossein Taji, Jose Miranda, Miguel Peón Quirós, Szabolcs Balási, David Atienza	Dynamic Scheduling for Event-Driven Embedded Industrial Applications.	VLSI-SoC	2023	DBLP DOI BibTeX RDF
32	Ziyang Ye, Makoto Ikeda	Dynamic Digital Circuit Locking (DDCL): A Shield against Static Analysis Attacks.	VLSI-SoC	2023	DBLP DOI BibTeX RDF
32	A. Datsuk, P. Ostrovskyy, F. Vater, C. Wieden	Towards Robust Process Design Kits with a Scalable DevOps Quality Assurance Platform.	VLSI-SoC	2023	DBLP DOI BibTeX RDF
32		30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	C. del Río Bueno, U. Esteban Eraso, Carlos Sánchez-Azqueta, Santiago Celma	A 18-27 GHz Programmable Gain Amplifier in 65-nm CMOS technology.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Halil Kükner, Gökhan Kaplayan, Ahmet Efe, Mehmet Ali Gülden	RISC-V Processor Trace Encoder with Multiple Instructions Retirement Support.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Foroozan Karimzadeh, Arijit Raychowdhury	Towards Energy Efficient DNN accelerator via Sparsified Gradual Knowledge Distillation.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Lucas Réveil, Chhandak Mukherjee, Cristell Maneux, Marina Deng, François Marc, Abhishek Kumar, Aurélie Lecestre, Guilhem Larrieu, Arnaud Poittevin, Ian O'Connor, Oskar Baumgartner, David Pirker	Analysis of an Inverter Logic Cell based on 3D Vertical NanoWire Junction-Less Transistors.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Vasileios Leon, Kiamal Z. Pekmestzi, Dimitrios Soudris	Systematic Embedded Development and Implementation Techniques on Intel Myriad VPUs.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Cecil Accetti, Peilin Liu	Architectural Support for Functional Programming.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Milad Eslaminia, Sébastien Le Beux	Toward Large Scale All-Optical Spiking Neural Networks.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Nils Bosbach, Jan Moritz Joseph, Rainer Leupers, Lukas Jünger 0001	NISTT: A Non-Intrusive SystemC-TLM 2.0 Tracing Tool.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Mohammad Humam Khan, Ruchika Gupta, Vedika J. Kulkarni, John Jose, Sukumar Nandi	Hardware Trojan Mitigation for Securing On-chip Networks from Dead Flit Attacks.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Endri Kaja, Nicolas Gerlin, Monideep Bora, Gabriel Rutsch, Keerthikumara Devarajegowda, Dominik Stoffel, Wolfgang Kunz, Wolfgang Ecker	Fast and Accurate Model-Driven FPGA-based System-Level Fault Emulation.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Foroozan Karimzadeh, Arijit Raychowdhury	Towards CIM-friendly and Energy-Efficient DNN Accelerator via Bit-level Sparsity.	VLSI-SoC	2022	DBLP DOI BibTeX RDF