Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
17 | Thomas Schilling, Magnus Själander, Per Larsson-Edefors |
Scheduling for an Embedded Architecture with a Flexible Datapath. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2009, 13-15 May 2009, Tampa, Florida, USA, pp. 151-156, 2009, IEEE Computer Society, 978-0-7695-3684-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
17 | Johann Großschädl, Erkay Savas, Kazim Yumbul |
Realizing Arbitrary-Precision Modular Multiplication with a Fixed-Precision Multiplier Datapath. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ReConFig ![In: ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, Cancun, Quintana Roo, Mexico, 9-11 December 2009, Proceedings, pp. 261-266, 2009, IEEE Computer Society, 978-0-7695-3917-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Bit-serial multiplier architecture, Scalability, Montgomery modular multiplication |
17 | Reto Zimmermann |
Datapath Synthesis for Standard-Cell Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 19th IEEE Symposium on Computer Arithmetic, ARITH 2009, Portland, Oregon, USA, 9-10 June 2009, pp. 207-211, 2009, IEEE Computer Society, 978-0-7695-3670-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
17 | Martin Langhammer, Tom VanCourt |
FPGA Floating Point Datapath Compiler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: FCCM 2009, 17th IEEE Symposium on Field Programmable Custom Computing Machines, Napa, California, USA, 5-7 April 2009, Proceedings, pp. 259-262, 2009, IEEE Computer Society, 978-0-7695-3716-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
performance computing, optimization, FPGA, floating point |
17 | Bijan Alizadeh, Masahiro Fujita |
Improved heuristics for finite word-length polynomial datapath optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2009 International Conference on Computer-Aided Design, ICCAD 2009, San Jose, CA, USA, November 2-5, 2009, pp. 739-744, 2009, ACM, 978-1-60558-800-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
17 | Bo Marr, Brian P. Degnan, Paul E. Hasler, David V. Anderson |
An Asynchronously Embedded Datapath for Performance Acceleration and Energy Efficiency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2009), 24-17 May 2009, Taipei, Taiwan, pp. 3046-3049, 2009, IEEE, 978-1-4244-3827-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
17 | Saeed Fouladi Fard, Amirhossein Alimohammad, Bruce F. Cockburn, Christian Schlegel |
High path-count multirate Rayleigh fading channel simulator with time-multiplexed datapath. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: Annual IEEE International SoC Conference, SoCC 2009, September 9-11, 2009, Belfast, Northern Ireland, UK, Proceedings, pp. 412-415, 2009, IEEE, 978-1-4244-4940-8. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
17 | Sotirios Xydis, Ioannis Triantafyllou, George Economakos, Kiamal Z. Pekmestzi |
Flexible Datapath Synthesis through Arithmetically Optimized Operation Chaining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AHS ![In: NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2009, San Francisco, California, USA, July 29 - August 1, 2009, pp. 407-414, 2009, IEEE Computer Society, 978-0-7695-3714-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
17 | Sohan Purohit, Marco Lanuzza, Stefania Perri, Pasquale Corsonello, Martin Margala |
Design-Space Exploration of Energy-Delay-Area Efficient Coarse-Grain Reconfigurable Datapath. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2009: Improving Productivity through Higher Abstraction, The 22nd International Conference on VLSI Design, New Delhi, India, 5-9 January 2009, pp. 45-50, 2009, IEEE Computer Society, 978-0-7695-3506-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
17 | Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki |
Novel Register Sharing in Datapath for Structural Robustness against Delay Variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(4), pp. 1044-1053, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Takayuki Obata, Mineo Kaneko |
Simultaneous Optimization of Skew and Control Step Assignments in RT-Datapath Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(12), pp. 3585-3595, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Shubhajit Roy Chowdhury, Dipankar Chakrabarti, Hiranmay Saha |
FPGA realization of a smart processing system for clinical diagnostic applications using pipelined datapath architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 32(2), pp. 107-120, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Doochul Shin, Sandeep K. Gupta 0001 |
A Re-design Technique for Datapath Modules in Error Tolerant Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ATS ![In: 17th IEEE Asian Test Symposium, ATS 2008, Sapporo, Japan, November 24-27, 2008, pp. 431-437, 2008, IEEE Computer Society, 978-0-7695-3396-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Martin Langhammer |
High performance matrix multiply using fused datapath operators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSCC ![In: 42nd Asilomar Conference on Signals, Systems and Computers, ACSSC 2008, Pacific Grove, CA, USA, October 26-29, 2008, pp. 153-159, 2008, IEEE, 978-1-4244-2940-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Kieron Turkington, George A. Constantinides, Peter Y. K. Cheung, Konstantinos Masselos |
Co-optimisation of datapath and memory in outer loop pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPT ![In: 2008 International Conference on Field-Programmable Technology, FPT 2008, Taipei, Taiwan, December 7-10, 2008, pp. 1-8, 2008, IEEE, 978-1-4244-2796-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Takayuki Obata, Mineo Kaneko |
Concurrent skew and control step assignments in RT-level datapath synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 2018-2021, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Shal Vishal |
Synthesis of dual-rail datapath circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2008 |
RDF |
|
17 | Zoran Salcic, George G. Coghill, R. Bruce Maunder |
A genetic algorithm high-level optimizer for complex datapath and data-flow digital systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Appl. Soft Comput. ![In: Appl. Soft Comput. 7(3), pp. 979-994, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Antonio M. Lopez Jr., Frederick G. Lopez, Robert W. Lent, Madonna G. Constantine |
Multidisciplinary research on the datapath of the computing disciplines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Commun. ACM ![In: Commun. ACM 50(12), pp. 46-50, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Justin Davis, Robert B. Reese |
Finite State Machine Datapath Design, Optimization, and Implementation ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2007 |
DOI RDF |
|
17 | Makoto Ikeda, Ken Ishii, Taku Sogabe, Kunihiro Asada |
Datapath Delay Distributions for Data/Instruction against PVT Variations in 90nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 14th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2007, Marrakech, Morocco, December 11-14, 2007, pp. 154-157, 2007, IEEE, 978-1-4244-1377-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Arash Ahmadi, Mark Zwolinski |
Multiple-Width Bus Partitioning Approach to Datapath Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 2994-2997, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Simone Medardoni, Davide Bertozzi, Luca Benini, Enrico Macii |
Control and datapath decoupling in the design of a NoC switch: area, power and performance implications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoC ![In: International Symposium on System-on-Chip, SoC 2007, Tampere, Finland, November 20-21, 2007, pp. 1-4, 2007, IEEE, 978-1-4244-1368-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Nagaraju Pothineni, Anshul Kumar, Kolin Paul |
Application Specific Datapath Extension with Distributed I/O Functional Units. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India, pp. 551-558, 2007, IEEE Computer Society, 0-7695-2762-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Saraju P. Mohanty, Ramakrishna Velagapudi, Elias Kougianos |
Physical-aware simulated annealing optimization of gate leakage in nanoscale datapath circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 1191-1196, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Mazen A. R. Saghir, Mohamad El-Majzoub, Patrick Akl |
Datapath and ISA Customization for Soft VLIW Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ReConFig ![In: 2006 IEEE International Conference on Reconfigurable Computing and FPGA's, ReConFig 2006, San Luis Potosi, Mexico, September 20-22, 2006, pp. 280-289, 2006, IEEE Computer Society, 1-4244-0690-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
17 | John Lofgren, Josefina Hobbs, John McCardle |
PSeuDoFFIL: Power Saving Datapath FiFo Insertion Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CGVR ![In: Proceedings of the 2006 International Conference on Computer Graphics & Virtual Reality, CGVR 2006, Las Vegas, Nevada, USA, June 26-29, 2006, pp. 65-71, 2006, CSREA Press, 1-932415-85-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP BibTeX RDF |
|
17 | Saraju P. Mohanty, Elias Kougianos, Ramakrishna Velagapudi, Valmiki Mukherjee |
Scheduling and binding for low gate leakage nanoCMOS datapath circuit synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Cid C. de Souza, André M. Lima, Guido Araujo, Nahri Moreano |
The datapath merging problem in reconfigurable systems: Complexity, dual bounds and heuristic evaluation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Exp. Algorithmics ![In: ACM J. Exp. Algorithmics 10, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Data path merging, heuristics, lower bounds, reconfigurable systems |
17 | Mile K. Stojcev |
Digital Computer Arithmetic Datapath Design Using Verilog HDL, James E. Stine, Kluwer Academic Publishers, Boston, 2004, ISBN 1-4020-7710-6. Hardcover, pp 180, plus XI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 45(7-8), pp. 1272, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Saraju P. Mohanty, Nagarajan Ranga Ranganathan |
Simultaneous peak and average power minimization during datapath scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 52-I(6), pp. 1157-1165, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Eckhard Grass, Frank Winkler 0001, Milos Krstic, Alexandra Julius, Christian Stahl, Maxim Piz |
Enhanced GALS Techniques for Datapath Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation, 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005, Proceedings, pp. 581-590, 2005, Springer, 3-540-29013-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Ali Manzak |
Temperature Aware Datapath Scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation, 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005, Proceedings, pp. 99-106, 2005, Springer, 3-540-29013-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Konstantinos Katsoulakis, Tughrul Arslan, Tony Kirkham, Sami Khawam |
A Low-Power Reconfigurable Datapath for Advanced Speech Coding Algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), CD-ROM / Abstracts Proceedings, 4-8 April 2005, Denver, CO, USA, 2005, IEEE Computer Society, 0-7695-2312-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Yee William Li, George Patounakis, Kenneth L. Shepard, Steven M. Nowick |
High-throughput asynchronous datapath with software-controlled voltage scaling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 39(4), pp. 704-708, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Nemanja Isailovic, Mark Whitney, Yatish Patel, John Kubiatowicz, Dean Copsey, Frederic T. Chong, Isaac L. Chuang, Mark Oskin |
Datapath and control for quantum wires. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 1(1), pp. 34-61, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Architecture, Control, Layout |
17 | Bob Moore, David Durham, John Strassner, Andrea Westerinen, Walter Weiss |
Information Model for Describing Network Device QoS Datapath Mechanisms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RFC ![In: RFC 3670, pp. 1-97, January 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Sumeet Kumar, Prateek Pujara, Aneesh Aggarwal |
Bit-Sliced Datapath for Energy-Efficient High Performance Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACS ![In: Power-Aware Computer Systems, 4th International Workshop, PACS 2004, Portland, OR, USA, December 5, 2004, Revised Selected Papers, pp. 30-45, 2004, Springer, 3-540-29790-1. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Ingmar Neumann, Dominik Stoffel, Kolja Sulimma, Michel R. C. M. Berkelaar, Wolfgang Kunz |
Layout Driven Optimization of Datapath Circuits using Arithmetic Reasoning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Kaiserslautern, Germany, February 24-25, 2004, pp. 24-33, 2004, Shaker. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP BibTeX RDF |
|
17 | Andy Gean Ye, Jonathan Rose |
Using multi-bit logic blocks and automated packing to improve field-programmable gate array density for implementing datapath circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPT ![In: Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, Brisbane, Australia, December 6-8, 2004, pp. 129-136, 2004, IEEE. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Hongtu Jiang, Viktor Öwall |
FPGA implementation of controller-datapath pair in custom image processor design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2004 International Symposium on Circuits and Systems, ISCAS 2004, Vancouver, BC, Canada, May 23-26, 2004, pp. 141-144, 2004, IEEE, 0-7803-8251-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP BibTeX RDF |
|
17 | Masanori Hashimoto, Yoshiteru Hayashi, Hidetoshi Onodera |
Experimental Study on Cell-Base High-Performance Datapath Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(12), pp. 3204-3207, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP BibTeX RDF |
|
17 | Nico Kasprzyk, Andreas Koch 0001, Ulrich Golze, Michael Rock |
An Improved Intermediate Representation for Datapath Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Engineering of Reconfigurable Systems and Algorithms ![In: Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, June 23 - 26, 2003, Las Vegas, Nevada, USA, pp. 88-94, 2003, CSREA Press. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP BibTeX RDF |
|
17 | V. V. Iyer |
Comparison of Verification Methodologies for Datapath Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTV ![In: Fourth International Workshop on Microprocessor Test and Verification, Common Challenges and Solutions (MTV 2003), May 29-30, 2003, Hyatt Town Lake Hotel, Austin, Texas, USA, pp. 27-31, 2003, IEEE Computer Society, 0-7695-2045-6. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Jürgen Becker 0001, Alexander Thomas, Maik Scheer |
Asynchronous Integration of Coarse-Grained Reconfigurable XPP-Arrays Into Pipelined Risc Processor Datapath. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC (Selected Papers) ![In: VLSI-SOC: From Systems to Chips - IFIP TC 10/ WG 10.5 Twelfth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2003), December 1-3, 2003, Darmstadt, Germany, pp. 263-279, 2003, Springer, 978-0-387-33402-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Jürgen Becker 0001, Alexander Thomas, Maik Scheer |
Datapath and Compiler Integration of Coarse-grain Reconfigurable XPP-Arrays into Pipelined RISC Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SOC ![In: IFIP VLSI-SoC 2003, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Darmstadt, Germany, 1-3 December 2003, pp. 288-, 2003, Technische Universität Darmstadt, Insitute of Microelectronic Systems, 3-901882-17-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP BibTeX RDF |
|
17 | Merav Aharoni, Sigal Asaf, Laurent Fournier, Anatoly Koyfman, Raviv Nagel |
FPgen - a test generation framework for datapath floating-point verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HLDVT ![In: Eighth IEEE International High-Level Design Validation and Test Workshop 2003, San Francisco, CA, USA, November 12-14, 2003, pp. 17-22, 2003, IEEE Computer Society, 0-7803-8236-6. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Michiko Inoue, Kazuhiro Suzuki, Hiroyuki Okamoto, Hideo Fujiwara |
Test Synthesis for Datapaths Using Datapath-Controller Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, pp. 294-299, 2003, IEEE Computer Society, 0-7695-1951-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
hierarchical test generation, non-scan design, design-for-testability, at-speed testing, RTL circuit |
17 | Carsten Gremzow, E. Hansen, Nico Moser, Hans-Ulrich Post |
Datapath constrained High-Level Synthesis of Central Memory Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Bremen, Germany, February 24-25, 2003, pp. 144-153, 2003, Shaker. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP BibTeX RDF |
|
17 | Saraju P. Mohanty, Nagarajan Ranganathan, Sunil K. Chappidi |
Transient power minimization through datapath scheduling in multiple supply voltage environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: Proceedings of the 2003 10th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2003, Sharjah, United Arab Emirates, December 14-17, 2003, pp. 300-303, 2003, IEEE, 0-7803-8163-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Kiyoshi Oguri, Yuichiro Shibata, Akira Nagoya |
Asynchronous Bit-Serial Datapath for Object-Oriented Reconfigurable Architecture PCA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asia-Pacific Computer Systems Architecture Conference ![In: Advances in Computer Systems Architecture, 8th Asia-Pacific Conference, ACSAC 2003, Aizu-Wakamatsu, Japan, September 23-26, 2003, Proceedings, pp. 54-68, 2003, Springer, 3-540-20122-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Andy Gean Ye, Jonathan Rose, David M. Lewis |
Architecture of datapath-oriented coarse-grain logic and routing for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: Proceedings of the IEEE Custom Integrated Circuits Conference, CICC 2003, San Jose, CA, USA, September 21 - 24, 2003, pp. 61-64, 2003, IEEE, 0-7803-7842-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Loganathan Lingappan, Srivaths Ravi 0001, Niraj K. Jha |
Test Generation for Non-separable RTL Controller-datapath Circuits using a Satisfiability based Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 21st International Conference on Computer Design (ICCD 2003),VLSI in Computers and Processors, 13-15 October 2003, San Jose, CA, USA, Proceedings, pp. 187-193, 2003, IEEE Computer Society, 0-7695-2025-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Petros Oikonomakos, Mark Zwolinski |
Foundation of Combined Datapath and Controller Self-checking Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 7-9 July 2003, Kos Island, Greece, pp. 30-34, 2003, IEEE Computer Society, 0-7695-1968-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Tony Kirkham, Tughrul Arslan, Fred Westall, David H. Crawford |
A low power datapath for algebraic codebook search targeting a generic GSM system-on-chip platform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoC ![In: Proceedings of the 2003 International Symposium on System-on-Chip, Tampere, Finland, November 19-21, 2003, pp. 53-56, 2003, IEEE, 0-7803-8160-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Gary William Grewal, Mike O'Cleirigh, Charlie Obimbo |
Hierarchical Genetic Algorithms Applied to Datapath Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IC-AI ![In: Proceedings of the International Conference on Artificial Intelligence, IC-AI '03, June 23 - 26, 2003, Las Vegas, Nevada, USA, Volume 2, pp. 994-1002, 2003, CSREA Press, 1-932415-13-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP BibTeX RDF |
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17 | Sérgio G. Araújo, Antonio Carneiro de Mesquita Filho, Aloysio Pedroza |
Optimized Datapath Design by Evolutionary Computation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWSOC ![In: Proceedings of the 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03), 30 June - 2 July 2003, Calgary, Alberta, Canada, pp. 6-9, 2003, IEEE Computer Society, 0-7695-1944-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
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17 | Eric S. Fetzer, Mark Gibson, Anthony Klein, Naomi Calick, Chengyu Zhu, Eric Busta, Baker Mohammad |
A fully bypassed six-issue integer datapath and register file on the Itanium-2 microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 37(11), pp. 1433-1440, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
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17 | Marie-Lise Flottes, Bruno Rouzeyre, Laurent Volpe |
Improving Datapath Testability by Modifying Controller Specification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 15(2), pp. 491-498, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
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17 | Suresh Raman, Sachin S. Sapatnekar, Charles J. Alpert |
Probability-driven routing in a datapath environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 31(2), pp. 159-182, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
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17 | Takahiro Kakimoto, Hiroyuki Ochi, Takao Tsuda |
Datapath-Layout-Driven Design for Low-Power Standard-Cell LSI Implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(12), pp. 2795-2798, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP BibTeX RDF |
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17 | Joerg Abke, Erich Barke |
A Direct Mapping System for Datapath Module and FSM Implementation into LUT-Based FPGAs . ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2002 Design, Automation and Test in Europe Conference and Exposition (DATE 2002), 4-8 March 2002, Paris, France, pp. 1085, 2002, IEEE Computer Society, 0-7695-1471-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
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17 | Nicholas Weaver, John Wawrzynek |
The Effects of Datapath Placement and C-Slow Retiming on Three Computational Benchmarks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 10th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2002), 22-24 April 2002, Napa, CA, USA, Proceedings, pp. 303-, 2002, IEEE Computer Society, 0-7695-1801-X. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
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17 | Masayuki Miyama, Osamu Tooyama, N. Takamatsu, T. Kodake, K. Nakamura, A. Kato, Junichi Miyakoshi, K. Hashimoto, Shigenobu Komatsu, M. Yagi, Masao Morimoto, Kazuo Taki, Masahiko Yoshimoto |
An ultra low power, realtime MPEG2 MP@HL motion estimation processor core with SIMD datapath architecture optimized for gradient descent search algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, CICC 2002, Orlando, FL, USA, May 12-15, 2002, pp. 167-170, 2002, IEEE, 0-7803-7250-6. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
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17 | Herman Schmit, David Whelihan, Andrew Tsai, Matthew Moe, Benjamin A. Levine, R. Reed Taylor |
PipeRench: A virtualized programmable datapath in 0.18 micron technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, CICC 2002, Orlando, FL, USA, May 12-15, 2002, pp. 63-66, 2002, IEEE, 0-7803-7250-6. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
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17 | Andy Gean Ye, Jonathan Rose, David M. Lewis |
Synthesizing datapath circuits for FPGAs with emphasis on area minimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPT ![In: Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, FPT 2002, Hong Kong, China, December 16-18, 2002, pp. 219-226, 2002, IEEE, 0-7803-7574-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
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17 | Wang Jiang Chau, Jose Artur Quilici González, Marius Strum, Ricardo Pires |
BIST Plan Optimization and Independent Input Test Register Insertion for Datapath Functional Units. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATW ![In: 3rd Latin American Test Workshop, LATW 2002, Montevideo, Uruguay, February 10-13, 2002., pp. 64-69, 2002, IEEE. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP BibTeX RDF |
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17 | Masanori Hashimoto, Yashiteru Hayashi, Hidetoshi Onodera |
Experimental Study on Cell-Base High-Performance Datapath Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWLS ![In: 11th IEEE/ACM International Workshop on Logic & Synthesis, IWLS 2002, June 4-7, 2002, New Orleans, Louisiana, USA., pp. 283-287, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP BibTeX RDF |
|
17 | Raik Brinkmann, Rolf Drechsler |
RTL-Datapath Verification using Integer Linear Programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 741-746, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
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17 | George A. Constantinides, Peter Y. K. Cheung, Wayne Luk |
Heuristic datapath allocation for multiple wordlength systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2001, Munich, Germany, March 12-16, 2001, pp. 791-797, 2001, IEEE Computer Society, 0-7695-0993-2. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
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17 | Tatjana Serdar, Carl Sechen |
Automatic datapath tile placement and routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2001, Munich, Germany, March 12-16, 2001, pp. 552-559, 2001, IEEE Computer Society, 0-7695-0993-2. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
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17 | Sabyasachi Das, Sunil P. Khatri |
A regularity-driven fast gridless detailed router for high frequency datapath designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2001 International Symposium on Physical Design, ISPD 2001, Sonoma County, CA, USA, April 1-4, 2001, pp. 130-135, 2001, ACM, 1-58113-347-2. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
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17 | Lijun Gao, Keshab K. Parhi |
Models for power consumption and power grid noise due to datapath transition activity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, West Lafayette, Indiana, USA, 2001, pp. 121-126, 2001, ACM, 1-58113-351-0. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
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17 | Mihalis Psarakis, Antonis M. Paschalis, Nektarios Kranitis, Dimitris Gizopoulos, Yervant Zorian |
Robust and Low-Cost BIST Architectures for Sequential Fault Testing in Datapath Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April - 3 May 2001, Marina Del Rey, CA, USA, pp. 15-21, 2001, IEEE Computer Society, 0-7695-1122-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
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17 | Anmol Mathur, Sanjeev Saluja |
Improved Merging of Datapath Operators using Information Content and Required Precision Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 38th Design Automation Conference, DAC 2001, Las Vegas, NV, USA, June 18-22, 2001, pp. 462-467, 2001, ACM, 1-58113-297-2. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
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17 | Steven R. Carlough, Robert A. Philhower, Cliff A. Maier, Sam A. Steidl, Pete M. Campbell, Atul Garg, Kyung-Suc Nah, Matthew W. Ernest, James R. Loy, Thomas W. Krawczyk Jr., Peter F. Curran, Russell P. Kraft, Hans J. Greub, John F. McDonald 0001 |
A 2-GHz clocked AlGaAs/GaAs HBT byte-slice datapath chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 35(6), pp. 885-894, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
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17 | Han Bin Kim, Dong Sam Ha, Takeshi Takahashi 0003, Takahiro J. Yamaguchi |
A new approach to built-in self-testable datapath synthesis based on integer linear programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 8(5), pp. 594-605, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
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17 | Reiner W. Hartenstein, Thomas Hoffmann 0001, Ulrich Nageldinger |
Design-Space Exploration of Low Power Coarse Grained Reconfigurable Datapath Array Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation, 10th International Workshop, PATMOS 2000, Göttingen, Germany, September 13-15, 2000, Proceedings, pp. 118-128, 2000, Springer, 3-540-41068-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
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17 | Laurence Goodby, Alex Orailoglu |
Test Quality and Fault Risk in Digital Filter Datapath BIST. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2000 Design, Automation and Test in Europe (DATE 2000), 27-30 March 2000, Paris, France, pp. 468-475, 2000, IEEE Computer Society / ACM, 0-7695-0537-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
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17 | David Berthelot, Marie-Lise Flottes, Bruno Rouzeyre |
A method for trading off test time, area and fault coverage in datapath BIST synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETW ![In: 5th European Test Workshop, ETW 2000, Cascais, Portugal, May 23-26, 2000, pp. 133-139, 2000, IEEE Computer Society, 0-7695-0701-8. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
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17 | Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann 0001, Ulrich Nageldinger |
KressArray Xplorer: a new CAD environment to optimize reconfigurable datapath array. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of ASP-DAC 2000, Asia and South Pacific Design Automation Conference 2000, Yokohama, Japan, pp. 163-168, 2000, ACM, 0-7803-5974-7. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
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17 | Suresh Raman, Sachin S. Sapatnekar, Charles J. Alpert |
Datapath routing based on a decongestion metric. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2000 International Symposium on Physical Design, ISPD 2000, San Diego, CA, USA, April 9-12, 2000, pp. 122-127, 2000, ACM, 1-58113-191-7. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
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17 | Hyung-Joon Kwon, Young-Beom Jang, Bangwon Lee |
A Finite Field Processor Employing Dual Parallel Datapath for High-Speed/Low-Power RS-ECC Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE International Conference on Multimedia and Expo (III) ![In: 2000 IEEE International Conference on Multimedia and Expo, ICME 2000, New York, NY, USA, July 30 - August 2, 2000, pp. 1387-1390, 2000, IEEE Computer Society, 0-7803-6536-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
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17 | Marek Wróblewski, Sven Simon 0001, Josef A. Nossek |
Low power transformation of datapath architectures with cyclic SFGs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2000, Emerging Technologies for the 21st Century, Geneva, Switzerland, 28-31 May 2000, Proceedings, pp. 597-600, 2000, IEEE. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
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17 | Marie-Lise Flottes, Bruno Rouzeyre, Laurent Volpe |
A controller resynthesis based method for improving datapath testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2000, Emerging Technologies for the 21st Century, Geneva, Switzerland, 28-31 May 2000, Proceedings, pp. 347-350, 2000, IEEE. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
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17 | Ming-Luen Liou, Tzi-Dar Chiueh |
A parametric module design framework and its application to gate-level datapath/DSP module synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2000, Emerging Technologies for the 21st Century, Geneva, Switzerland, 28-31 May 2000, Proceedings, pp. 41-44, 2000, IEEE. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
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17 | V. A. Zivkovic, Ronald J. W. T. Tangelder, H. G. Herkhoff |
The Test-Cycle Minimization in Parameterized Bus-Oriented Datapath Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATW ![In: 1st Latin American Test Workshop, LATW 2000, Rio de Janeiro, RJ, Brazil, March 13-15, 2000., pp. 215-220, 2000, IEEE. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP BibTeX RDF |
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17 | Katarzyna Radecka, Zeljko Zilic |
Using Arithmetic Transform for Verification of Datapath Circuits via Error Modeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 18th IEEE VLSI Test Symposium (VTS 2000), 30 April - 4 May 2000, Montreal, Canada, pp. 271-280, 2000, IEEE Computer Society, 0-7695-0613-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
arithmetic transforms, functional verification, arithmetic circuits |
17 | Hema Kapadia, Luca Benini, Giovanni De Micheli |
Reducing switching activity on datapath buses with control-signal gating. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 34(3), pp. 405-414, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
17 | Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo |
A 56-bit self-timed adder for high speed asynchronous datapath. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 6th IEEE International Conference on Electronics, Circuits and Systems, ICECS 1999, Pafos, Cyprus, September 5-8, 1999, pp. 37-41, 1999, IEEE, 0-7803-5682-9. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
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17 | Durgam Vahia, Maciej J. Ciesielski |
Transistor level placement for full custom datapath cell design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 1999 International Symposium on Physical Design, ISPD 1999, Monterey, CA, USA, April 12-14, 1999, pp. 158-163, 1999, ACM, 1-58113-089-9. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
17 | Sven Simon 0001, Marek Wróblewski |
Low power datapath design using transformation similar to temporal localization of SFGs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 59-61, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
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17 | Joon-Seo Yim, Chong-Min Kyung |
Reducing Cross-Coupling Among Interconnect Wires in Deep-Submicron Datapath Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 36th Conference on Design Automation, New Orleans, LA, USA, June 21-25, 1999., pp. 485-490, 1999, ACM Press. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
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17 | R. X. T. Nijssen, C. A. J. van Eijk |
GreyHound: A methodology for utilizing datapath regularity in standard design flows. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 25(2), pp. 111-135, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
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17 | Tsuyoshi Isshiki, Takenobu Shimizugashira, Akihisa Ohta, Imanuddin Amril, Hiroaki Kunieda |
A New FPGA Architecture for High-Performance bit-Serial Pipeline Datapath (Abstract). ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, FPGA 1998, Monterey, CA, USA, February 22-24, 1998, pp. 255, 1998, ACM, 0-89791-978-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
17 | Tsuyoshi Isshiki, Takenobu Shimizugashira, Akihisa Ohta, Imanuddin Amril, Hiroaki Kunieda |
FPGA for High-Performance Bit-Serial Pipeline Datapath. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the ASP-DAC '98, Asia and South Pacific Design Automation Conference 1998, Pacifico Yokohama, Yokohama, Japan, February 10-13, 1998, pp. 331-332, 1998, IEEE, 0-7803-4425-1. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
17 | Amit Chowdhary, Sudhakar Kale, Phani K. Saripella, Naresh Sehgal, Rajesh K. Gupta 0001 |
A general approach for regularity extraction in datapath circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1998, San Jose, CA, USA, November 8-12, 1998, pp. 332-339, 1998, ACM / IEEE Computer Society, 1-58113-008-2. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
17 | Hema Kapadia, Giovanni De Micheli, Luca Benini |
Reducing switching activity on datapath buses with control-signal gating. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, CICC 1998, Santa Clara, CA, USA, May 11-14, 1998, pp. 589-592, 1998, IEEE, 0-7803-4292-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
17 | Javier D. Bruguera, Tomás Lang |
Leading-one prediction scheme for latency improvement in single datapath floating-point adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: International Conference on Computer Design: VLSI in Computers and Processors, ICCD 1998, Proceedings, 5-7 October, 1998, Austin, TX, USA, pp. 298-305, 1998, IEEE Computer Society, 0-8186-9099-2. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
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17 | Carina Ben-Zvi, Patrick McGuinness, Franklin Lassandro |
An effective datapath design methodology for high-frequency design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: International Conference on Computer Design: VLSI in Computers and Processors, ICCD 1998, Proceedings, 5-7 October, 1998, Austin, TX, USA, pp. 186-187, 1998, IEEE Computer Society, 0-8186-9099-2. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|