Search results for "datapath"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
17	Thomas Schilling, Magnus Själander, Per Larsson-Edefors	Scheduling for an Embedded Architecture with a Flexible Datapath.	ISVLSI	2009	DBLP DOI BibTeX RDF
17	Johann Großschädl, Erkay Savas, Kazim Yumbul	Realizing Arbitrary-Precision Modular Multiplication with a Fixed-Precision Multiplier Datapath.	ReConFig	2009	DBLP DOI BibTeX RDF	Bit-serial multiplier architecture, Scalability, Montgomery modular multiplication
17	Reto Zimmermann	Datapath Synthesis for Standard-Cell Design.	IEEE Symposium on Computer Arithmetic	2009	DBLP DOI BibTeX RDF
17	Martin Langhammer, Tom VanCourt	FPGA Floating Point Datapath Compiler.	FCCM	2009	DBLP DOI BibTeX RDF	performance computing, optimization, FPGA, floating point
17	Bijan Alizadeh, Masahiro Fujita	Improved heuristics for finite word-length polynomial datapath optimization.	ICCAD	2009	DBLP DOI BibTeX RDF
17	Bo Marr, Brian P. Degnan, Paul E. Hasler, David V. Anderson	An Asynchronously Embedded Datapath for Performance Acceleration and Energy Efficiency.	ISCAS	2009	DBLP DOI BibTeX RDF
17	Saeed Fouladi Fard, Amirhossein Alimohammad, Bruce F. Cockburn, Christian Schlegel	High path-count multirate Rayleigh fading channel simulator with time-multiplexed datapath.	SoCC	2009	DBLP DOI BibTeX RDF
17	Sotirios Xydis, Ioannis Triantafyllou, George Economakos, Kiamal Z. Pekmestzi	Flexible Datapath Synthesis through Arithmetically Optimized Operation Chaining.	AHS	2009	DBLP DOI BibTeX RDF
17	Sohan Purohit, Marco Lanuzza, Stefania Perri, Pasquale Corsonello, Martin Margala	Design-Space Exploration of Energy-Delay-Area Efficient Coarse-Grain Reconfigurable Datapath.	VLSI Design	2009	DBLP DOI BibTeX RDF
17	Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki	Novel Register Sharing in Datapath for Structural Robustness against Delay Variation.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2008	DBLP DOI BibTeX RDF
17	Takayuki Obata, Mineo Kaneko	Simultaneous Optimization of Skew and Control Step Assignments in RT-Datapath Synthesis.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2008	DBLP DOI BibTeX RDF
17	Shubhajit Roy Chowdhury, Dipankar Chakrabarti, Hiranmay Saha	FPGA realization of a smart processing system for clinical diagnostic applications using pipelined datapath architectures.	Microprocess. Microsystems	2008	DBLP DOI BibTeX RDF
17	Doochul Shin, Sandeep K. Gupta 0001	A Re-design Technique for Datapath Modules in Error Tolerant Applications.	ATS	2008	DBLP DOI BibTeX RDF
17	Martin Langhammer	High performance matrix multiply using fused datapath operators.	ACSCC	2008	DBLP DOI BibTeX RDF
17	Kieron Turkington, George A. Constantinides, Peter Y. K. Cheung, Konstantinos Masselos	Co-optimisation of datapath and memory in outer loop pipelining.	FPT	2008	DBLP DOI BibTeX RDF
17	Takayuki Obata, Mineo Kaneko	Concurrent skew and control step assignments in RT-level datapath synthesis.	ISCAS	2008	DBLP DOI BibTeX RDF
17	Shal Vishal	Synthesis of dual-rail datapath circuits.		2008	RDF
17	Zoran Salcic, George G. Coghill, R. Bruce Maunder	A genetic algorithm high-level optimizer for complex datapath and data-flow digital systems.	Appl. Soft Comput.	2007	DBLP DOI BibTeX RDF
17	Antonio M. Lopez Jr., Frederick G. Lopez, Robert W. Lent, Madonna G. Constantine	Multidisciplinary research on the datapath of the computing disciplines.	Commun. ACM	2007	DBLP DOI BibTeX RDF
17	Justin Davis, Robert B. Reese	Finite State Machine Datapath Design, Optimization, and Implementation		2007	DOI RDF
17	Makoto Ikeda, Ken Ishii, Taku Sogabe, Kunihiro Asada	Datapath Delay Distributions for Data/Instruction against PVT Variations in 90nm CMOS.	ICECS	2007	DBLP DOI BibTeX RDF
17	Arash Ahmadi, Mark Zwolinski	Multiple-Width Bus Partitioning Approach to Datapath Synthesis.	ISCAS	2007	DBLP DOI BibTeX RDF
17	Simone Medardoni, Davide Bertozzi, Luca Benini, Enrico Macii	Control and datapath decoupling in the design of a NoC switch: area, power and performance implications.	SoC	2007	DBLP DOI BibTeX RDF
17	Nagaraju Pothineni, Anshul Kumar, Kolin Paul	Application Specific Datapath Extension with Distributed I/O Functional Units.	VLSI Design	2007	DBLP DOI BibTeX RDF
17	Saraju P. Mohanty, Ramakrishna Velagapudi, Elias Kougianos	Physical-aware simulated annealing optimization of gate leakage in nanoscale datapath circuits.	DATE	2006	DBLP DOI BibTeX RDF
17	Mazen A. R. Saghir, Mohamad El-Majzoub, Patrick Akl	Datapath and ISA Customization for Soft VLIW Processors.	ReConFig	2006	DBLP DOI BibTeX RDF
17	John Lofgren, Josefina Hobbs, John McCardle	PSeuDoFFIL: Power Saving Datapath FiFo Insertion Logic.	CGVR	2006	DBLP BibTeX RDF
17	Saraju P. Mohanty, Elias Kougianos, Ramakrishna Velagapudi, Valmiki Mukherjee	Scheduling and binding for low gate leakage nanoCMOS datapath circuit synthesis.	ISCAS	2006	DBLP DOI BibTeX RDF
17	Cid C. de Souza, André M. Lima, Guido Araujo, Nahri Moreano	The datapath merging problem in reconfigurable systems: Complexity, dual bounds and heuristic evaluation.	ACM J. Exp. Algorithmics	2005	DBLP DOI BibTeX RDF	Data path merging, heuristics, lower bounds, reconfigurable systems
17	Mile K. Stojcev	Digital Computer Arithmetic Datapath Design Using Verilog HDL, James E. Stine, Kluwer Academic Publishers, Boston, 2004, ISBN 1-4020-7710-6. Hardcover, pp 180, plus XI.	Microelectron. Reliab.	2005	DBLP DOI BibTeX RDF
17	Saraju P. Mohanty, Nagarajan Ranga Ranganathan	Simultaneous peak and average power minimization during datapath scheduling.	IEEE Trans. Circuits Syst. I Regul. Pap.	2005	DBLP DOI BibTeX RDF
17	Eckhard Grass, Frank Winkler 0001, Milos Krstic, Alexandra Julius, Christian Stahl, Maxim Piz	Enhanced GALS Techniques for Datapath Applications.	PATMOS	2005	DBLP DOI BibTeX RDF
17	Ali Manzak	Temperature Aware Datapath Scheduling.	PATMOS	2005	DBLP DOI BibTeX RDF
17	Konstantinos Katsoulakis, Tughrul Arslan, Tony Kirkham, Sami Khawam	A Low-Power Reconfigurable Datapath for Advanced Speech Coding Algorithms.	IPDPS	2005	DBLP DOI BibTeX RDF
17	Yee William Li, George Patounakis, Kenneth L. Shepard, Steven M. Nowick	High-throughput asynchronous datapath with software-controlled voltage scaling.	IEEE J. Solid State Circuits	2004	DBLP DOI BibTeX RDF
17	Nemanja Isailovic, Mark Whitney, Yatish Patel, John Kubiatowicz, Dean Copsey, Frederic T. Chong, Isaac L. Chuang, Mark Oskin	Datapath and control for quantum wires.	ACM Trans. Archit. Code Optim.	2004	DBLP DOI BibTeX RDF	Architecture, Control, Layout
17	Bob Moore, David Durham, John Strassner, Andrea Westerinen, Walter Weiss	Information Model for Describing Network Device QoS Datapath Mechanisms.	RFC	2004	DBLP DOI BibTeX RDF
17	Sumeet Kumar, Prateek Pujara, Aneesh Aggarwal	Bit-Sliced Datapath for Energy-Efficient High Performance Microprocessors.	PACS	2004	DBLP DOI BibTeX RDF
17	Ingmar Neumann, Dominik Stoffel, Kolja Sulimma, Michel R. C. M. Berkelaar, Wolfgang Kunz	Layout Driven Optimization of Datapath Circuits using Arithmetic Reasoning.	MBMV	2004	DBLP BibTeX RDF
17	Andy Gean Ye, Jonathan Rose	Using multi-bit logic blocks and automated packing to improve field-programmable gate array density for implementing datapath circuits.	FPT	2004	DBLP DOI BibTeX RDF
17	Hongtu Jiang, Viktor Öwall	FPGA implementation of controller-datapath pair in custom image processor design.	ISCAS (5)	2004	DBLP BibTeX RDF
17	Masanori Hashimoto, Yoshiteru Hayashi, Hidetoshi Onodera	Experimental Study on Cell-Base High-Performance Datapath Design.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2003	DBLP BibTeX RDF
17	Nico Kasprzyk, Andreas Koch 0001, Ulrich Golze, Michael Rock	An Improved Intermediate Representation for Datapath Generation.	Engineering of Reconfigurable Systems and Algorithms	2003	DBLP BibTeX RDF
17	V. V. Iyer	Comparison of Verification Methodologies for Datapath Testing.	MTV	2003	DBLP DOI BibTeX RDF
17	Jürgen Becker 0001, Alexander Thomas, Maik Scheer	Asynchronous Integration of Coarse-Grained Reconfigurable XPP-Arrays Into Pipelined Risc Processor Datapath.	VLSI-SoC (Selected Papers)	2003	DBLP DOI BibTeX RDF
17	Jürgen Becker 0001, Alexander Thomas, Maik Scheer	Datapath and Compiler Integration of Coarse-grain Reconfigurable XPP-Arrays into Pipelined RISC Processors.	VLSI-SOC	2003	DBLP BibTeX RDF
17	Merav Aharoni, Sigal Asaf, Laurent Fournier, Anatoly Koyfman, Raviv Nagel	FPgen - a test generation framework for datapath floating-point verification.	HLDVT	2003	DBLP DOI BibTeX RDF
17	Michiko Inoue, Kazuhiro Suzuki, Hiroyuki Okamoto, Hideo Fujiwara	Test Synthesis for Datapaths Using Datapath-Controller Functions.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF	hierarchical test generation, non-scan design, design-for-testability, at-speed testing, RTL circuit
17	Carsten Gremzow, E. Hansen, Nico Moser, Hans-Ulrich Post	Datapath constrained High-Level Synthesis of Central Memory Architectures.	MBMV	2003	DBLP BibTeX RDF
17	Saraju P. Mohanty, Nagarajan Ranganathan, Sunil K. Chappidi	Transient power minimization through datapath scheduling in multiple supply voltage environment.	ICECS	2003	DBLP DOI BibTeX RDF
17	Kiyoshi Oguri, Yuichiro Shibata, Akira Nagoya	Asynchronous Bit-Serial Datapath for Object-Oriented Reconfigurable Architecture PCA.	Asia-Pacific Computer Systems Architecture Conference	2003	DBLP DOI BibTeX RDF
17	Andy Gean Ye, Jonathan Rose, David M. Lewis	Architecture of datapath-oriented coarse-grain logic and routing for FPGAs.	CICC	2003	DBLP DOI BibTeX RDF
17	Loganathan Lingappan, Srivaths Ravi 0001, Niraj K. Jha	Test Generation for Non-separable RTL Controller-datapath Circuits using a Satisfiability based Approach.	ICCD	2003	DBLP DOI BibTeX RDF
17	Petros Oikonomakos, Mark Zwolinski	Foundation of Combined Datapath and Controller Self-checking Design.	IOLTS	2003	DBLP DOI BibTeX RDF
17	Tony Kirkham, Tughrul Arslan, Fred Westall, David H. Crawford	A low power datapath for algebraic codebook search targeting a generic GSM system-on-chip platform.	SoC	2003	DBLP DOI BibTeX RDF
17	Gary William Grewal, Mike O'Cleirigh, Charlie Obimbo	Hierarchical Genetic Algorithms Applied to Datapath Synthesis.	IC-AI	2003	DBLP BibTeX RDF
17	Sérgio G. Araújo, Antonio Carneiro de Mesquita Filho, Aloysio Pedroza	Optimized Datapath Design by Evolutionary Computation.	IWSOC	2003	DBLP DOI BibTeX RDF
17	Eric S. Fetzer, Mark Gibson, Anthony Klein, Naomi Calick, Chengyu Zhu, Eric Busta, Baker Mohammad	A fully bypassed six-issue integer datapath and register file on the Itanium-2 microprocessor.	IEEE J. Solid State Circuits	2002	DBLP DOI BibTeX RDF
17	Marie-Lise Flottes, Bruno Rouzeyre, Laurent Volpe	Improving Datapath Testability by Modifying Controller Specification.	VLSI Design	2002	DBLP DOI BibTeX RDF
17	Suresh Raman, Sachin S. Sapatnekar, Charles J. Alpert	Probability-driven routing in a datapath environment.	Integr.	2002	DBLP DOI BibTeX RDF
17	Takahiro Kakimoto, Hiroyuki Ochi, Takao Tsuda	Datapath-Layout-Driven Design for Low-Power Standard-Cell LSI Implementation.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2002	DBLP BibTeX RDF
17	Joerg Abke, Erich Barke	A Direct Mapping System for Datapath Module and FSM Implementation into LUT-Based FPGAs .	DATE	2002	DBLP DOI BibTeX RDF
17	Nicholas Weaver, John Wawrzynek	The Effects of Datapath Placement and C-Slow Retiming on Three Computational Benchmarks.	FCCM	2002	DBLP DOI BibTeX RDF
17	Masayuki Miyama, Osamu Tooyama, N. Takamatsu, T. Kodake, K. Nakamura, A. Kato, Junichi Miyakoshi, K. Hashimoto, Shigenobu Komatsu, M. Yagi, Masao Morimoto, Kazuo Taki, Masahiko Yoshimoto	An ultra low power, realtime MPEG2 MP@HL motion estimation processor core with SIMD datapath architecture optimized for gradient descent search algorithm.	CICC	2002	DBLP DOI BibTeX RDF
17	Herman Schmit, David Whelihan, Andrew Tsai, Matthew Moe, Benjamin A. Levine, R. Reed Taylor	PipeRench: A virtualized programmable datapath in 0.18 micron technology.	CICC	2002	DBLP DOI BibTeX RDF
17	Andy Gean Ye, Jonathan Rose, David M. Lewis	Synthesizing datapath circuits for FPGAs with emphasis on area minimization.	FPT	2002	DBLP DOI BibTeX RDF
17	Wang Jiang Chau, Jose Artur Quilici González, Marius Strum, Ricardo Pires	BIST Plan Optimization and Independent Input Test Register Insertion for Datapath Functional Units.	LATW	2002	DBLP BibTeX RDF
17	Masanori Hashimoto, Yashiteru Hayashi, Hidetoshi Onodera	Experimental Study on Cell-Base High-Performance Datapath Design.	IWLS	2002	DBLP BibTeX RDF
17	Raik Brinkmann, Rolf Drechsler	RTL-Datapath Verification using Integer Linear Programming.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
17	George A. Constantinides, Peter Y. K. Cheung, Wayne Luk	Heuristic datapath allocation for multiple wordlength systems.	DATE	2001	DBLP DOI BibTeX RDF
17	Tatjana Serdar, Carl Sechen	Automatic datapath tile placement and routing.	DATE	2001	DBLP DOI BibTeX RDF
17	Sabyasachi Das, Sunil P. Khatri	A regularity-driven fast gridless detailed router for high frequency datapath designs.	ISPD	2001	DBLP DOI BibTeX RDF
17	Lijun Gao, Keshab K. Parhi	Models for power consumption and power grid noise due to datapath transition activity.	ACM Great Lakes Symposium on VLSI	2001	DBLP DOI BibTeX RDF
17	Mihalis Psarakis, Antonis M. Paschalis, Nektarios Kranitis, Dimitris Gizopoulos, Yervant Zorian	Robust and Low-Cost BIST Architectures for Sequential Fault Testing in Datapath Multipliers.	VTS	2001	DBLP DOI BibTeX RDF
17	Anmol Mathur, Sanjeev Saluja	Improved Merging of Datapath Operators using Information Content and Required Precision Analysis.	DAC	2001	DBLP DOI BibTeX RDF
17	Steven R. Carlough, Robert A. Philhower, Cliff A. Maier, Sam A. Steidl, Pete M. Campbell, Atul Garg, Kyung-Suc Nah, Matthew W. Ernest, James R. Loy, Thomas W. Krawczyk Jr., Peter F. Curran, Russell P. Kraft, Hans J. Greub, John F. McDonald 0001	A 2-GHz clocked AlGaAs/GaAs HBT byte-slice datapath chip.	IEEE J. Solid State Circuits	2000	DBLP DOI BibTeX RDF
17	Han Bin Kim, Dong Sam Ha, Takeshi Takahashi 0003, Takahiro J. Yamaguchi	A new approach to built-in self-testable datapath synthesis based on integer linear programming.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
17	Reiner W. Hartenstein, Thomas Hoffmann 0001, Ulrich Nageldinger	Design-Space Exploration of Low Power Coarse Grained Reconfigurable Datapath Array Architectures.	PATMOS	2000	DBLP DOI BibTeX RDF
17	Laurence Goodby, Alex Orailoglu	Test Quality and Fault Risk in Digital Filter Datapath BIST.	DATE	2000	DBLP DOI BibTeX RDF
17	David Berthelot, Marie-Lise Flottes, Bruno Rouzeyre	A method for trading off test time, area and fault coverage in datapath BIST synthesis.	ETW	2000	DBLP DOI BibTeX RDF
17	Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann 0001, Ulrich Nageldinger	KressArray Xplorer: a new CAD environment to optimize reconfigurable datapath array.	ASP-DAC	2000	DBLP DOI BibTeX RDF
17	Suresh Raman, Sachin S. Sapatnekar, Charles J. Alpert	Datapath routing based on a decongestion metric.	ISPD	2000	DBLP DOI BibTeX RDF
17	Hyung-Joon Kwon, Young-Beom Jang, Bangwon Lee	A Finite Field Processor Employing Dual Parallel Datapath for High-Speed/Low-Power RS-ECC Applications.	IEEE International Conference on Multimedia and Expo (III)	2000	DBLP DOI BibTeX RDF
17	Marek Wróblewski, Sven Simon 0001, Josef A. Nossek	Low power transformation of datapath architectures with cyclic SFGs.	ISCAS	2000	DBLP DOI BibTeX RDF
17	Marie-Lise Flottes, Bruno Rouzeyre, Laurent Volpe	A controller resynthesis based method for improving datapath testability.	ISCAS	2000	DBLP DOI BibTeX RDF
17	Ming-Luen Liou, Tzi-Dar Chiueh	A parametric module design framework and its application to gate-level datapath/DSP module synthesis.	ISCAS	2000	DBLP DOI BibTeX RDF
17	V. A. Zivkovic, Ronald J. W. T. Tangelder, H. G. Herkhoff	The Test-Cycle Minimization in Parameterized Bus-Oriented Datapath Designs.	LATW	2000	DBLP BibTeX RDF
17	Katarzyna Radecka, Zeljko Zilic	Using Arithmetic Transform for Verification of Datapath Circuits via Error Modeling.	VTS	2000	DBLP DOI BibTeX RDF	arithmetic transforms, functional verification, arithmetic circuits
17	Hema Kapadia, Luca Benini, Giovanni De Micheli	Reducing switching activity on datapath buses with control-signal gating.	IEEE J. Solid State Circuits	1999	DBLP DOI BibTeX RDF
17	Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo	A 56-bit self-timed adder for high speed asynchronous datapath.	ICECS	1999	DBLP DOI BibTeX RDF
17	Durgam Vahia, Maciej J. Ciesielski	Transistor level placement for full custom datapath cell design.	ISPD	1999	DBLP DOI BibTeX RDF
17	Sven Simon 0001, Marek Wróblewski	Low power datapath design using transformation similar to temporal localization of SFGs.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
17	Joon-Seo Yim, Chong-Min Kyung	Reducing Cross-Coupling Among Interconnect Wires in Deep-Submicron Datapath Design.	DAC	1999	DBLP DOI BibTeX RDF
17	R. X. T. Nijssen, C. A. J. van Eijk	GreyHound: A methodology for utilizing datapath regularity in standard design flows.	Integr.	1998	DBLP DOI BibTeX RDF
17	Tsuyoshi Isshiki, Takenobu Shimizugashira, Akihisa Ohta, Imanuddin Amril, Hiroaki Kunieda	A New FPGA Architecture for High-Performance bit-Serial Pipeline Datapath (Abstract).	FPGA	1998	DBLP DOI BibTeX RDF
17	Tsuyoshi Isshiki, Takenobu Shimizugashira, Akihisa Ohta, Imanuddin Amril, Hiroaki Kunieda	FPGA for High-Performance Bit-Serial Pipeline Datapath.	ASP-DAC	1998	DBLP DOI BibTeX RDF
17	Amit Chowdhary, Sudhakar Kale, Phani K. Saripella, Naresh Sehgal, Rajesh K. Gupta 0001	A general approach for regularity extraction in datapath circuits.	ICCAD	1998	DBLP DOI BibTeX RDF
17	Hema Kapadia, Giovanni De Micheli, Luca Benini	Reducing switching activity on datapath buses with control-signal gating.	CICC	1998	DBLP DOI BibTeX RDF
17	Javier D. Bruguera, Tomás Lang	Leading-one prediction scheme for latency improvement in single datapath floating-point adders.	ICCD	1998	DBLP DOI BibTeX RDF
17	Carina Ben-Zvi, Patrick McGuinness, Franklin Lassandro	An effective datapath design methodology for high-frequency design.	ICCD	1998	DBLP DOI BibTeX RDF