Search results for "sizing"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
15	Kan-Lin Hsiung	Design of High-Speed Metal-Semiconductor-Metal Photodetectors: An Optimization-Based Approach.	DELTA	2006	DBLP DOI BibTeX RDF
15	Retsef Levi, Martin Pál, Robin Roundy, David B. Shmoys	Approximation Algorithms for Stochastic Inventory Control Models.	IPCO	2005	DBLP DOI BibTeX RDF
15	Anton Valouev, Lei Li, Yu-Chi Liu, David C. Schwartz, Yi Yang 0047, Yu Zhang 0002, Michael S. Waterman	Alignment of Optical Maps.	RECOMB	2005	DBLP DOI BibTeX RDF
15	Jeng-Liang Tsai, Charlie Chung-Ping Chen	Process-variation robust and low-power zero-skew buffered clock-tree synthesis using projected scan-line sampling.	ASP-DAC	2005	DBLP DOI BibTeX RDF
15	Youngmoon Choi, Earl E. Swartzlander Jr.	Parallel Prefix Adder Design with Matrix Representation.	IEEE Symposium on Computer Arithmetic	2005	DBLP DOI BibTeX RDF
15	Anuradha Agarwal, Ranga Vemuri	Layout-Aware RF Circuit Synthesis Driven by Worst Case Parasitic Corners.	ICCD	2005	DBLP DOI BibTeX RDF
15	Min Pan, Chris C. N. Chu, J. Morris Chang	Transition time bounded low-power clock tree construction.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
15	Ning Fu, Shigetoshi Nakatake, Yasuhiro Takashima, Yoji Kajitani	The oct-touched tile: a new architecture for shape-based routing.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	OTT updated according to the obstacles, shape-based routing, routing architecture
15	Daniel Quadt	A Hierarchical Production Planning Approach for Multiprocessor Flow Shops.	OR	2005	DBLP DOI BibTeX RDF
15	Cliff C. N. Sze, Charles J. Alpert, Jiang Hu, Weiping Shi	Path based buffer insertion.	DAC	2005	DBLP DOI BibTeX RDF	layout, physical design, global routing, buffer insertion, power minimization, interconnect synthesis
15	Alex Garthwaite, David Dice, Derek White	Supporting per-processor local-allocation buffers using lightweight user-level preemption notification.	VEE	2005	DBLP DOI BibTeX RDF	restartable critical sections, locality, memory allocation
15	Fabricio B. Bastian, Cristiano Lazzari, José Luís Almada Güntzel, Ricardo Reis 0001	A New Transistor Folding Algorithm Applied to an Automatic Full-Custom Layout Generation Tool.	PATMOS	2004	DBLP DOI BibTeX RDF
15	A. E. Eiben, Elena Marchiori, V. A. Valkó	Evolutionary Algorithms with On-the-Fly Population Size Adjustment.	PPSN	2004	DBLP DOI BibTeX RDF
15	Chandrasekar Rajagopal, Adrián Núñez-Aldana	CMOS Analog Programmable Logic Array.	ISVLSI	2004	DBLP DOI BibTeX RDF
15	Vikas Chandra, Anthony Xu, Herman Schmit, Lawrence T. Pileggi	An Interconnect Channel Design Methodology for High Performance Integrated Circuits.	DATE	2004	DBLP DOI BibTeX RDF
15	Changbo Long, Jinjun Xiong, Lei He 0001	On optimal physical synthesis of sleep transistors.	ISPD	2004	DBLP DOI BibTeX RDF	physical design, power-gating, sleep transistors
15	Adam Engelhart, Mark K. Gardner, Wu-chun Feng	Re-Architecting Flow Control Adaptation for Grid Environments.	IPDPS	2004	DBLP DOI BibTeX RDF
15	João Ramos, Kenneth Francken, Georges G. E. Gielen, Michiel Steyaert	Knowledge- and optimization-based design of RF power amplifiers.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
15	Raoul F. Badaoui, Hemanth Sampath, Anuradha Agarwal, Ranga Vemuri	A high level language for pre-layout extraction in parasite-aware analog circuit synthesis.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	MSL, pre-layout extraction, parasitics, analog VLSI
15	Pedro F. Vieira, Leonardo Bruno de Sá, João P. B. Botelho, Antonio Carneiro de Mesquita Filho	Evolutionary Synthesis of Analog Circuits Using Only MOS Transistors.	Evolvable Hardware	2004	DBLP DOI BibTeX RDF
15	Li-Da Huang, Minghorng Lai, Martin D. F. Wong, Youxin Gao	Maze routing with buffer insertion under transition time constraints.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
15	Frederic Cordier, Hyewon Seo, Nadia Magnenat-Thalmann	Made-to-Measure Technologies for an Online Clothing Store.	IEEE Computer Graphics and Applications	2003	DBLP DOI BibTeX RDF
15	Tom Eeckelaert, Walter Daems, Georges G. E. Gielen, Willy M. C. Sansen	Generalized Posynomial Performance Modeling.	DATE	2003	DBLP DOI BibTeX RDF
15	Jennifer Y.-L. Lo, Wu-An Kuo, Allen C.-H. Wu, TingTing Hwang	A Custom-Cell Identification Method for High-Performance Mixed Standard/Custom-Cell Designs.	DATE	2003	DBLP DOI BibTeX RDF
15	Will Casey, Bud Mishra	A Nearly Linear-Time General Algorithm for Genome-Wide Bi-allele Haplotype Phasing.	HiPC	2003	DBLP DOI BibTeX RDF
15	Soroush Abbaspour, Massoud Pedram, Payam Heydari	Optimizing the Energy-Delay-Ringing Product in On-Chip CMOS Line Drivers.	ISQED	2003	DBLP DOI BibTeX RDF
15	Vani Prasad, Madhav P. Desai	Interconnect Delay Minimization Using a Novel Pre-Mid-Post Buffer Strategy.	VLSI Design	2003	DBLP DOI BibTeX RDF
15	Li-Da Huang, Minghorng Lai, D. F. Wong 0001, Youxin Gao	Maze Routing with Buffer Insertion under Transition Time Constraints.	DATE	2002	DBLP DOI BibTeX RDF
15	Murat R. Becer, Vladimir Zolotov, David T. Blaauw, Rajendran Panda, Ibrahim N. Hajj	Analysis of Noise Avoidance Techniques in DSM Interconnects Using a Complete Crosstalk Noise Model .	DATE	2002	DBLP DOI BibTeX RDF
15	Wei Chen, Massoud Pedram, Premal Buch	Buffered Routing Tree Construction under Buffer Placement Blockages.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	Blockage, Routing, Buffer
15	Sunil Rafeeque	Area efficient current steering DAC using current tuning.	APCCAS (1)	2002	DBLP DOI BibTeX RDF
15	Yu-Yen Mo, Chris C. N. Chu	Hybrid dynamic/quadratic programming algorithm for interconnecttree optimization.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
15	Geert Van der Plas, Geert Debyser, Francky Leyn, Koen Lampaert, Jan Vandenbussche, Georges G. E. Gielen, Willy M. C. Sansen, Petar Veselinovic, Domine Leenaerts	AMGIE-A synthesis environment for CMOS analog integrated circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
15	Te-Kai Liu, Santhosh Kumaran, Zongwei Luo	Layered Queueing Models for Enterprise JavaBean Applications.	EDOC	2001	DBLP DOI BibTeX RDF
15	Jiang Hu, Sachin S. Sapatnekar	Algorithms for non-Hanan-based optimization for VLSI interconnectunder a higher-order AWE model.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
15	Forrest H. Bennett III, John R. Koza, Jessen Yu, William Mydlowec	Automatic Synthesis, Placement, and Routing of an Amplifier Circuit by Means of Genetic Programming.	ICES	2000	DBLP DOI BibTeX RDF
15	Mohamed Dessouky, Marie-Minerve Louërat	A Layout Approach for Electrical and Physical Design Integration of High-Performance Analog Circuits.	ISQED	2000	DBLP DOI BibTeX RDF	Analog layout, layout generation
15	Ingmar Neumann, Dominik Stoffel, Hendrik Hartje, Wolfgang Kunz	Cell replication and redundancy elimination during placement for cycle time optimization.	ICCAD	1999	DBLP DOI BibTeX RDF
15	Kenneth Francken, Georges G. E. Gielen	Methodology for analog technology porting including performance tuning.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
15	Josef Eckmüller, Martin Groepl, Helmut E. Graeb	Hierarchical Characterization of Analog Integrated CMOS Circuits.	DATE	1998	DBLP DOI BibTeX RDF	hierarchical characterization, circuit class, topology independent, transistor pairs, circuit performances, functional constraints
15	Jason Cong, Lei He 0001	An efficient technique for device and interconnect optimization in deep submicron designs.	ISPD	1998	DBLP DOI BibTeX RDF
15	K. Ravi Shanker, Vinita Vasudevan	Synthesis of Analog CMOS Circuits.	VLSI Design	1997	DBLP DOI BibTeX RDF	synthesis, analog circuits
15	Chia-Chun Tsai, De-Yu Kao, Chung-Kuan Cheng	Performance driven bus buffer insertion.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
15	Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin	Power-delay characteristics of CMOS adders.	IEEE Trans. Very Large Scale Integr. Syst.	1994	DBLP DOI BibTeX RDF
15	Weitong Chuang, Ibrahim N. Hajj	Delay and area optimization for compact placement by gate resizing and relocation.	ICCAD	1994	DBLP DOI BibTeX RDF
15	Uwe Hinsberger, Reiner Kolla	A cell-based approach to performance optimization of fanout-free circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
15	Mark Hofmann, Jae K. Kim	Delay Optimization of Combinational Static CMOS Logic.	DAC	1987	DBLP DOI BibTeX RDF
14	Jonathan F. Bard, Narameth Nananukul	The integrated production-inventory-distribution-routing problem.	J. Sched.	2009	DBLP DOI BibTeX RDF	Allocation model, Tabu search, Vehicle routing problem, Inventory, Production planning, Lot-sizing
14	Julien Dardenne, Sébastien Valette, Nicolas Siauve, Noël Burais, Rémy Prost	Variational tetrahedral mesh generation from discrete volume data.	Vis. Comput.	2009	DBLP DOI BibTeX RDF	Discrete data, Centroidal Voronoi Diagrams, Sizing field, Tetrahedral meshing
14	Jianwei Niu 0003, Zhizhong Li 0003, Song Xu	Block Division for 3D Head Shape Clustering.	HCI (11)	2009	DBLP DOI BibTeX RDF	Three dimensional anthropometry, block-division, clustering, sizing
14	Kaushik Roy 0001, Jaydeep P. Kulkarni, Sumeet Kumar Gupta	Device/circuit interactions at 22nm technology node.	DAC	2009	DBLP DOI BibTeX RDF	22 nm technology node, DG MOSFETs, scaling, SRAM, transistor sizing, FinFETs
14	André L. V. Coelho, Daniel G. de Oliveira	Dynamically tuning the population size in particle swarm optimization.	SAC	2008	DBLP DOI BibTeX RDF	numerical optimization, population sizing, parameter control
14	Rosane Maria Maffei Vallim, David E. Goldberg, Xavier Llorà, Thyago S. P. C. Duque, André C. P. L. F. de Carvalho	A new approach for multi-label classification based on default hierarchies and organizational learning.	GECCO (Companion)	2008	DBLP DOI BibTeX RDF	default hierarchies, organizational sizing, LCS
14	Bill Stackpole	The evolution of a virtualized laboratory environment.	SIGITE Conference	2008	DBLP DOI BibTeX RDF	curricular issues, laboratory environments, system sizing and benchmarking, networking, virtualization, distance learning, it education
14	Robert Shorten, Douglas J. Leith	On queue provisioning, network efficiency and the transmission control protocol.	IEEE/ACM Trans. Netw.	2007	DBLP DOI BibTeX RDF	TCP, TCP/IP, buffer sizing, AIMD
14	Jeegar Tilak Shah, Marius Evers, Jeff Trull, Alper Halbutogullari	Circuit optimization for leakage power reduction using multi-threshold voltages for high performance microprocessors.	ISPD	2007	DBLP DOI BibTeX RDF	multi-VTH, optimization, timing, low-power design, microprocessor, EDA, leakage power, sizing
14	Kumara Sastry, David E. Goldberg, Xavier Llorà	Towards billion-bit optimization via a parallel estimation of distribution algorithm.	GECCO	2007	DBLP DOI BibTeX RDF	billion-variable optimization, parallelization, vectorization, population sizing, large-scale optimization, efficiency enhancement, convergence time, scalability analysis, compact genetic algorithm
14	Kumara Sastry, Martin Pelikan, David E. Goldberg	Empirical analysis of ideal recombination on random decomposable problems.	GECCO	2007	DBLP DOI BibTeX RDF	additively-decomposable problems, ideal crossover, genetic algorithms, building blocks, empirical analysis, population sizing, convergence time, problem difficulty, test problems, scalability analysis
14	Chengliang Zhang, Kirk Kelsey, Xipeng Shen, Chen Ding 0001, Matthew Hertz, Mitsunori Ogihara	Program-level adaptive memory management.	ISMM	2006	DBLP DOI BibTeX RDF	heap sizing, program-level, adaptive, garbage collection, paging
14	Kumara Sastry, D. D. Johnson, Alexis L. Thompson, David E. Goldberg, Todd J. Martínez, Jeff Leiding, Jane Owens	Multiobjective genetic algorithms for multiscaling excited state direct dynamics in photochemistry.	GECCO	2006	DBLP DOI BibTeX RDF	multiobjective genetic algorithms, non-domination, photochemistry, semiempirical methods, niching, population sizing, NSGA-II, convergence time, multiscale modeling
14	Alan Piszcz, Terence Soule	Genetic programming: optimal population sizes for varying complexity problems.	GECCO	2006	DBLP DOI BibTeX RDF	MAX binary tree problem, binomial-3, optimal, population sizing, problem difficulty
14	Sherif Hammouda, Hazem Said, Mohamed Dessouky, Mohamed Tawfik, Quang Nguyen, Wael M. Badawy, Hazem M. Abbas, Hussein I. Shahein	Chameleon ART: a non-optimization based analog design migration framework.	DAC	2006	DBLP DOI BibTeX RDF	analog reuse, design extraction, layout compaction, layout retargeting, circuit sizing
14	Ming-Jong Yao	The Economic Lot Scheduling Problem without Capacity Constraints.	Ann. Oper. Res.	2005	DBLP DOI BibTeX RDF	scheduling, production, search algorithm, inventory, lot sizing
14	Pierre Alliez, David Cohen-Steiner, Mariette Yvinec, Mathieu Desbrun	Variational tetrahedral meshing.	ACM Trans. Graph.	2005	DBLP DOI BibTeX RDF	delaunay mesh, isotropic meshing, sizing field, slivers
14	Anuradha Agarwal, Glenn Wolfe, Ranga Vemuri	Accuracy driven performance macromodeling of feasible regions during synthesis of analog circuits.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	performance modeling, circuit sizing, analog synthesis
14	Huan-Yun Wei, Shih-Chiang Tsao, Ying-Dar Jason Lin	Assessing and Improving TCP Rate Shaping over Edge Gateways.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	rate enforcement, ACK-pacing, scheduling, TCP, testbed, packet scheduler, queuing, Bandwidth management, window-sizing
14	Peter-Michael Seidel, Guy Even	Delay-Optimized Implementation of IEEE Floating-Point Addition.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	IEEE rounding, dual path algorithm, optimized gate sizing, buffer insertion, delay optimization, logical effort, Floating-point addition
14	Gang Zhang, E. Aykut Dengi, Ronald A. Rohrer, Rob A. Rutenbar, L. Richard Carley	A synthesis flow toward fast parasitic closure for radio-frequency integrated circuits.	DAC	2004	DBLP DOI BibTeX RDF	modeling, synthesis, layout, sizing, parasitic, radio frequency
14	Te-Kai Liu, Amir Behroozi, Santhosh Kumaran	A performance model for a BPI middleware.	EC	2003	DBLP DOI BibTeX RDF	business process integration middleware, capacity sizing, e-commerce workload, layered queueing model, synchronous and asynchronous requests, thread pool tuning, benchmark, performance modeling
14	Sergio F. Ochoa, M. Cecilia Bastarrica, Germán Parra	Estimating the Development Effort of Web Projects in Chile.	LA-WEB	2003	DBLP DOI BibTeX RDF	Effort Estimation Method, Sizing Metric, Web Engineering, Web-based Information Systems
14	Stephen P. Boyd, Lieven Vandenberghe, Abbas El Gamal, Sunghee Yun	Design of robust global power and ground networks.	ISPD	2001	DBLP DOI BibTeX RDF	interconnect sizing, power and ground network design, convex optimization
14	Shiyou Zhao, Kaushik Roy 0001, Cheng-Kok Koh	Decoupling capacitance allocation for power supply noise suppression.	ISPD	2001	DBLP DOI BibTeX RDF	interconnect sizing, power and ground network design, convex optimization
14	Laurence D. Merkle, George H. Gates Jr., Gary B. Lamont	Scalability of an MPI-based fast messy genetic algorithm.	SAC	1998	DBLP DOI BibTeX RDF	fixed solution quality, messy genetic algorithms, polypeptide structure prediction, parallel genetic algorithms, population sizing
14	Michael Orshansky, James C. Chen, Chenming Hu	A Statistical Performance Simulation Methodology for VLSI Circuits.	DAC	1998	DBLP DOI BibTeX RDF	migration, timing optimazation, custom sizing
14	Jason Cong, Patrick H. Madden	Performance Driven Multi-Layer General Area Routing for PCB/MCM Designs.	DAC	1998	DBLP DOI BibTeX RDF	logic synthesis, gate-sizing, fanout optimization
14	Al Dunlop, Alper Demir 0001, Peter Feldmann, Sharad Kapur, David E. Long, Robert C. Melville, Jaijeet S. Roychowdhury	Tools and Methodology for RF IC Design.	DAC	1998	DBLP DOI BibTeX RDF	migration, timing optimazation, custom sizing
14	Hsiao-Ping Tseng, Louis Scheffer, Carl Sechen	Timing and Crosstalk Driven Area Routing.	DAC	1998	DBLP DOI BibTeX RDF	logic synthesis, gate-sizing, fanout optimization
14	Bogdan G. Arsintescu, Edoardo Charbon, Enrico Malavasi, Umakanta Choudhury, William H. Kao	General AC Constraint Transformation for Analog ICs.	DAC	1998	DBLP DOI BibTeX RDF	logic synthesis, gate-sizing, fanout optimization
14	David S. Kung 0001	A Fast Fanout Optimization Algorithm for Near-Continuous Buffer Libraries.	DAC	1998	DBLP DOI BibTeX RDF	logic synthesis, gate-sizing, fanout optimization
14	Behzad Razavi	RF IC Design Challenges.	DAC	1998	DBLP DOI BibTeX RDF	migration, timing optimazation, custom sizing
14	Charles J. Alpert, Anirudh Devgan, Stephen T. Quay	Buffer Insertion for Noise and Delay Optimization.	DAC	1998	DBLP DOI BibTeX RDF	logic synthesis, gate-sizing, fanout optimization
14	Rajendran Panda, Abhijit Dharchoudhury, Tim Edwards, Joe Norton, David T. Blaauw	Migration: A New Technique to Improve Synthesized Designs Through Incremental Customization.	DAC	1998	DBLP DOI BibTeX RDF	migration, timing optimazation, custom sizing
14	Julian Culetu, Chaim Amir, John MacDonald	A Practical Repeater Insertion Method in High Speed VLSI Circuits.	DAC	1998	DBLP DOI BibTeX RDF	migration, timing optimazation, custom sizing
14	Frank Y. Yuan	Electromagnetic Modeling and Signal Integrity Simulation of Power/Ground Networks in High Speed Digital Packages and Printed Circuit Boards.	DAC	1998	DBLP DOI BibTeX RDF	migration, timing optimazation, custom sizing
14	Hai Zhou 0001, D. F. Wong 0001	Global Routing with Crosstalk Constraints.	DAC	1998	DBLP DOI BibTeX RDF	logic synthesis, gate-sizing, fanout optimization
14	Arun N. Lokanathan, Jay B. Brockman	Process Multi-Circuit Optimization.	DAC	1998	DBLP DOI BibTeX RDF	logic synthesis, gate-sizing, fanout optimization
14	Paolo Ienne, Alexander Grießing	Practical Experiences with Standard-Cell Based Datapath Design Tools: Do We Really Need Regular Layouts?	DAC	1998	DBLP DOI BibTeX RDF	migration, timing optimazation, custom sizing
14	Atsushi Takahashi 0001, Kazunori Inoue, Yoji Kajitani	Clock-tree routing realizing a clock-schedule for semi-synchronous circuits.	ICCAD	1997	DBLP DOI BibTeX RDF	clock-tree routing, semi-synchronous, deferred-merge-embedding (DME), synchronous, buffer insertion, buffer sizing, clock-schedule
14	Martin Zauner	CASE - Computer-Aided Systems Engineering, a New Approach for Developing IM-Systems with Special Consideration of CIM Systems.	EUROCAST	1993	DBLP DOI BibTeX RDF	active database management systems, client/server concepts, CIM concept, IM concepts, right-sizing, prototyping, open systems, RDBMS
14	Robert G. Arnold, Robert O. Berg, James W. Thomas	A Modular Approach to Real-Time Supersystems.	IEEE Trans. Computers	1982	DBLP DOI BibTeX RDF	real-time embedded computers, Architectural building blocks, data driven software structure, example system sizing, memory/processor tradeoff, distributed computing, high performance, expandable, high throughput, architecture optimization
11	Abdelaziz Lberni, Malika Alami Marktani, Abdelaziz Ahaitouf, Ali Ahaitouf	Analog circuit sizing based on Evolutionary Algorithms and deep learning.	Expert Syst. Appl.	2024	DBLP DOI BibTeX RDF
11	Wenjie Ao, Jiawei Chen 0002, Wenjie Lv	Coordinate Sizing and Control of the Onboard Pulse Power Supply System.	IEEE Trans. Ind. Electron.	2024	DBLP DOI BibTeX RDF
11	Mohammad Rohaninejad, Behdin Vahedi Nouri, Zdenek Hanzálek, Reza Tavakkoli-Moghaddam	An integrated lot-sizing and scheduling problem in a reconfigurable manufacturing system under workforce constraints.	Int. J. Prod. Res.	2024	DBLP DOI BibTeX RDF
11	Caio Paziani Tomazella, Maristela Oliveira Santos, Douglas José Alem, Raf Jans	Service-level-driven procurement and production lot-sizing problem with demand fulfilment.	Int. J. Prod. Res.	2024	DBLP DOI BibTeX RDF
11	Ruiwen Liao, Céline Gicquel	Integrated lot-sizing and energy supply planning with onsite generation of intermittent renewable energy.	Int. J. Prod. Res.	2024	DBLP DOI BibTeX RDF
11	Kevin A. Bunn, José A. Ventura	Reformulations to improve the Lagrangian relaxation approach for the capacitated multi-product dynamic lot sizing problem with batch ordering.	Int. J. Prod. Res.	2024	DBLP DOI BibTeX RDF
11	Rafael Ajudarte de Campos, Aakil M. Caunhye, Douglas José Alem, Pedro Munari	Fragility-based lot-sizing in veterinary pharmaceutical plants under demand uncertainty.	Int. J. Prod. Res.	2024	DBLP DOI BibTeX RDF
11	Alexandre Honorat, Mickaël Dardaillon, Hugo Miomandre, Jean-François Nezan	Automated Buffer Sizing of Dataflow Applications in a High-level Synthesis Workflow.	ACM Trans. Reconfigurable Technol. Syst.	2024	DBLP DOI BibTeX RDF
11	Yufei Yang, Chenhao Xie 0001, Liansheng Liu, Philip H. W. Leong, Shuaiwen Leon Song	Efficient Radius Search for Adaptive Foveal Sizing Mechanism in Collaborative Foveated Rendering Framework.	IEEE Trans. Mob. Comput.	2024	DBLP DOI BibTeX RDF
11	Diptish Saha, Najmeh Bazmohammadi, Abderezak Lashab, Juan C. Vasquez 0001, Josep M. Guerrero	Power and Energy Management System of a Lunar Microgrid - Part II: Optimal Sizing and Operation of ISRU.	IEEE Trans. Aerosp. Electron. Syst.	2024	DBLP DOI BibTeX RDF