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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 1250 occurrences of 693 keywords
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Results
Found 3867 publication records. Showing 3867 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
15 | Kan-Lin Hsiung |
Design of High-Speed Metal-Semiconductor-Metal Photodetectors: An Optimization-Based Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2006), 17-19 January 2006, Kuala Lumpur, Malaysia, pp. 83-84, 2006, IEEE Computer Society, 0-7695-2500-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Retsef Levi, Martin Pál, Robin Roundy, David B. Shmoys |
Approximation Algorithms for Stochastic Inventory Control Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPCO ![In: Integer Programming and Combinatorial Optimization, 11th International IPCO Conference, Berlin, Germany, June 8-10, 2005, Proceedings, pp. 306-320, 2005, Springer, 3-540-26199-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
15 | Anton Valouev, Lei Li, Yu-Chi Liu, David C. Schwartz, Yi Yang 0047, Yu Zhang 0002, Michael S. Waterman |
Alignment of Optical Maps. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RECOMB ![In: Research in Computational Molecular Biology, 9th Annual International Conference, RECOMB 2005, Cambridge, MA, USA, May 14-18, 2005, Proceedings, pp. 489-504, 2005, Springer, 3-540-25866-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
15 | Jeng-Liang Tsai, Charlie Chung-Ping Chen |
Process-variation robust and low-power zero-skew buffered clock-tree synthesis using projected scan-line sampling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 1168-1171, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
15 | Youngmoon Choi, Earl E. Swartzlander Jr. |
Parallel Prefix Adder Design with Matrix Representation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 17th IEEE Symposium on Computer Arithmetic (ARITH-17 2005), 27-29 June 2005, Cape Cod, MA, USA, pp. 90-98, 2005, IEEE Computer Society, 0-7695-2366-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
15 | Anuradha Agarwal, Ranga Vemuri |
Layout-Aware RF Circuit Synthesis Driven by Worst Case Parasitic Corners. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 23rd International Conference on Computer Design (ICCD 2005), 2-5 October 2005, San Jose, CA, USA, pp. 444-452, 2005, IEEE Computer Society, 0-7695-2451-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
15 | Min Pan, Chris C. N. Chu, J. Morris Chang |
Transition time bounded low-power clock tree construction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 2445-2448, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
15 | Ning Fu, Shigetoshi Nakatake, Yasuhiro Takashima, Yoji Kajitani |
The oct-touched tile: a new architecture for shape-based routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005, pp. 126-129, 2005, ACM, 1-59593-057-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
OTT updated according to the obstacles, shape-based routing, routing architecture |
15 | Daniel Quadt |
A Hierarchical Production Planning Approach for Multiprocessor Flow Shops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
OR ![In: Operations Research Proceedings 2005, Selected Papers of the Annual International Conference of the German Operations Research Society (GOR), Bremen, Germany, September 7-9, 2005, pp. 9-14, 2005, 978-3-540-32537-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
15 | Cliff C. N. Sze, Charles J. Alpert, Jiang Hu, Weiping Shi |
Path based buffer insertion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 509-514, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
layout, physical design, global routing, buffer insertion, power minimization, interconnect synthesis |
15 | Alex Garthwaite, David Dice, Derek White |
Supporting per-processor local-allocation buffers using lightweight user-level preemption notification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VEE ![In: Proceedings of the 1st International Conference on Virtual Execution Environments, VEE 2005, Chicago, IL, USA, June 11-12, 2005, pp. 24-34, 2005, ACM, 1-59593-047-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
restartable critical sections, locality, memory allocation |
15 | Fabricio B. Bastian, Cristiano Lazzari, José Luís Almada Güntzel, Ricardo Reis 0001 |
A New Transistor Folding Algorithm Applied to an Automatic Full-Custom Layout Generation Tool. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation; 14th International Workshop, PATMOS 2004, Santorini, Greece, September 15-17, 2004, Proceedings, pp. 732-741, 2004, Springer, 3-540-23095-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
15 | A. E. Eiben, Elena Marchiori, V. A. Valkó |
Evolutionary Algorithms with On-the-Fly Population Size Adjustment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PPSN ![In: Parallel Problem Solving from Nature - PPSN VIII, 8th International Conference, Birmingham, UK, September 18-22, 2004, Proceedings, pp. 41-50, 2004, Springer, 3-540-23092-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
15 | Chandrasekar Rajagopal, Adrián Núñez-Aldana |
CMOS Analog Programmable Logic Array. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), Emerging Trends in VLSI Systems Design, 19-20 February 2004, Lafayette, LA, USA, pp. 291-292, 2004, IEEE Computer Society, 0-7695-2097-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
15 | Vikas Chandra, Anthony Xu, Herman Schmit, Lawrence T. Pileggi |
An Interconnect Channel Design Methodology for High Performance Integrated Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 1138-1143, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
15 | Changbo Long, Jinjun Xiong, Lei He 0001 |
On optimal physical synthesis of sleep transistors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2004 International Symposium on Physical Design, ISPD 2004, Phoenix, Arizona, USA, April 18-21, 2004, pp. 156-161, 2004, ACM, 1-58113-817-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
physical design, power-gating, sleep transistors |
15 | Adam Engelhart, Mark K. Gardner, Wu-chun Feng |
Re-Architecting Flow Control Adaptation for Grid Environments. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), CD-ROM / Abstracts Proceedings, 26-30 April 2004, Santa Fe, New Mexico, USA, 2004, IEEE Computer Society, 0-7695-2132-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
15 | João Ramos, Kenneth Francken, Georges G. E. Gielen, Michiel Steyaert |
Knowledge- and optimization-based design of RF power amplifiers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2004 International Symposium on Circuits and Systems, ISCAS 2004, Vancouver, BC, Canada, May 23-26, 2004, pp. 629-632, 2004, IEEE, 0-7803-8251-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
15 | Raoul F. Badaoui, Hemanth Sampath, Anuradha Agarwal, Ranga Vemuri |
A high level language for pre-layout extraction in parasite-aware analog circuit synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, Boston, MA, USA, April 26-28, 2004, pp. 271-276, 2004, ACM, 1-58113-853-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
MSL, pre-layout extraction, parasitics, analog VLSI |
15 | Pedro F. Vieira, Leonardo Bruno de Sá, João P. B. Botelho, Antonio Carneiro de Mesquita Filho |
Evolutionary Synthesis of Analog Circuits Using Only MOS Transistors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Evolvable Hardware ![In: 6th NASA / DoD Workshop on Evolvable Hardware (EH 2004), 24-26 June 2004, Seattle, WA, USA, pp. 38-45, 2004, IEEE Computer Society, 0-7695-2145-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
15 | Li-Da Huang, Minghorng Lai, Martin D. F. Wong, Youxin Gao |
Maze routing with buffer insertion under transition time constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(1), pp. 91-95, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
15 | Frederic Cordier, Hyewon Seo, Nadia Magnenat-Thalmann |
Made-to-Measure Technologies for an Online Clothing Store. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Computer Graphics and Applications ![In: IEEE Computer Graphics and Applications 23(1), pp. 38-48, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
15 | Tom Eeckelaert, Walter Daems, Georges G. E. Gielen, Willy M. C. Sansen |
Generalized Posynomial Performance Modeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany, pp. 10250-10255, 2003, IEEE Computer Society, 0-7695-1870-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
15 | Jennifer Y.-L. Lo, Wu-An Kuo, Allen C.-H. Wu, TingTing Hwang |
A Custom-Cell Identification Method for High-Performance Mixed Standard/Custom-Cell Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany, pp. 11102-11103, 2003, IEEE Computer Society, 0-7695-1870-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
15 | Will Casey, Bud Mishra |
A Nearly Linear-Time General Algorithm for Genome-Wide Bi-allele Haplotype Phasing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPC ![In: High Performance Computing - HiPC 2003, 10th International Conference, Hyderabad, India, December 17-20, 2003, Proceedings, pp. 204-215, 2003, Springer, 3-540-20626-4. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
15 | Soroush Abbaspour, Massoud Pedram, Payam Heydari |
Optimizing the Energy-Delay-Ringing Product in On-Chip CMOS Line Drivers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 4th International Symposium on Quality of Electronic Design (ISQED 2003), 24-26 March 2003, San Jose, CA, USA, pp. 261-266, 2003, IEEE Computer Society, 0-7695-1881-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
15 | Vani Prasad, Madhav P. Desai |
Interconnect Delay Minimization Using a Novel Pre-Mid-Post Buffer Strategy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 16th International Conference on VLSI Design (VLSI Design 2003), 4-8 January 2003, New Delhi, India, pp. 417-422, 2003, IEEE Computer Society, 0-7695-1868-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
15 | Li-Da Huang, Minghorng Lai, D. F. Wong 0001, Youxin Gao |
Maze Routing with Buffer Insertion under Transition Time Constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2002 Design, Automation and Test in Europe Conference and Exposition (DATE 2002), 4-8 March 2002, Paris, France, pp. 702-707, 2002, IEEE Computer Society, 0-7695-1471-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
15 | Murat R. Becer, Vladimir Zolotov, David T. Blaauw, Rajendran Panda, Ibrahim N. Hajj |
Analysis of Noise Avoidance Techniques in DSM Interconnects Using a Complete Crosstalk Noise Model . ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2002 Design, Automation and Test in Europe Conference and Exposition (DATE 2002), 4-8 March 2002, Paris, France, pp. 456-463, 2002, IEEE Computer Society, 0-7695-1471-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
15 | Wei Chen, Massoud Pedram, Premal Buch |
Buffered Routing Tree Construction under Buffer Placement Blockages. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 381-386, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Blockage, Routing, Buffer |
15 | Sunil Rafeeque |
Area efficient current steering DAC using current tuning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS (1) ![In: IEEE Asia Pacific Conference on Circuits and Systems 2002, APCCAS 2002, Singapore, 16-18 December 2002, pp. 559-564, 2002, IEEE, 0-7803-7690-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
15 | Yu-Yen Mo, Chris C. N. Chu |
Hybrid dynamic/quadratic programming algorithm for interconnecttree optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(5), pp. 680-686, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
15 | Geert Van der Plas, Geert Debyser, Francky Leyn, Koen Lampaert, Jan Vandenbussche, Georges G. E. Gielen, Willy M. C. Sansen, Petar Veselinovic, Domine Leenaerts |
AMGIE-A synthesis environment for CMOS analog integrated circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(9), pp. 1037-1058, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
15 | Te-Kai Liu, Santhosh Kumaran, Zongwei Luo |
Layered Queueing Models for Enterprise JavaBean Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EDOC ![In: 5th International Enterprise Distributed Object Computing Conference (EDOC 2001), 4-7 September 2001, Seattle, WA, USA, Proceedings, pp. 174-178, 2001, IEEE Computer Society, 0-7695-1345-X. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
15 | Jiang Hu, Sachin S. Sapatnekar |
Algorithms for non-Hanan-based optimization for VLSI interconnectunder a higher-order AWE model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(4), pp. 446-458, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
15 | Forrest H. Bennett III, John R. Koza, Jessen Yu, William Mydlowec |
Automatic Synthesis, Placement, and Routing of an Amplifier Circuit by Means of Genetic Programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICES ![In: Evolvable Systems: From Biology to Hardware, Third International Conference, ICES 2000, Edinburgh, Scotland, UK, April 17-19, 2000, Proceedings, pp. 1-10, 2000, Springer, 3-540-67338-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
15 | Mohamed Dessouky, Marie-Minerve Louërat |
A Layout Approach for Electrical and Physical Design Integration of High-Performance Analog Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 1st International Symposium on Quality of Electronic Design (ISQED 2000), 20-22 March 2000, San Jose, CA, USA, pp. 291-298, 2000, IEEE Computer Society, 0-7695-0525-2. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Analog layout, layout generation |
15 | Ingmar Neumann, Dominik Stoffel, Hendrik Hartje, Wolfgang Kunz |
Cell replication and redundancy elimination during placement for cycle time optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999, San Jose, California, USA, November 7-11, 1999, pp. 25-30, 1999, IEEE Computer Society, 0-7803-5832-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
15 | Kenneth Francken, Georges G. E. Gielen |
Methodology for analog technology porting including performance tuning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 415-418, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
15 | Josef Eckmüller, Martin Groepl, Helmut E. Graeb |
Hierarchical Characterization of Analog Integrated CMOS Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 636-643, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
hierarchical characterization, circuit class, topology independent, transistor pairs, circuit performances, functional constraints |
15 | Jason Cong, Lei He 0001 |
An efficient technique for device and interconnect optimization in deep submicron designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 1998 International Symposium on Physical Design, ISPD 1998, Monterey, CA, USA, April 6-8, 1998, pp. 45-51, 1998, ACM, 1-58113-021-X. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
15 | K. Ravi Shanker, Vinita Vasudevan |
Synthesis of Analog CMOS Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 10th International Conference on VLSI Design (VLSI Design 1997), 4-7 January 1997, Hyderabad, India, pp. 439-445, 1997, IEEE Computer Society, 0-8186-7755-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
synthesis, analog circuits |
15 | Chia-Chun Tsai, De-Yu Kao, Chung-Kuan Cheng |
Performance driven bus buffer insertion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(4), pp. 429-437, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
15 | Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin |
Power-delay characteristics of CMOS adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 2(3), pp. 377-381, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
15 | Weitong Chuang, Ibrahim N. Hajj |
Delay and area optimization for compact placement by gate resizing and relocation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1994, San Jose, California, USA, November 6-10, 1994, pp. 145-148, 1994, IEEE Computer Society / ACM, 0-89791-690-5. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
15 | Uwe Hinsberger, Reiner Kolla |
A cell-based approach to performance optimization of fanout-free circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(10), pp. 1317-1322, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
15 | Mark Hofmann, Jae K. Kim |
Delay Optimization of Combinational Static CMOS Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28 - July 1, 1987., pp. 125-132, 1987, IEEE Computer Society Press / ACM. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
14 | Jonathan F. Bard, Narameth Nananukul |
The integrated production-inventory-distribution-routing problem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Sched. ![In: J. Sched. 12(3), pp. 257-280, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Allocation model, Tabu search, Vehicle routing problem, Inventory, Production planning, Lot-sizing |
14 | Julien Dardenne, Sébastien Valette, Nicolas Siauve, Noël Burais, Rémy Prost |
Variational tetrahedral mesh generation from discrete volume data. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Vis. Comput. ![In: Vis. Comput. 25(5-7), pp. 401-410, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Discrete data, Centroidal Voronoi Diagrams, Sizing field, Tetrahedral meshing |
14 | Jianwei Niu 0003, Zhizhong Li 0003, Song Xu |
Block Division for 3D Head Shape Clustering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HCI (11) ![In: Digital Human Modeling, Second International Conference, ICDHM 2009, Held as Part of HCI International 2009, San Diego, CA, USA, July 19-24, 2009. Proceedings, pp. 64-71, 2009, Springer, 978-3-642-02808-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Three dimensional anthropometry, block-division, clustering, sizing |
14 | Kaushik Roy 0001, Jaydeep P. Kulkarni, Sumeet Kumar Gupta |
Device/circuit interactions at 22nm technology node. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 97-102, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
22 nm technology node, DG MOSFETs, scaling, SRAM, transistor sizing, FinFETs |
14 | André L. V. Coelho, Daniel G. de Oliveira |
Dynamically tuning the population size in particle swarm optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAC ![In: Proceedings of the 2008 ACM Symposium on Applied Computing (SAC), Fortaleza, Ceara, Brazil, March 16-20, 2008, pp. 1782-1787, 2008, ACM, 978-1-59593-753-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
numerical optimization, population sizing, parameter control |
14 | Rosane Maria Maffei Vallim, David E. Goldberg, Xavier Llorà, Thyago S. P. C. Duque, André C. P. L. F. de Carvalho |
A new approach for multi-label classification based on default hierarchies and organizational learning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GECCO (Companion) ![In: Genetic and Evolutionary Computation Conference, GECCO 2008, Proceedings, Atlanta, GA, USA, July 12-16, 2008, Companion Material, pp. 2017-2022, 2008, ACM, 978-1-60558-131-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
default hierarchies, organizational sizing, LCS |
14 | Bill Stackpole |
The evolution of a virtualized laboratory environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGITE Conference ![In: Proceedings of the 9th Conference on Information Technology Education, SIGITE 2008, Cincinnati, OH, USA, October 16-18, 2008, pp. 243-248, 2008, ACM, 978-1-60558-329-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
curricular issues, laboratory environments, system sizing and benchmarking, networking, virtualization, distance learning, it education |
14 | Robert Shorten, Douglas J. Leith |
On queue provisioning, network efficiency and the transmission control protocol. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE/ACM Trans. Netw. ![In: IEEE/ACM Trans. Netw. 15(4), pp. 866-877, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
TCP, TCP/IP, buffer sizing, AIMD |
14 | Jeegar Tilak Shah, Marius Evers, Jeff Trull, Alper Halbutogullari |
Circuit optimization for leakage power reduction using multi-threshold voltages for high performance microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2007 International Symposium on Physical Design, ISPD 2007, Austin, Texas, USA, March 18-21, 2007, pp. 67-74, 2007, ACM, 978-1-59593-613-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
multi-VTH, optimization, timing, low-power design, microprocessor, EDA, leakage power, sizing |
14 | Kumara Sastry, David E. Goldberg, Xavier Llorà |
Towards billion-bit optimization via a parallel estimation of distribution algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GECCO ![In: Genetic and Evolutionary Computation Conference, GECCO 2007, Proceedings, London, England, UK, July 7-11, 2007, pp. 577-584, 2007, ACM, 978-1-59593-697-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
billion-variable optimization, parallelization, vectorization, population sizing, large-scale optimization, efficiency enhancement, convergence time, scalability analysis, compact genetic algorithm |
14 | Kumara Sastry, Martin Pelikan, David E. Goldberg |
Empirical analysis of ideal recombination on random decomposable problems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GECCO ![In: Genetic and Evolutionary Computation Conference, GECCO 2007, Proceedings, London, England, UK, July 7-11, 2007, pp. 1388-1395, 2007, ACM, 978-1-59593-697-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
additively-decomposable problems, ideal crossover, genetic algorithms, building blocks, empirical analysis, population sizing, convergence time, problem difficulty, test problems, scalability analysis |
14 | Chengliang Zhang, Kirk Kelsey, Xipeng Shen, Chen Ding 0001, Matthew Hertz, Mitsunori Ogihara |
Program-level adaptive memory management. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMM ![In: Proceedings of the 5th International Symposium on Memory Management, ISMM 2006, Ottawa, Ontario, Canada, June 10-11, 2006, pp. 174-183, 2006, ACM, 1-59593-221-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
heap sizing, program-level, adaptive, garbage collection, paging |
14 | Kumara Sastry, D. D. Johnson, Alexis L. Thompson, David E. Goldberg, Todd J. Martínez, Jeff Leiding, Jane Owens |
Multiobjective genetic algorithms for multiscaling excited state direct dynamics in photochemistry. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GECCO ![In: Genetic and Evolutionary Computation Conference, GECCO 2006, Proceedings, Seattle, Washington, USA, July 8-12, 2006, pp. 1745-1752, 2006, ACM, 1-59593-186-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
multiobjective genetic algorithms, non-domination, photochemistry, semiempirical methods, niching, population sizing, NSGA-II, convergence time, multiscale modeling |
14 | Alan Piszcz, Terence Soule |
Genetic programming: optimal population sizes for varying complexity problems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GECCO ![In: Genetic and Evolutionary Computation Conference, GECCO 2006, Proceedings, Seattle, Washington, USA, July 8-12, 2006, pp. 953-954, 2006, ACM, 1-59593-186-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
MAX binary tree problem, binomial-3, optimal, population sizing, problem difficulty |
14 | Sherif Hammouda, Hazem Said, Mohamed Dessouky, Mohamed Tawfik, Quang Nguyen, Wael M. Badawy, Hazem M. Abbas, Hussein I. Shahein |
Chameleon ART: a non-optimization based analog design migration framework. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 885-888, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
analog reuse, design extraction, layout compaction, layout retargeting, circuit sizing |
14 | Ming-Jong Yao |
The Economic Lot Scheduling Problem without Capacity Constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Ann. Oper. Res. ![In: Ann. Oper. Res. 133(1-4), pp. 193-205, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
scheduling, production, search algorithm, inventory, lot sizing |
14 | Pierre Alliez, David Cohen-Steiner, Mariette Yvinec, Mathieu Desbrun |
Variational tetrahedral meshing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Graph. ![In: ACM Trans. Graph. 24(3), pp. 617-625, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
delaunay mesh, isotropic meshing, sizing field, slivers |
14 | Anuradha Agarwal, Glenn Wolfe, Ranga Vemuri |
Accuracy driven performance macromodeling of feasible regions during synthesis of analog circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005, pp. 482-487, 2005, ACM, 1-59593-057-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
performance modeling, circuit sizing, analog synthesis |
14 | Huan-Yun Wei, Shih-Chiang Tsao, Ying-Dar Jason Lin |
Assessing and Improving TCP Rate Shaping over Edge Gateways. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 53(3), pp. 259-275, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
rate enforcement, ACK-pacing, scheduling, TCP, testbed, packet scheduler, queuing, Bandwidth management, window-sizing |
14 | Peter-Michael Seidel, Guy Even |
Delay-Optimized Implementation of IEEE Floating-Point Addition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 53(2), pp. 97-113, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
IEEE rounding, dual path algorithm, optimized gate sizing, buffer insertion, delay optimization, logical effort, Floating-point addition |
14 | Gang Zhang, E. Aykut Dengi, Ronald A. Rohrer, Rob A. Rutenbar, L. Richard Carley |
A synthesis flow toward fast parasitic closure for radio-frequency integrated circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 155-158, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
modeling, synthesis, layout, sizing, parasitic, radio frequency |
14 | Te-Kai Liu, Amir Behroozi, Santhosh Kumaran |
A performance model for a BPI middleware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EC ![In: Proceedings 4th ACM Conference on Electronic Commerce (EC-2003), San Diego, California, USA, June 9-12, 2003, pp. 222-223, 2003, ACM, 1-58113-679-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
business process integration middleware, capacity sizing, e-commerce workload, layered queueing model, synchronous and asynchronous requests, thread pool tuning, benchmark, performance modeling |
14 | Sergio F. Ochoa, M. Cecilia Bastarrica, Germán Parra |
Estimating the Development Effort of Web Projects in Chile. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LA-WEB ![In: 1st Latin American Web Congress (LA-WEB 2003), Empowering Our Web, 10-12 November 2003, Sanitago, Chile, pp. 114-122, 2003, IEEE Computer Society, 0-7695-2058-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Effort Estimation Method, Sizing Metric, Web Engineering, Web-based Information Systems |
14 | Stephen P. Boyd, Lieven Vandenberghe, Abbas El Gamal, Sunghee Yun |
Design of robust global power and ground networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2001 International Symposium on Physical Design, ISPD 2001, Sonoma County, CA, USA, April 1-4, 2001, pp. 60-65, 2001, ACM, 1-58113-347-2. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
interconnect sizing, power and ground network design, convex optimization |
14 | Shiyou Zhao, Kaushik Roy 0001, Cheng-Kok Koh |
Decoupling capacitance allocation for power supply noise suppression. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2001 International Symposium on Physical Design, ISPD 2001, Sonoma County, CA, USA, April 1-4, 2001, pp. 66-71, 2001, ACM, 1-58113-347-2. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
interconnect sizing, power and ground network design, convex optimization |
14 | Laurence D. Merkle, George H. Gates Jr., Gary B. Lamont |
Scalability of an MPI-based fast messy genetic algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAC ![In: Proceedings of the 1998 ACM symposium on Applied Computing, SAC'98, Atlanta, GA, USA, February 27 - March 1, 1998, pp. 386-393, 1998, ACM, 0-89791-969-6. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
fixed solution quality, messy genetic algorithms, polypeptide structure prediction, parallel genetic algorithms, population sizing |
14 | Michael Orshansky, James C. Chen, Chenming Hu |
A Statistical Performance Simulation Methodology for VLSI Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 402-407, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
migration, timing optimazation, custom sizing |
14 | Jason Cong, Patrick H. Madden |
Performance Driven Multi-Layer General Area Routing for PCB/MCM Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 356-361, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
logic synthesis, gate-sizing, fanout optimization |
14 | Al Dunlop, Alper Demir 0001, Peter Feldmann, Sharad Kapur, David E. Long, Robert C. Melville, Jaijeet S. Roychowdhury |
Tools and Methodology for RF IC Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 414-420, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
migration, timing optimazation, custom sizing |
14 | Hsiao-Ping Tseng, Louis Scheffer, Carl Sechen |
Timing and Crosstalk Driven Area Routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 378-381, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
logic synthesis, gate-sizing, fanout optimization |
14 | Bogdan G. Arsintescu, Edoardo Charbon, Enrico Malavasi, Umakanta Choudhury, William H. Kao |
General AC Constraint Transformation for Analog ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 38-43, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
logic synthesis, gate-sizing, fanout optimization |
14 | David S. Kung 0001 |
A Fast Fanout Optimization Algorithm for Near-Continuous Buffer Libraries. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 352-355, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
logic synthesis, gate-sizing, fanout optimization |
14 | Behzad Razavi |
RF IC Design Challenges. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 408-413, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
migration, timing optimazation, custom sizing |
14 | Charles J. Alpert, Anirudh Devgan, Stephen T. Quay |
Buffer Insertion for Noise and Delay Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 362-367, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
logic synthesis, gate-sizing, fanout optimization |
14 | Rajendran Panda, Abhijit Dharchoudhury, Tim Edwards, Joe Norton, David T. Blaauw |
Migration: A New Technique to Improve Synthesized Designs Through Incremental Customization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 388-391, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
migration, timing optimazation, custom sizing |
14 | Julian Culetu, Chaim Amir, John MacDonald |
A Practical Repeater Insertion Method in High Speed VLSI Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 392-395, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
migration, timing optimazation, custom sizing |
14 | Frank Y. Yuan |
Electromagnetic Modeling and Signal Integrity Simulation of Power/Ground Networks in High Speed Digital Packages and Printed Circuit Boards. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 421-426, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
migration, timing optimazation, custom sizing |
14 | Hai Zhou 0001, D. F. Wong 0001 |
Global Routing with Crosstalk Constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 374-377, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
logic synthesis, gate-sizing, fanout optimization |
14 | Arun N. Lokanathan, Jay B. Brockman |
Process Multi-Circuit Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 382-387, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
logic synthesis, gate-sizing, fanout optimization |
14 | Paolo Ienne, Alexander Grießing |
Practical Experiences with Standard-Cell Based Datapath Design Tools: Do We Really Need Regular Layouts? ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 396-401, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
migration, timing optimazation, custom sizing |
14 | Atsushi Takahashi 0001, Kazunori Inoue, Yoji Kajitani |
Clock-tree routing realizing a clock-schedule for semi-synchronous circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1997, San Jose, CA, USA, November 9-13, 1997, pp. 260-265, 1997, IEEE Computer Society / ACM, 0-8186-8200-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
clock-tree routing, semi-synchronous, deferred-merge-embedding (DME), synchronous, buffer insertion, buffer sizing, clock-schedule |
14 | Martin Zauner |
CASE - Computer-Aided Systems Engineering, a New Approach for Developing IM-Systems with Special Consideration of CIM Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROCAST ![In: Computer Aided Systems Theory - EUROCAST'93, A Selection of Papers from the Third International Workshop on Computer Aided Systems Theory, Las Palmas, Spain, February 22-26, 1993, Proceedings, pp. 406-417, 1993, Springer, 3-540-57601-0. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
active database management systems, client/server concepts, CIM concept, IM concepts, right-sizing, prototyping, open systems, RDBMS |
14 | Robert G. Arnold, Robert O. Berg, James W. Thomas |
A Modular Approach to Real-Time Supersystems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 31(5), pp. 385-398, 1982. The full citation details ...](Pics/full.jpeg) |
1982 |
DBLP DOI BibTeX RDF |
real-time embedded computers, Architectural building blocks, data driven software structure, example system sizing, memory/processor tradeoff, distributed computing, high performance, expandable, high throughput, architecture optimization |
11 | Abdelaziz Lberni, Malika Alami Marktani, Abdelaziz Ahaitouf, Ali Ahaitouf |
Analog circuit sizing based on Evolutionary Algorithms and deep learning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Expert Syst. Appl. ![In: Expert Syst. Appl. 237(Part B), pp. 121480, March 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
11 | Wenjie Ao, Jiawei Chen 0002, Wenjie Lv |
Coordinate Sizing and Control of the Onboard Pulse Power Supply System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Ind. Electron. ![In: IEEE Trans. Ind. Electron. 71(8), pp. 9034-9043, August 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
11 | Mohammad Rohaninejad, Behdin Vahedi Nouri, Zdenek Hanzálek, Reza Tavakkoli-Moghaddam |
An integrated lot-sizing and scheduling problem in a reconfigurable manufacturing system under workforce constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Prod. Res. ![In: Int. J. Prod. Res. 62(11), pp. 3994-4013, 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
11 | Caio Paziani Tomazella, Maristela Oliveira Santos, Douglas José Alem, Raf Jans |
Service-level-driven procurement and production lot-sizing problem with demand fulfilment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Prod. Res. ![In: Int. J. Prod. Res. 62(6), pp. 1977-1998, March 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
11 | Ruiwen Liao, Céline Gicquel |
Integrated lot-sizing and energy supply planning with onsite generation of intermittent renewable energy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Prod. Res. ![In: Int. J. Prod. Res. 62(10), pp. 3483-3503, 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
11 | Kevin A. Bunn, José A. Ventura |
Reformulations to improve the Lagrangian relaxation approach for the capacitated multi-product dynamic lot sizing problem with batch ordering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Prod. Res. ![In: Int. J. Prod. Res. 62(8), pp. 2868-2887, 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
11 | Rafael Ajudarte de Campos, Aakil M. Caunhye, Douglas José Alem, Pedro Munari |
Fragility-based lot-sizing in veterinary pharmaceutical plants under demand uncertainty. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Prod. Res. ![In: Int. J. Prod. Res. 62(10), pp. 3716-3752, 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
11 | Alexandre Honorat, Mickaël Dardaillon, Hugo Miomandre, Jean-François Nezan |
Automated Buffer Sizing of Dataflow Applications in a High-level Synthesis Workflow. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Reconfigurable Technol. Syst. ![In: ACM Trans. Reconfigurable Technol. Syst. 17(1), pp. 8:1-8:26, March 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
11 | Yufei Yang, Chenhao Xie 0001, Liansheng Liu, Philip H. W. Leong, Shuaiwen Leon Song |
Efficient Radius Search for Adaptive Foveal Sizing Mechanism in Collaborative Foveated Rendering Framework. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Mob. Comput. ![In: IEEE Trans. Mob. Comput. 23(5), pp. 3620-3632, May 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
11 | Diptish Saha, Najmeh Bazmohammadi, Abderezak Lashab, Juan C. Vasquez 0001, Josep M. Guerrero |
Power and Energy Management System of a Lunar Microgrid - Part II: Optimal Sizing and Operation of ISRU. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Aerosp. Electron. Syst. ![In: IEEE Trans. Aerosp. Electron. Syst. 60(2), pp. 1376-1385, 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
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