Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
23 | Christophe Alexandre, Marek Sroka, Hugo Clément, Christian Masson |
Zephyr: A Static Timing Analyzer Integrated in a Trans-hierarchical Refinement Design Flow. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006, Proceedings, pp. 319-328, 2006, Springer, 3-540-39094-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
23 | Daniel Lima Ferrão, Ricardo Reis 0001, José Luís Almada Güntzel |
Considering Zero-Arrival Time and Block-Arrival Time in Hierarchical Functional Timing Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006, Proceedings, pp. 301-310, 2006, Springer, 3-540-39094-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
23 | Eduardo Tavares, Raimundo S. Barreto, Paulo Romero Martins Maciel, Meuse N. Oliveira Jr., Adilson Arcoverde, Gabriel Alves, Ricardo Massa Ferreira Lima, Leonardo Barros, Arthur Bessa |
An Integrated Environment for Embedded Hard Real-Time Systems Scheduling with Timing and Energy Constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation, 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005, Proceedings, pp. 382-392, 2005, Springer, 3-540-29013-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
23 | Nick Kanopoulos |
Design Methodology for Rapid Development of SoC ICs Based on an Innovative System Architecture with Emphasis to Timing Closure and Power Consumption Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation; 14th International Workshop, PATMOS 2004, Santorini, Greece, September 15-17, 2004, Proceedings, pp. 2, 2004, Springer, 3-540-23095-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
23 | Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang |
Timing constraints for domino logic gates with timing-dependent keepers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(1), pp. 96-103, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
23 | Tod Amon, Gaetano Borriello, Taokuan Hu, Jiwen Liu |
Symbolic Timing Verification of Timing Diagrams using Presburger Formulas. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 34st Conference on Design Automation, Anaheim, California, USA, Anaheim Convention Center, June 9-13, 1997., pp. 226-231, 1997, ACM Press, 0-89791-920-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
23 | Jin-Tai Yan, Zhi-Wei Chen |
Resource-constrained timing-driven link insertion for critical delay reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010, pp. 119-122, 2010, ACM, 978-1-4503-0012-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
critical delay, link insertion, non-tree |
23 | Lin Xie, Azadeh Davoodi |
Representative path selection for post-silicon timing prediction under variability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 386-391, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
process variations, post-silicon validation |
23 | Takashi Enami, Shinyu Ninomiya, Masanori Hashimoto |
Statistical Timing Analysis Considering Spatially and Temporally Correlated Dynamic Power Supply Noise. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(4), pp. 541-553, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
23 | Minxue Pan, Lei Bu, Xuandong Li |
TASS: Timing Analyzer of Scenario-Based Specifications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 21st International Conference, CAV 2009, Grenoble, France, June 26 - July 2, 2009. Proceedings, pp. 689-695, 2009, Springer, 978-3-642-02657-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
23 | HaNeul Chon, Taewhan Kim |
Timing variation-aware task scheduling and binding for MPSoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009, pp. 137-142, 2009, IEEE, 978-1-4244-2748-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
23 | Yi Wang, Ping Chen 0003, Yi Ge, Bing Mao, Li Xie 0001 |
Traffic Controller: A Practical Approach to Block Network Covert Timing Channel. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARES ![In: Proceedings of the The Forth International Conference on Availability, Reliability and Security, ARES 2009, March 16-19, 2009, Fukuoka, Japan, pp. 349-354, 2009, IEEE Computer Society, 978-1-4244-3572-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
23 | Yunchuan Guo, Lihua Yin, Yuan Zhou, Chao Li 0027, Li Guo 0001 |
Simulation Analysis of Probabilistic Timing Covert Channels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NAS ![In: International Conference on Networking, Architecture, and Storage, NAS 2009, 9-11 July 2009, Zhang Jia Jie, Hunan, China, pp. 325-332, 2009, IEEE Computer Society, 978-0-7695-3741-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
23 | Menguc Oner |
On the effects of random timing jitter on spectrum sensing algorithms based on cyclostationarity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCECE ![In: Proceedings of the 22nd Canadian Conference on Electrical and Computer Engineering, CCECE 2009, 3-6 May 2009, Delta St. John's Hotel and Conference Centre, St. John's, Newfoundland, Canada, pp. 213-218, 2009, IEEE, 978-1-4244-3508-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
23 | Bart Coppens 0001, Ingrid Verbauwhede, Koen De Bosschere, Bjorn De Sutter |
Practical Mitigations for Timing-Based Side-Channel Attacks on Modern x86 Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SP ![In: 30th IEEE Symposium on Security and Privacy (SP 2009), 17-20 May 2009, Oakland, California, USA, pp. 45-60, 2009, IEEE Computer Society, 978-0-7695-3633-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
23 | Ramamurthy Vishweshwara, Ramakrishnan Venkatraman, H. Udayakumar, N. V. Arvind |
An Approach to Measure the Performance Impact of Dynamic Voltage Fluctuations Using Static Timing Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2009: Improving Productivity through Higher Abstraction, The 22nd International Conference on VLSI Design, New Delhi, India, 5-9 January 2009, pp. 519-524, 2009, IEEE Computer Society, 978-0-7695-3506-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
23 | Jinjun Xiong, Chandu Visweswariah, Vladimir Zolotov |
Statistical ordering of correlated timing quantities and its application for path ranking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 122-125, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
path ranking, statistical ordering, testing, correlation |
23 | Lin Wu, Vincenzo Lottici, Zhi Tian |
Maximum Likelihood Multiple Access Timing Synchronization for UWB Communications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Wirel. Commun. ![In: IEEE Trans. Wirel. Commun. 7(11-2), pp. 4497-4501, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
23 | Ruiming Chen, Hai Zhou 0001 |
Fast Estimation of Timing Yield Bounds for Process Variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(3), pp. 241-248, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
23 | Sari Onaissi, Farid N. Najm |
A Linear-Time Approach for Static Timing Analysis Covering All Process Corners. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(7), pp. 1291-1304, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
23 | Vamsi Vankamamidi, Marco Ottavi, Fabrizio Lombardi |
Two-Dimensional Schemes for Clocking/Timing of QCA Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(1), pp. 34-44, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
23 | Kotipalli Pushpa, Chavali Nanda Kishore, Yeleswarapu Yoganandam |
Comparative study of four modified timing metrics for the frame synchronization in OFDMA mode of WMAN. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PIMRC ![In: Proceedings of the IEEE 19th International Symposium on Personal, Indoor and Mobile Radio Communications, PIMRC 2008, 15-18 September 2008, Cannes, French Riviera, France, pp. 1-5, 2008, IEEE. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
23 | Xiapu Luo, Edmond W. W. Chan, Rocky K. C. Chang |
TCP covert timing channels: Design and detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSN ![In: The 38th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, DSN 2008, June 24-27, 2008, Anchorage, Alaska, USA, Proceedings, pp. 420-429, 2008, IEEE Computer Society, 978-1-4244-2397-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
23 | Sean X. Shi, Anand Ramalingam, Daifeng Wang, David Z. Pan |
Latch Modeling for Statistical Timing Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 1136-1141, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
23 | Raman Venkataramani, Mehmet Fatih Erden |
MAP-Based Timing Recovery for Magnetic Recording. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICC ![In: Proceedings of IEEE International Conference on Communications, ICC 2008, Beijing, China, 19-23 May 2008, pp. 1982-1985, 2008, IEEE. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
23 | Rajeshwary Tayade, Sani R. Nassif, Jacob A. Abraham |
Analytical model for the impact of multiple input switching noise on timing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 13th Asia South Pacific Design Automation Conference, ASP-DAC 2008, Seoul, Korea, January 21-24, 2008, pp. 514-517, 2008, IEEE, 978-1-4244-1921-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
23 | Khaled R. Heloue, Sari Onaissi, Farid N. Najm |
Efficient block-based parameterized timing analysis covering all potentially critical paths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2008 International Conference on Computer-Aided Design, ICCAD 2008, San Jose, CA, USA, November 10-13, 2008, pp. 173-180, 2008, IEEE Computer Society, 978-1-4244-2820-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
23 | Javid Jaffari, Mohab Anis |
On efficient Monte Carlo-based statistical static timing analysis of digital circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2008 International Conference on Computer-Aided Design, ICCAD 2008, San Jose, CA, USA, November 10-13, 2008, pp. 196-203, 2008, IEEE Computer Society, 978-1-4244-2820-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
23 | Shiyan Hu, Zhuo Li 0001, Charles J. Alpert |
A polynomial time approximation scheme for timing constrained minimum cost layer assignment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2008 International Conference on Computer-Aided Design, ICCAD 2008, San Jose, CA, USA, November 10-13, 2008, pp. 112-115, 2008, IEEE Computer Society, 978-1-4244-2820-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
23 | Veerapaneni Nagbhushan, C. Y. Roger Chen |
Modeling and reduction of complex timing constraints in high performance digital circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 26th International Conference on Computer Design, ICCD 2008, 12-15 October 2008, Lake Tahoe, CA, USA, Proceedings, pp. 544-550, 2008, IEEE Computer Society, 978-1-4244-2657-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
23 | Anuj Kumar, Tai-Hsuan Wu, Azadeh Davoodi |
SynECO: Incremental technology mapping with constrained placement and fast detail routing for predictable timing improvement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 26th International Conference on Computer Design, ICCD 2008, 12-15 October 2008, Lake Tahoe, CA, USA, Proceedings, pp. 551-556, 2008, IEEE Computer Society, 978-1-4244-2657-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
23 | Hatim Daginawala, Matthew K. Wright |
Studying Timing Analysis on the Internet with SubRosa. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Privacy Enhancing Technologies ![In: Privacy Enhancing Technologies, 8th International Symposium, PETS 2008, Leuven, Belgium, July 23-25, 2008, Proceedings, pp. 133-150, 2008, Springer, 978-3-540-70629-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
23 | Yongjian Tang, Hans Hegt, Arthur H. M. van Roermund |
Predictive timing error calibration technique for RF current-steering DACs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 228-231, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
23 | Johannes Partzsch, Christian Mayr 0001, René Schüffny |
BCM and Membrane Potential: Alternative Ways to Timing Dependent Plasticity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICONIP (1) ![In: Advances in Neuro-Information Processing, 15th International Conference, ICONIP 2008, Auckland, New Zealand, November 25-28, 2008, Revised Selected Papers, Part I, pp. 137-144, 2008, Springer, 978-3-642-02489-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
23 | Shiyan Hu, Qiuyang Li, Jiang Hu, Peng Li 0001 |
Utilizing Redundancy for Timing Critical Interconnect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(10), pp. 1067-1080, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
23 | Farid N. Najm, Noel Menezes, Imad A. Ferzli |
A Yield Model for Integrated Circuits and its Application to Statistical Timing Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(3), pp. 574-591, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
23 | Rutuparna Tamhankar, Srinivasan Murali, Stergios Stergiou, Antonio Pullini, Federico Angiolini, Luca Benini, Giovanni De Micheli |
Timing-Error-Tolerant Network-on-Chip Design Methodology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(7), pp. 1297-1310, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
23 | Puneet Gupta 0001, Andrew B. Kahng, Youngmin Kim, Dennis Sylvester |
Self-Compensating Design for Reduction of Timing and Leakage Sensitivity to Systematic Pattern-Dependent Variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(9), pp. 1614-1624, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
23 | Desta Tadesse, D. Sheffield, E. Lenge, R. Iris Bahar, Joel Grodstein |
Accurate timing analysis using SAT and pattern-dependent delay models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 1018-1023, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
23 | Jing Xu, Wensheng Yu, Jian-Qiang Yi, Zhishou Tu |
Traffic Signal Timing with Neural Dynamic Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISNN (1) ![In: Advances in Neural Networks - ISNN 2007, 4th International Symposium on Neural Networks, ISNN 2007, Nanjing, China, June 3-7, 2007, Proceedings, Part I, pp. 358-367, 2007, Springer, 978-3-540-72382-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
23 | Daniel Parthey, Robert Baumgartl |
Analyzing Access Timing of Removable Flash Media. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTCSA ![In: 13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2007), 21-24 August 2007, Daegu, Korea, pp. 510-515, 2007, IEEE Computer Society, 0-7695-2975-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
23 | Michael Ward, Neil C. Audsley |
A Deterministic Implementation Process for Accurate and Traceable System Timing and Space Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTCSA ![In: 13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2007), 21-24 August 2007, Daegu, Korea, pp. 432-440, 2007, IEEE Computer Society, 0-7695-2975-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
23 | Jongyoon Jung, Taewhan Kim |
Timing variation-aware high-level synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2007 International Conference on Computer-Aided Design, ICCAD 2007, San Jose, CA, USA, November 5-8, 2007, pp. 424-428, 2007, IEEE Computer Society, 1-4244-1382-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
23 | Yen-Pin Chen, Jia-Wei Fang, Yao-Wen Chang |
ECO timing optimization using spare cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2007 International Conference on Computer-Aided Design, ICCAD 2007, San Jose, CA, USA, November 5-8, 2007, pp. 530-535, 2007, IEEE Computer Society, 1-4244-1382-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
23 | Veerapaneni Nagbhushan, C. Y. Roger Chen |
Algorithms to simplify multi-clock/edge timing constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 25th International Conference on Computer Design, ICCD 2007, 7-10 October 2007, Lake Tahoe, CA, USA, Proceedings, pp. 444-449, 2007, IEEE, 1-4244-1258-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
23 | Dylan Stark, Gabrielle Allen, Tom Goodale, Thomas Radke, Erik Schnetter |
An Extensible Timing Infrastructure for Adaptive Large-Scale Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PPAM ![In: Parallel Processing and Applied Mathematics, 7th International Conference, PPAM 2007, Gdansk, Poland, September 9-12, 2007, Revised Selected Papers, pp. 1170-1179, 2007, Springer, 978-3-540-68105-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
23 | Tadesse Ghirmai |
Data Detection and Fixed Symbol-Timing Estimation in Flat Fading Channels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CISS ![In: Proceedings of the 41st Annual Conference on Information Sciences and Systems, CISS 2007, 14-16 March 2007, Johns Hopkins University, Department of Electrical Engineering, Baltimore, MD, USA, pp. 456-461, 2007, IEEE, 1-4244-1037-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
23 | Harry I. A. Chen, Edward K. W. Loo, James B. Kuo, Marek Syrzycki |
Triple-Threshold Static Power Minimization in High-Level Synthesis of VLSI CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings, pp. 453-462, 2007, Springer, 978-3-540-74441-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
23 | Jochen A. G. Jess, Kerim Kalafala, Srinath R. Naidu, Ralph H. J. M. Otten, Chandramouli Visweswariah |
Statistical Timing for Parametric Yield Prediction of Digital Integrated Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(11), pp. 2376-2392, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
23 | Kiran Seth, Aravindh Anantaraman, Frank Mueller 0001, Eric Rotenberg |
FAST: Frequency-aware static timing analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 5(1), pp. 200-224, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
scheduling, Real-time systems, dynamic voltage scaling, worst-case execution time analysis |
23 | Ara Patapoutian |
Timing metrics for constrained codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Inf. Theory ![In: IEEE Trans. Inf. Theory 52(1), pp. 300-307, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
23 | José A. Lopez-Salcedo, Gregori Vázquez |
Asymptotic equivalence between the unconditional maximum likelihood and the square-law nonlinearity symbol timing estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Signal Process. ![In: IEEE Trans. Signal Process. 54(1), pp. 244-257, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
23 | Hongbin Li 0001, Rensheng Wang, Khaled Amleh |
Blind code-timing estimation for CDMA systems with bandlimited chip waveforms in multipath fading channels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Commun. ![In: IEEE Trans. Commun. 54(1), pp. 141-149, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
23 | Yasamin Mostofi, Donald C. Cox |
Mathematical analysis of the impact of timing synchronization errors on the performance of an OFDM system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Commun. ![In: IEEE Trans. Commun. 54(2), pp. 226-230, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
23 | Kenneth Eguro, Scott Hauck |
Armada: timing-driven pipeline-aware routing for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, FPGA 2006, Monterey, California, USA, February 22-24, 2006, pp. 169-178, 2006, ACM, 1-59593-292-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
pipeline FPGA, pipeline routing, reconfigurable computing |
23 | Lizheng Zhang, Jeng-Liang Tsai, Weijen Chen, Yuhen Hu, Charlie Chung-Ping Chen |
Convergence-provable statistical timing analysis with level-sensitive latches and feedback loops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, Yokohama, Japan, January 24-27, 2006, pp. 941-946, 2006, IEEE, 0-7803-9451-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
23 | Chanseok Hwang, Massoud Pedram |
Timing-driven placement based on monotone cell ordering constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, Yokohama, Japan, January 24-27, 2006, pp. 201-206, 2006, IEEE, 0-7803-9451-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
23 | Mike Hutton, Yan Lin 0001, Lei He 0001 |
Placement and Timing for FPGAs Considering Variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), Madrid, Spain, August 28-30, 2006, pp. 1-7, 2006, IEEE, 1-4244-0312-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
23 | Jiyoun Kim, Marios C. Papaefthymiou, José Luis Neves |
Parallelizing post-placement timing optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), Proceedings, 25-29 April 2006, Rhodes Island, Greece, 2006, IEEE. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
23 | Jörg E. Vollrath, Jürg Schwizer, Marcin Gnat, Ralf Schneider, Bret Johnson |
DDR2 DRAM Output Timing Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 14th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2006), 2-4 August 2006, Taipei, Taiwan, pp. 49-54, 2006, IEEE Computer Society, 0-7695-2572-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
23 | Alejandro Russo, John Hughes 0001, David A. Naumann, Andrei Sabelfeld |
Closing Internal Timing Channels by Transformation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASIAN ![In: Advances in Computer Science - ASIAN 2006. Secure Software and Related Issues, 11th Asian Computing Science Conference, Tokyo, Japan, December 6-8, 2006, Revised Selected Papers, pp. 120-135, 2006, Springer, 978-3-540-77504-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
23 | Sari Onaissi, Farid N. Najm |
A linear-time approach for static timing analysis covering all process corners. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 2006, pp. 217-224, 2006, ACM, 1-59593-389-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
23 | Bo Hu |
Timing-driven placement for heterogeneous field programmable gate array. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 2006, pp. 383-388, 2006, ACM, 1-59593-389-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
23 | Sean X. Shi, Peng Yu, David Z. Pan |
A unified non-rectangular device and circuit simulation model for timing and power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 2006, pp. 423-428, 2006, ACM, 1-59593-389-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
physical design, VLSI CAD, device modeling |
23 | Yue Yu 0002, Shangping Ren, Ophir Frieder |
Prediction of Timing Constraint Violation for Real-Time Embedded Systems with Known Transient Hardware Failure Distribution Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTSS ![In: Proceedings of the 27th IEEE Real-Time Systems Symposium (RTSS 2006), 5-8 December 2006, Rio de Janeiro, Brazil, pp. 454-466, 2006, IEEE Computer Society, 0-7695-2761-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
23 | Valavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh, Stephen Dean Brown |
Difficulty of predicting interconnect delay in a timing driven FPGA CAD flow. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Eigth International Workshop on System-Level Interconnect Prediction (SLIP 2006), Munich, Germany, March 4-5, 2006, Proceedings, pp. 3-8, 2006, ACM, 1-59593-255-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
23 | Lijuan Luo, Qiang Zhou 0001, Yici Cai, Xianlong Hong, Yibo Wang |
A novel technique integrating buffer insertion into timing driven placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
23 | Andrew B. Kahng, Bao Liu 0001, Xu Xu 0001 |
Constructing Current-Based Gate Models Based on Existing Timing Library. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 7th International Symposium on Quality of Electronic Design (ISQED 2006), 27-29 March 2006, San Jose, CA, USA, pp. 37-42, 2006, IEEE Computer Society, 0-7695-2523-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
23 | Chenyu Huang, William John Misskey, Joe Toth |
Combination of Coarse Symbol Timing and Carrier Frequency Offset (CFO) Estimation Techniques for MIMO OFDM Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCECE ![In: Proceedings of the Canadian Conference on Electrical and Computer Engineering, CCECE 2006, May 7-10, 2006, Ottawa Congress Centre, Ottawa, Canada, pp. 472-477, 2006, IEEE, 1-4244-0038-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
23 | Ramyanshu Datta, Gary D. Carpenter, Kevin J. Nowka, Jacob A. Abraham |
A Scheme for On-Chip Timing Characterization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 24th IEEE VLSI Test Symposium (VTS 2006), 30 April - 4 May 2006, Berkeley, California, USA, pp. 24-29, 2006, IEEE Computer Society, 0-7695-2514-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
23 | Pai Peng, Peng Ning, Douglas S. Reeves |
On the Secrecy of Timing-Based Active Watermarking Trace-Back Techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
S&P ![In: 2006 IEEE Symposium on Security and Privacy (S&P 2006), 21-24 May 2006, Berkeley, California, USA, pp. 334-349, 2006, IEEE Computer Society, 0-7695-2574-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
23 | Siva Embanath, Ramakrishnan Venkata |
Exceptional ASIC: Through Automatic Timing Exception Generation (ATEG). ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 19th International Conference on VLSI Design (VLSI Design 2006), 3-7 January 2006, Hyderabad, India, pp. 503-506, 2006, IEEE Computer Society, 0-7695-2502-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
23 | Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram |
Timing-based delay test for screening small delay defects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 320-325, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
test generation, delay testing |
23 | Sujan Pandey, Manfred Glesner |
Statistical on-chip communication bus synthesis and voltage scaling under timing yield constraint. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 663-668, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
communication bus synthesis, voltage scaling |
23 | Zhi Tian, Georgios B. Giannakis |
A GLRT approach to data-aided timing acquisition in UWB radios-Part I: algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Wirel. Commun. ![In: IEEE Trans. Wirel. Commun. 4(6), pp. 2956-2967, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
23 | Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski |
Delay-fault diagnosis using timing information. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(9), pp. 1315-1325, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
23 | Yong Liu, Tan F. Wong, Ashish Pandharipande |
Timing estimation in multiple-antenna systems over Rayleigh flat-fading channels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Signal Process. ![In: IEEE Trans. Signal Process. 53(6), pp. 2074-2088, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
23 | Wonzoo Chung, William A. Sethares, C. Richard Johnson Jr. |
Timing phase offset recovery based on dispersion minimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Signal Process. ![In: IEEE Trans. Signal Process. 53(3), pp. 1097-1109, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
23 | Liuqing Yang 0001, Georgios B. Giannakis |
Timing ultra-wideband signals with dirty templates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Commun. ![In: IEEE Trans. Commun. 53(11), pp. 1952-1963, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
23 | M. Ümit Uyar, Yu Wang 0012, Samrat S. Batth, Adriana Wise, Mariusz A. Fecko |
Timing Fault Models for Systems with Multiple Timers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
TestCom ![In: Testing of Communicating Systems, 17th IFIP TC6/WG 6.1 International Conference, TestCom 2005, Montreal, Canada, May 31 - June 2, 2005, Proceedings, pp. 192-208, 2005, Springer, 3-540-26054-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Timer Constraints, Fault Modeling, Timed Automata, Conformance Testing, Multiple Faults |
23 | Sanjit A. Seshia, Randal E. Bryant, Kenneth S. Stevens |
Modeling and Verifying Circuits Using Generalized Relative Timing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 11th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2005), 14-16 March 2005, New York, NY, USA, pp. 98-108, 2005, IEEE Computer Society, 0-7695-2305-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
23 | Qingzhou (Ben) Wang, John Lillis, Shubhankar Sanyal |
An LP-based methodology for improved timing-driven placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 1139-1143, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
23 | Di Wu 0017, Jiang Hu, Rabi N. Mahapatra |
Coupling aware timing optimization and antenna avoidance in layer assignment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2005 International Symposium on Physical Design, ISPD 2005, San Francisco, California, USA, April 3-6, 2005, pp. 20-27, 2005, ACM, 1-59593-021-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
VLSI, interconnect, probabilistic modeling, physical design, crosstalk, design for manufacturability (DFM), antenna effect |
23 | Hana Chockler, Kathi Fisler |
Temporal Modalities for Concisely Capturing Timing Diagrams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHARME ![In: Correct Hardware Design and Verification Methods, 13th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2005, Saarbrücken, Germany, October 3-6, 2005, Proceedings, pp. 176-190, 2005, Springer, 3-540-29105-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
23 | David J. Hathaway |
Dealing with the spatio-temporal interactions among transient power, supply noise and timing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Seventh International Workshop on System-Level Interconnect Prediction (SLIP 2005), San Francisco, CA, USA, April 2-3, 2005, Proceedings, pp. 61, 2005, ACM, 1-59593-033-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
23 | Sibin Mohan, Frank Mueller 0001, David B. Whalley, Christopher A. Healy |
Timing Analysis for Sensor Network Nodes of the Atmega Processor Family. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Real-Time and Embedded Technology and Applications Symposium ![In: 11th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2005), 7-10 March 2005, San Francisco, CA, USA, pp. 405-414, 2005, IEEE Computer Society, 0-7695-2302-1. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
23 | Christian Vogel 0001, Dieter Draxelmayr, Gernot Kubin |
Spectral shaping of timing mismatches in time-interleaved analog-to-digital converters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 1394-1397, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
23 | Octav Chipara, Chenyang Lu 0001, Gruia-Catalin Roman |
Efficient Power Management Based on Application Timing Semantics for Wireless Sensor Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICDCS ![In: 25th International Conference on Distributed Computing Systems (ICDCS 2005), 6-10 June 2005, Columbus, OH, USA, pp. 361-370, 2005, IEEE Computer Society, 0-7695-2331-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
23 | Jie Yang 0010, Luigi Capodieci, Dennis Sylvester |
Advanced timing analysis based on post-OPC extraction of critical dimensions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 359-364, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
process CD, layout, OPC, design flow |
23 | Hongliang Chang, Vladimir Zolotov, Sambasivan Narayan, Chandu Visweswariah |
Parameterized block-based statistical timing analysis with non-gaussian parameters, nonlinear delay functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 71-76, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
23 | Chi-Sheng Shih 0001, Jane W.-S. Liu |
Acquiring and incorporating state-dependent timing requirements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Requir. Eng. ![In: Requir. Eng. 9(2), pp. 121-131, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Requirement capture and update, Real-time software architecture, Real-time requirements |
23 | Jason Cong, Sung Kyu Lim |
Retiming-based timing analysis with an application to mincut-based global placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(12), pp. 1684-1692, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
23 | Brian Neil Levine, Michael K. Reiter, Chenxi Wang, Matthew K. Wright |
Timing Attacks in Low-Latency Mix Systems (Extended Abstract). ![Search on Bibsonomy](Pics/bibsonomy.png) |
Financial Cryptography ![In: Financial Cryptography, 8th International Conference, FC 2004, Key West, FL, USA, February 9-12, 2004. Revised Papers, pp. 251-265, 2004, Springer, 3-540-22420-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
23 | Neil C. Audsley, Konstantinos Bletsas |
Fixed Priority Timing Analysis of Real-Time Systems with Limited Parallelism. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECRTS ![In: 16th Euromicro Conference on Real-Time Systems (ECRTS 2004), 30 June - 2 July 1004, Catania, Italy, Proceedings, pp. 231-238, 2004, IEEE Computer Society, 0-7695-2176-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
23 | Mango Chia-Tso Chao, Li-C. Wang, Kwang-Ting Cheng |
Pattern Selection for Testing of Deep Sub-Micron Timing Defects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 160, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
23 | Keoncheol Shin, Taewhan Kim |
An integrated approach to timing-driven synthesis and placement of arithmetic circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, Yokohama, Japan, January 27-30, 2004, pp. 155-158, 2004, IEEE Computer Society, 0-7803-8175-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
23 | Reinhard Wilhelm |
Formal Analysis of Processor Timing Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPIN ![In: Model Checking Software, 11th International SPIN Workshop, Barcelona, Spain, April 1-3, 2004, Proceedings, pp. 1-4, 2004, Springer, 3-540-21314-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
23 | Vishal Khandelwal, Azadeh Davoodi, Ankur Srivastava 0001 |
Efficient statistical timing analysis through error budgeting. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2004 International Conference on Computer-Aided Design, ICCAD 2004, San Jose, CA, USA, November 7-11, 2004, pp. 473-477, 2004, IEEE Computer Society / ACM, 0-7803-8702-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
23 | Masashi Shimanouchi |
Timing Accuracy Enhancement by a New Calibration Scheme for Multi-Gbps ATE. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, pp. 567-576, 2004, IEEE Computer Society, 0-7803-8581-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
23 | Aseem Agarwal, Vladimir Zolotov, David T. Blaauw |
Statistical timing analysis using bounds and selective enumeration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(9), pp. 1243-1260, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|