Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
10 | Jun-Hee Mun, Shung Han Cho, Sangjin Hong |
Flexible Controller Design and Its Application for Concurrent Execution of Buffer Centric Dataflows. |
J. VLSI Signal Process. |
2007 |
DBLP DOI BibTeX RDF |
flexible controller design, buffer centric dataflow, reconfigurable architecture |
10 | Konrad Slind, Scott Owens, Juliano Iyoda, Mike Gordon |
Proof producing synthesis of arithmetic and cryptographic hardware. |
Formal Aspects Comput. |
2007 |
DBLP DOI BibTeX RDF |
Cryptography, Compiling, Theorem proving, Hardware synthesis, High assurance |
10 | Fabrizio Ferrandi, Pier Luca Lanzi, Gianluca Palermo, Christian Pilato, Donatella Sciuto, Antonino Tumeo |
An Evolutionary Approach to Area-Time Optimization of FPGA designs. |
ICSAMOS |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Nishant Sinha 0001, Edmund M. Clarke |
SAT-Based Compositional Verification Using Lazy Learning. |
CAV |
2007 |
DBLP DOI BibTeX RDF |
|
10 | David M. Russinoff |
A Mathematical Approach to RTL Verification. |
CAV |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Barbara Jobstmann, Stefan J. Galler, Martin Weiglhofer, Roderick Bloem |
Anzu: A Tool for Property Synthesis. |
CAV |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Scott Little, Alper Sen 0001, Chris J. Myers |
Application of Automated Model Generation Techniques to Analog/Mixed-Signal Circuits. |
MTV |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Gaurav Singh 0006, Sandeep K. Shukla |
Model Checking Bluespec Specified Hardware Designs. |
MTV |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Behnam Ghavami, Mahtab Niknahad, Mehrdad Najibi, Hossein Pedram |
A Fast and Accurate Power Estimation Methodology for QDI Asynchronous Circuits. |
PATMOS |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Francesco Centurelli, Luca Giancane, Mauro Olivieri, Giuseppe Scotti, Alessandro Trifiletti |
A Statistical Model of Logic Gates for Monte Carlo Simulation Including On-Chip Variations. |
PATMOS |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Michael J. Wirthlin, Misha Burich, Andrew Guyler, Brian Von Herzen |
High-level languages: the future or a passing fad? |
FPGA |
2007 |
DBLP DOI BibTeX RDF |
high-level design languages, RTL design |
10 | Min Chen 0024, Wei Zhao, Frank Liu 0001, Yu Cao 0001 |
Fast statistical circuit analysis with finite-point based transistor model. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Shuilong Huang, Huainan Ma, Zhihua Wang |
Modeling and simulation to the design of SigmaDelta fractional-N frequency synthesizer. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Sanjit A. Seshia, Wenchao Li 0001, Subhasish Mitra |
Verification-guided soft error resilience. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Jason A. Blome, Shuguang Feng, Shantanu Gupta, Scott A. Mahlke |
Self-calibrating Online Wearout Detection. |
MICRO |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Yan Lin Aung, Douglas L. Maskell, Timothy F. Oliver, Bertil Schmidt, William Bong |
C-Based Design Methodology for FPGA Implementation of ClustalW MSA. |
PRIB |
2007 |
DBLP DOI BibTeX RDF |
ClustalW, FPGA, multiple sequence alignment, sequence analysis |
10 | Muhammad T. Anan, Ghulam M. Chaudhry |
A Real-Time Hardware-Based Scheduler For Next-Generation Optical Burst Switches. |
ICC |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Xiao Hu, Pengyong Ma, Shuming Chen |
Scheduling for Combining Traffic of On-Chip Trace Data in Embedded Multi-core Processor. |
ICESS |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Mark A. Erle, Michael J. Schulte, Brian J. Hickmann |
Decimal Floating-Point Multiplication Via Carry-Save Addition. |
IEEE Symposium on Computer Arithmetic |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Jin-Oh Jeon, Su-Bong Ryu, Tae-Min Chang, Ho-Yong Choi, Min-Sup Kang |
Digital Codec Design for RFID Tag Based on Cryptographic Authentication Protocol. |
FGCN (2) |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Flavius Gruian, Mark Westmijze |
BlueJEP: a flexible and high-performance Java embedded processor. |
JTRES |
2007 |
DBLP DOI BibTeX RDF |
embedded systems, Java processor, Bluespec |
10 | Chao Wang 0068, Wu Zhilin, Peng Cao 0002, Li Jie |
An Efficient VLSI Architecture for Lifting-Based Discrete Wavelet Transform. |
ICME |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Walid A. Najjar |
Compiling code accelerators for FPGAs. |
CASES |
2007 |
DBLP DOI BibTeX RDF |
FPGA code acceleration |
10 | Mahsan Amoui, Daniel Große, Mitchell A. Thornton, Rolf Drechsler |
Evaluation of Toggle Coverage for MVL Circuits Specified in the SystemVerilog HDL. |
ISMVL |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Chengjun Zhang, Chunyan Wang 0004, M. Omair Ahmad |
A VLSI Architecture for a Fast Computation of the 2-D Discrete Wavelet Transform. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Ik-Jae Chun, Tae Moon Roh, Bo-Gwan Kim |
Binary-Truncated CDMA-Based On-Chip Network. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Jun Wang 0010, Kyeong-Yuk Min, Jong-Wha Chong |
A Hybrid Image Coding in Overdriving for Motion Blur Reduction in LCD. |
ICEC |
2007 |
DBLP DOI BibTeX RDF |
Overdriving, Block Truncation Coding, Adaptive Quantization Coding, Compression, LCD, Motion blur |
10 | Mustafa Parlak, Ilker Hamzaoglu |
A Low Power Implementation of H.264 Adaptive Deblocking Filter Algorithm. |
AHS |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Jin-Oh Jeon, Su-Bong Ryu, Sang-Jo Park, Min-Sup Kang |
Strong Authentication Protocol for RFID Tag Using SHA-1 Hash Algorithm. |
ICCSA (1) |
2007 |
DBLP DOI BibTeX RDF |
Strong authentication protocol, SHA-1 hash algorithm, Three-way challenge response, ISO/IEC 1800-3 standard, Digital Codec design, RFID Tag |
10 | Adam Handzlik, Andrzej Jablonski |
"Chameleon" Software Defined Control Platform. |
EUROCAST |
2007 |
DBLP DOI BibTeX RDF |
Signal processing architectures, control platform development, innovative reprogrammable technology, virtual Programmable Logic Controller, Field Programmable Gate Arrays, IP Core |
10 | Haruhiko Kaneko, Eiji Fujiwara |
Reconstruction of Erasure Correcting Codes for Dependable Distributed Storage System without Spare Disks. |
DFT |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Seung-Man Pyen, Kyeong-Yuk Min, Jong-Wha Chong |
An Efficient VLSI Architecture for Full-Search Variable Block Size Motion Estimation in H.264/AVC. |
MMM (2) |
2007 |
DBLP DOI BibTeX RDF |
VBSME, VLSI, motion estimation, H.264/AVC, block matching algorithm |
10 | Vahid Lari, Mehdi Dehbashi, Seyed Ghassem Miremadi, Navid Farazmand |
Assessment of Message Missing Failures in FlexRay-Based Networks. |
PRDC |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Shrenik Mehta, Dwayne Lee |
Industry perspective on chip multi-threading, bridging the gap with academia using OpenSPARC. |
WCAE |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Shobha Vasudevan, Vinod Viswanath, Jacob A. Abraham |
Efficient Microprocessor Verification using Antecedent Conditioned Slicing. |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Jiang Long, Andrew Seawright |
Synthesizing SVA Local Variables for Formal Verification. |
DAC |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Foster F. Dai, Charles E. Stroud, Dayu Yang |
Automatic linearity and frequency response tests with built-in pattern generator and analyzer. |
IEEE Trans. Very Large Scale Integr. Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Stephen A. Edwards, Olivier Tardieu |
SHIM: a deterministic model for heterogeneous embedded systems. |
IEEE Trans. Very Large Scale Integr. Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Hyunchul Shin, Jin-Aeon Lee, Lee-Sup Kim |
A cost-effective VLSI architecture for anisotropic texture filtering in limited memory bandwidth. |
IEEE Trans. Very Large Scale Integr. Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Jaehwan John Lee, Vincent John Mooney |
A Novel {O(n)} Parallel Banker's Algorithm for System-on-a-Chip. |
IEEE Trans. Parallel Distributed Syst. |
2006 |
DBLP DOI BibTeX RDF |
Parallel Banker's Algorithm, deadlock avoidance in hardware, multiprocessor system-on-a-chip |
10 | Kris Tiri, Ingrid Verbauwhede |
A digital design flow for secure integrated circuits. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Tao Lv 0001, Jianping Fan 0002, Xiaowei Li 0001, Ling-Yi Liu |
Observability Statement Coverage Based on Dynamic Factored Use-Definition Chains for Functional Verification. |
J. Electron. Test. |
2006 |
DBLP DOI BibTeX RDF |
dynamic factored use-definition chains, observability, data-flow analysis, design verification, coverage metrics |
10 | Patrick Schaumont, Doris Ching, Ingrid Verbauwhede |
An interactive codesign environment for domain-specific coprocessors. |
ACM Trans. Design Autom. Electr. Syst. |
2006 |
DBLP DOI BibTeX RDF |
hardware description language, hardware-software codesign, Cosimulation |
10 | Shobha Vasudevan, Jacob A. Abraham, Vinod Viswanath, Jiajin Tu |
Automatic decomposition for sequential equivalence checking of system level and RTL descriptions. |
MEMOCODE |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Mark G. Arnold |
A RISC Processor with Redundant LNS Instructions. |
DSD |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Alexander Kamkin |
The UniTESK Approach to Specification-Based Validation of Hardware Designs. |
ISoLA |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Baofeng Li, Qiang Shao |
Deeply Parallel Architecture for Lifting-Based 2D DWT in JPEG2000. |
CIT |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Hansu Cho, Samar Abdi, Daniel Gajski |
Design and implementation of transducer for ARM-TMS communication. |
ASP-DAC |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Ramsey Hourani, Ravi Jenkal, W. Rhett Davis, Winser E. Alexander |
Automated Architectural Exploration for Signal Processing Algorithms. |
SiPS |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Choudhury A. Rahman, Wael M. Badawy |
An Area Efficient Real-time CAVLC IP-Block towards the H.264/AVC Encoder. |
SiPS |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Christian Ferdinand, Florian Martin 0001, Christoph Cullmann, Marc Schlickling, Ingmar Stein, Stephan Thesing, Reinhold Heckmann |
New Developments in WCET Analysis. |
Program Analysis and Compilation |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Seung-Man Pyen, Kyeong-Yuk Min, Jong-Wha Chong, Satoshi Goto |
An Efficient Hardware Architecture for Full-Search Variable Block Size Motion Estimation in H.264/AVC. |
ISVC (2) |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Carsten Bieser |
A Novel FPGA Design Acceleration Methodology Supported by a Unique RP Platform for Fast and Easy System Develpoment. |
FPL |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Zude Zhou, Songlin Cheng, Quan Liu |
Application of DDR Controller for High-speed Data Acquisition Board. |
ICICIC (2) |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Erik Reeber, Warren A. Hunt Jr. |
A SAT-Based Decision Procedure for the Subclass of Unrollable List Formulas in ACL2 (SULFA). |
IJCAR |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Carsten Bieser, Klaus D. Müller-Glaser |
Rapid Prototyping Design Acceleration Using a Novel Merging Methodology for Partial Configuration Streams of Xilinx Virtex-II FPGAs. |
IEEE International Workshop on Rapid System Prototyping |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Hyunseok Lee, Trevor N. Mudge, Chaitali Chakrabarti |
Reducing idle mode power in software defined radio terminals. |
ISLPED |
2006 |
DBLP DOI BibTeX RDF |
baseband processor, idle mode, wireless terminal, low power, SIMD, SDR, software defined radio |
10 | Saeid Hashemi, Mohamad Sawan, Yvon Savaria |
A power planning model for implantable stimulators. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Charles E. Stroud, Dayu Yang, Foster F. Dai |
Analog frequency response measurement in mixed-signal systems. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Kuang-Hao Lin, Hsin-Lei Lin, Shih-Ming Wang, Robert Chen-Hao Chang |
Implementation of digital IQ imbalance compensation in OFDM WLAN receivers. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Kai-Yuan Jheng, Yi-Chiuan Wang, An-Yeu Wu, Hen-Wai Tsao |
DSP engine design for LINC wireless transmitter systems. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Pawel Garstecki, Adam Luczak, Marta Stepniewska |
A bit-serial implementation of mode decision algorithm for AVC encoders. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Po-Tsang Huang, Wei Hwang |
2-level FIFO architecture design for switch fabrics in network-on-chip. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Kimo Kim, In-Cheol Park |
Combined image signal processing for CMOS image sensors. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
10 | André K. Nieuwland, Samir Jasarevic, Goran Jerin |
Combinational Logic Soft Error Analysis and Protection. |
IOLTS |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Neil Smyth, Máire McLoone, John V. McCanny |
An Adaptable And Scalable Asymmetric Cryptographic Processor. |
ASAP |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Xianhui He, Yongxin Zhu 0001, Zhenxin Sun, Yuzhuo Fu |
UML Based Evaluation of Reconfigurable Shape Adaptive DCT for Embedded Stream Processing. |
EUC Workshops |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Donglin Li, Otmane Aït Mohamed |
MDG-Based Verification of the Look-Aside Interface. |
CCECE |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Josh Harr |
Innovative technologies II - Multi-paradigm computing. |
SC |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Bruno Girodias, El Mostapha Aboulhamid, Gabriela Nicolescu |
A Platform for Refinement of OS Services for Embedded Systems. |
DELTA |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Tathagato Rai Dastidar, Partha Ray |
A New Device Level Digital Simulator for Simulation and Functional Verification of Large Semiconductor Memories. |
VLSI Design |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Junhao Zheng, Di Wu 0022, Lei Deng 0007, Don Xie, Wen Gao 0001 |
A Motion Vector Predictor Architecture for AVS and MPEG-2 HDTV Decoder. |
PCM |
2006 |
DBLP DOI BibTeX RDF |
Motion vector prediction, MPEG, Motion compensation, VLSI architecture, AVS |
10 | Shiqun Zhang, Dunshan Yu, Shimin Sheng |
A Discrete STFT Processor for Real-time Spectrum Analysis. |
APCCAS |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Yu-Chien Kao, Huang-Chih Kuo, Yin-Tzu Lin, Chia-Wen Hou, Yi-Hsien Li, Hao-Tin Huang, Youn-Long Lin |
A High-Performance VLSI Architecture for Intra Prediction and Mode Decision in H.264/AVC Video Encoding. |
APCCAS |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Wonwoo Jang, Hyunsik Kim, Sungmok Lee, Jooyoung Ha, Bongsoon Kang |
Implementation of the Gamma Line System Similar to Non-linear Gamma Curve with 2bit Error(LSB). |
APCCAS |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Ajay Kumar Verma, Paolo Ienne |
Towards the automatic exploration of arithmetic-circuit architectures. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Insu Song, Guido Governatori |
Designing agent chips. |
AAMAS |
2006 |
DBLP DOI BibTeX RDF |
agent chips, agent architecture, agent programming languages |
10 | Kun-Bin Lee, Jih-Yiing Lin, Chein-Wei Jen |
A multisymbol context-based arithmetic coding architecture for MPEG-4 shape coding. |
IEEE Trans. Circuits Syst. Video Technol. |
2005 |
DBLP DOI BibTeX RDF |
|
10 | Jung L. Lee, Myung Hoon Sunwoo |
Implementation of a Wireless Multimedia DSP Chip for Mobile Applications. |
J. VLSI Signal Process. |
2005 |
DBLP DOI BibTeX RDF |
multimedia, DSP, instruction |
10 | Fei Xie, Xiaoyu Song, Haera Chung, Ranajoy Nandi |
Translation-based co-verification. |
MEMOCODE |
2005 |
DBLP DOI BibTeX RDF |
|
10 | Miodrag Vujkovic, David Wadkins, Carl Sechen |
Efficient Post-layout Power-Delay Curve Generation. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
10 | Ankit Mathur, Mayank Agarwal, Soumyadeb Mitra, Anup Gangwar, M. Balakrishnan, Subhashis Banerjee |
SMPS: an FPGA-based prototyping environment for multiprocessor embedded systems (abstract only). |
FPGA |
2005 |
DBLP DOI BibTeX RDF |
|
10 | Kris Tiri, Ingrid Verbauwhede |
A VLSI Design Flow for Secure Side-Channel Attack Resistant ICs. |
DATE |
2005 |
DBLP DOI BibTeX RDF |
|
10 | Stephen A. Edwards |
The Challenges of Hardware Synthesis from C-Like Languages. |
DATE |
2005 |
DBLP DOI BibTeX RDF |
|
10 | Saranyan A. Vigraham, John C. Gallagher |
A space saving digital VLSI evolutionary engine for CTRNN-EH devices. |
Congress on Evolutionary Computation |
2005 |
DBLP DOI BibTeX RDF |
|
10 | Jaehwan John Lee, Vincent John Mooney III |
A novel O(n) parallel banker's algorithm for System-on-a-Chip. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
10 | Indradeep Ghosh |
High Level Test Generation for Custom Hardware: An Industrial Perspective. |
Asian Test Symposium |
2005 |
DBLP DOI BibTeX RDF |
|
10 | Il-Gu Lee, Seungbeom Lee, Sin-Chong Park |
Effective Co-Verification of IEEE 802.11a MAC/PHY Combining Emulation and Simulation Technology. |
Annual Simulation Symposium |
2005 |
DBLP DOI BibTeX RDF |
|
10 | Martín Casado, Gregory Watson, Nick McKeown |
Teaching networking hardware. |
ITiCSE |
2005 |
DBLP DOI BibTeX RDF |
network internals, network project, pedagogy |
10 | Mark G. Arnold |
The Residue Logarithmic Number System: Theory and Implementation. |
IEEE Symposium on Computer Arithmetic |
2005 |
DBLP DOI BibTeX RDF |
|
10 | John D. Lynch, Daniel W. Hammerstrom, Roy Kravitz |
A Cohesive FPGA-Based System-on-Chip Design Curriculum. |
MSE |
2005 |
DBLP DOI BibTeX RDF |
|
10 | R. James Duckworth |
Embedded System Design with FPGAs Using HDLs (Lessons Learned and Pitfalls to Be Avoided). |
MSE |
2005 |
DBLP DOI BibTeX RDF |
|
10 | Debashis Sahoo, Jawahar Jain, Subramanian K. Iyer, David L. Dill, E. Allen Emerson |
Predictive Reachability Using a Sample-Based Approach. |
CHARME |
2005 |
DBLP DOI BibTeX RDF |
|
10 | Girish Venkataramani, Tiberiu Chelcea, Seth Copen Goldstein, Tobias Bjerregaard |
SOMA: a tool for synthesizing and optimizing memory accesses in ASICs. |
CODES+ISSS |
2005 |
DBLP DOI BibTeX RDF |
high-level synthesis, memory synthesis |
10 | Mathias Halbach, Rolf Hoffmann |
Optimal Behavior of a Moving Creature in the Cellular Automata Model. |
PaCT |
2005 |
DBLP DOI BibTeX RDF |
|
10 | Stephen A. Edwards, Olivier Tardieu |
SHIM: a deterministic model for heterogeneous embedded systems. |
EMSOFT |
2005 |
DBLP DOI BibTeX RDF |
deterministic model of computation, hardware/software codesign, software synthesis, hardware synthesis |
10 | Youhui Zhang, Liu Dong, Yu Gu 0005, Dongsheng Wang 0002 |
Exploring Design Space Using Transaction Level Models. |
Asia-Pacific Computer Systems Architecture Conference |
2005 |
DBLP DOI BibTeX RDF |
|
10 | Gyu-Sung Yeon, Chi-Hun Jun, Tae-Jin Hwang, Seongsoo Lee, Jae-Kyung Wee |
Low-Power MPEG-4 Motion Estimator Design for Deep Sub-Micron Multimedia SoC. |
KES (3) |
2005 |
DBLP DOI BibTeX RDF |
|
10 | Young-Su Kwon, Payam Lajevardi, Anantha P. Chandrakasan, Frank Honoré, Donald E. Troxel |
A 3-D FPGA wire resource prediction model validated using a 3-D placement and routing tool. |
SLIP |
2005 |
DBLP DOI BibTeX RDF |
3-D FPGA, wire resource prediction |
10 | Hyunseok Lee, Trevor N. Mudge |
A dual-processor solution for the MAC layer of a software defined radio terminal. |
CASES |
2005 |
DBLP DOI BibTeX RDF |
SDR terminal, wireless platform, protocol processing |