Search results for "3DIC"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Patrick Leduc, Myriam Assous, Léa Di Cioccio, Marc Zussy, Thomas Signamarcheix, Antonio Roman, Maxime Rousseau, Sophie Verrun, Laurent Bally, David Bouchu, Lionel Cadix, Alexis Farcy, Nicolas Sillon	First integration of Cu TSV using die-to-wafer direct bonding and planarization.	3DIC	2009	DBLP DOI BibTeX RDF
1	Ryusuke Egawa, Jubee Tada, Hiroaki Kobayashi, Gensuke Goto	Evaluation of fine grain 3-D integrated arithmetic units.	3DIC	2009	DBLP DOI BibTeX RDF
1	Yuki Ohara, Akihiro Noriki, Katsuyuki Sakuma, Kang Wook Lee 0002, Mariappan Murugesan, Jichoel Bea, Fumiaki Yamada, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi	10 µm fine pitch Cu/Sn micro-bumps for 3-D super-chip stack.	3DIC	2009	DBLP DOI BibTeX RDF
1	Weng Hong Teh, Raymond Caramto, Jamal Qureshi, Sitaram Arkalgud, M. O'Brien, T. Gilday, Kou Maekawa, T. Saito, Kouichi Maruyama, Thenappan Chidambaram, Wei Wang 0003, David Marx, David Grant, Russ Dudley	A route towards production-worthy 5 µm × 25 µm and 1 µm × 20 µm non-Bosch through-silicon-via (TSV) etch, TSV metrology, and TSV integration.	3DIC	2009	DBLP DOI BibTeX RDF
1	Tomohide Murase, Hiroyuki Aikyou, Fumikazu Mizutani, Yu Shoji, Tomoya Higashihara, Mitsuru Ueda	Thermotropic liquid crystalline polyimides toward high heat conducting materials for 3D chip stack.	3DIC	2009	DBLP DOI BibTeX RDF
1	Dragomir Milojevic, Trevor E. Carlson, Kris Croes, Riko Radojcic, Diana F. Ragett, Dirk Seynhaeve, Federico Angiolini, Geert Van der Plas, Paul Marchal	Automated Pathfinding tool chain for 3D-stacked integrated circuits: Practical case study.	3DIC	2009	DBLP DOI BibTeX RDF
1	Seyyed Ahmad Razavi, Morteza Saheb Zamani, Kia Bazargan	A tileable switch module architecture for homogeneous 3D FPGAs.	3DIC	2009	DBLP DOI BibTeX RDF
1	Kelli Ireland, Donald M. Chiarulli, Steven P. Levitan	A routerless system level interconnection network for 3D integrated systems.	3DIC	2009	DBLP DOI BibTeX RDF
1	Keith Buchanan, Stephen Burgess, Kathrine Giles, Matthew Muggeridge, Hao Zhao	Etch, dielectrics and metal barrier-seed for low temperature through-silicon via processing.	3DIC	2009	DBLP DOI BibTeX RDF
1	Dean L. Lewis, Hsien-Hsin S. Lee	Architectural evaluation of 3D stacked RRAM caches.	3DIC	2009	DBLP DOI BibTeX RDF
1	Matt Grange, Awet Yemane Weldezion, Dinesh Pamunuwa, Roshan Weerasekera, Zhonghai Lu, Axel Jantsch, Dave Shippen	Physical mapping and performance study of a multi-clock 3-Dimensional Network-on-Chip mesh.	3DIC	2009	DBLP DOI BibTeX RDF
1	Thomas Brunschwiler, Stephan Paredes, Ute Drechsler, Bruno Michel, W. Cesar, G. Töral, Yuksel Temiz, Yusuf Leblebici	Validation of the porous-medium approach to model interlayer-cooled 3D-chip stacks.	3DIC	2009	DBLP DOI BibTeX RDF
1	Ric van Doremalen, Piet van Engen, Wouter Jochems, Shi Cheng, Thomas Fritzsch, Walter De Raedt	Miniature wireless activity monitor using 3D system integration.	3DIC	2009	DBLP DOI BibTeX RDF
1	Grzegorz Janczyk, Tomasz Bieniek, Jerzy Szynka, Piotr Grabiec	Reliability aspects of 3D-oriented heterogeneous device design related to stress sensitivity of MOS transistors.	3DIC	2009	DBLP DOI BibTeX RDF
1	Christopher Mineo, William Rhett Davis	The benefits of 3D networks-on-chip as shown with LDPC decoding.	3DIC	2009	DBLP DOI BibTeX RDF
1	Tapobrata Bandyopadhyay, Ritwik Chatterjee, Daehyun Chung, Madhavan Swaminathan, Rao R. Tummala	Electrical modeling of Through Silicon and Package Vias.	3DIC	2009	DBLP DOI BibTeX RDF
1	Thomas Fritzsch, Raul Mrossko, Tobias Baumgartner 0003, Michael Toepper, Matthias Klein, Jürgen Wolf, Bernhard Wunderle, Herbert Reichl	3-D thin chip integration technology - from technology development to application.	3DIC	2009	DBLP DOI BibTeX RDF
1	Ji Chel Bea, Mariappan Murugesan, Yuki Ohara, Akihiro Noriki, Hisashi Kino, Kang Wook Lee 0002, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi	Micro-Raman spectroscopy analysis and capacitance - time (C-t) measurement of thinned silicon substrates for 3D integration.	3DIC	2009	DBLP DOI BibTeX RDF
1	Claudio Truzzi, Frédéric Raynal, Vincent Mevellec	Wet-process deposition of TSV liner and metal films.	3DIC	2009	DBLP DOI BibTeX RDF
1	G. Williams, Patrick O'Hara, J. Moore, Bart Gordon, J. Rose	A review of wafer bonding materials and characterizations to enable wafer thinning, backside processing, and laser dicing.	3DIC	2009	DBLP DOI BibTeX RDF
1	Yusuke Funaya, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi	3D on-chip memory for the vector architecture.	3DIC	2009	DBLP DOI BibTeX RDF
1	Shiv Govind Singh, Chuan Seng Tan	Impact of thermal through silicon via (TTSV) on the temperature profile of multi-layer 3-D device stack.	3DIC	2009	DBLP DOI BibTeX RDF
1	Matthew Hogan, Dusan Petranovic	Robust verification of 3D-ICs: Pros, cons and recommendations.	3DIC	2009	DBLP DOI BibTeX RDF
1	Eun Chu Oh, Paul D. Franzon	Technology impact analysis for 3D TCAM.	3DIC	2009	DBLP DOI BibTeX RDF
1	Yaoyao Ye, Lian Duan, Jiang Xu 0001, Jin Ouyang, Mo Kwai Hung, Yuan Xie 0001	3D optical networks-on-chip (NoC) for multiprocessor systems-on-chip (MPSoC).	3DIC	2009	DBLP DOI BibTeX RDF

Publications at "3DIC"( http://dblp.L3S.de/Venues/3DIC )