Search results for "A-SSCC"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Wala Saadeh, Haneen Alsuradi, Muhammad Awais Bin Altaf, Jerald Yoo	A 1.1mW hybrid OFDM ground effect-resilient body coupled communication transceiver for head and body area network.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Jie Zhang 0039, Hong Zhang 0009, Ruizhi Zhang 0002, Jiangtao Xu, Yang Zhao, Mudan Zhang, Jia Li	A mixed-signal ASIC for triple-chamber cardiac pacemakers with heart resistance measurement.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Tai-Chuan Ou, Zhengya Zhang, Marios C. Papaefthymiou	A 934MHz 9Gb/s 3.2pJ/b/iteration charge-recovery LDPC decoder with in-package inductors.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Matteo Ramella, Ivan Fabiano, Danilo Manstretta, Rinaldo Castello	A 2.4GHz low-power SAW-less receiver for SoC coexistence.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Y. J. Du, W. Su, S. Tolunay, L. Zhang, M. Kaynak, R. Scholz, Yong-Zhong Xiong	220GHz wide-band MEMS switch in standard BiCMOS technology.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Zheng Song 0002, Xiliang Liu, Zongming Jin, Xiaokun Zhao, Qiongbing Liu, Yun Yin, Baoyong Chi	A 180nm CMOS wireless transceiver by utilizing guard band for narrowband IoT applications.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Meng Li 0012, Jan-Willem Weijers, Veerle Derudder, Ilse Vos, Maxim Rykunov, Steven Dupont, Peter Debacker, Andy Dewilde, Yanxiang Huang, Liesbet Van der Perre, Wim Van Thillo	An energy efficient 18Gbps LDPC decoding processor for 802.11ad in 28nm CMOS.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Hai Huang 0010, Ling Du, Yun Chiu	A 1.2-GS/s 8-bit two-step SAR ADC in 65-nm CMOS with passive residue transfer.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Shinsuke Nakano, Masafumi Nogawa, Hideyuki Nosaka, Akira Tsuchiya, Hidetoshi Onodera, Shunji Kimura	A 25-Gb/s 480-mW CMOS modulator driver using area-efficient 3D inductor peaking.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Chao Yuan, Kian Ann Ng, Yong Ping Xu, Shih-Cheng Yen, Nitish V. Thakor	A 1-V 9.8-ENOB 100-kS/s single-ended SAR ADC with symmetrical DAC switching technique for neural signal acquisition.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Matteo Ramella, Ivan Fabiano, Danilo Manstretta, Rinaldo Castello	A 1.7-2.1GHz +23dBm TX power compatible blocker tolerant FDD receiver with integrated duplexer in 28nm CMOS.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Li-Cheng Chu, Te-Fu Yang, Ru-Yu Huang, Yi-Ping Su, Chiun-He Lin, Chin-Long Wey, Ke-Horng Chen, Ying-Hsi Lin, Chao-Cheng Lee, Jian-Ru Lin, Tsung-Yen Tsai	200nA low quiescent current deep-standby mode in 28nm DC-DC buck converter for active implantable medical devices.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Allen Waters, Un-Ku Moon	A fully automated verilog-to-layout synthesized ADC demonstrating 56dB-SNDR with 2MHz-BW.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Junfeng Jiang, Kofi A. A. Makinwa	A multi-path CMOS Hall sensor with integrated ripple reduction loops.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Hiroki Miyaoka, Futoshi Terasawa, Masahiro Kudo, Hideki Kano, Atsushi Matsuda, Noriaki Shirai, Shigeaki Kawai, Tomoyuki Arai, Yutaka Ide, Kazuhiro Terashima, Hirohito Higashi, Tomokazu Higuchi, Naoaki Naka	A 28-Gb/s 4.5-pJ/bit transceiver with 1-tap decision feedback equalizer in 28-nm CMOS.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Jaehwa Kwak, Borivoje Nikolic	A 550-2260MHz self-adjustable clock generator in 28nm FDSOI.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Saurabh Agarwal, Mark Ingels, Michal Rakowski, Marianna Pantouvaki, Michiel Steyaert, Philippe P. Absil, Joris Van Campenhout	Wavelength locking of a Si ring modulator using an integrated drop-port OMA monitoring circuit.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Kelvin Yi-Tse Lai, Ming-Feng Shiu, Yi-Wen Lu, Yingchieh Ho, Yu-Chi Kao, Yu-Tao Yang, Gary Wang, Keng-Ming Liu, Hsie-Chia Chang, Chen-Yi Lee	A field-programmable lab-on-a-chip with built-in self-test circuit and low-power sensor-fusion solution in 0.35μm standard CMOS process.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Matthew J. Turnquist, Markus Hiienkari, Jani Mäkipää, Lauri Koskinen	A fully integrated self-oscillating switched-capacitor DC-DC converter for near-threshold loads.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Chia-Chi Kuo, Chih-Cheng Hsieh	A 132dB DR readout IC with pulse width modulation for IR focal plane arrays.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Lilan Yu, Masaya Miyahara, Akira Matsuzawa	A 9-bit 1.8-GS/s pipelined ADC using linearized open-loop amplifiers.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Huan-Sheng Chen, Hung-Yu Tsai, Li-Xuan Chuo, Yu-Kai Tsai, Liang-Hung Lu	A 5.2-GHz full-integrated RF front-end by T/R switch, LNA, and PA co-design with 3.2-dB NF and +25.9-dBm output power.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Tomoya Ishii, Shogo Hachiya, Sheyang Ning, Masahiro Tanaka, Ken Takeuchi	0.6 V operation, 26% smaller voltage ripple, 9% energy efficient boost converter with adaptively optimized comparator bias-current for ReRAM program in low power IoT embedded applications.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Joo-Hyung Chae, Gi-Moon Hong, Jihwan Park, Mino Kim, Hyeongjun Ko, Woo-Yeol Shin, Hankyu Chi, Deog-Kyoon Jeong, Suhwan Kim	A 1.74mW/GHz 0.11-2.5GHz fast-locking, jitter-reducing, 180° phase-shift digital DLL with a window phase detector for LPDDR4 memory controllers.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Mahmoud Saadat, Boris Murmann	A 0.6 V-2.4 V input, fully integrated reconfigurable switched-capacitor DC-DC converter for energy harvesting sensor tags.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Sangyeun Cho	Fast memory and storage architectures for the big data era.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Haikun Jia, Baoyong Chi, Lixue Kuang, Wei Zhu, Zhiping Wang, Feng Ma, Zhihua Wang 0001	A frequency doubling two-path phased-array FMCW radar transceiver in 65nm CMOS.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Hyunki Kim, Kiseok Song, Taehwan Roh, Hoi-Jun Yoo	A 95% accurate EEG-connectome processor for a mental health monitoring system.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Kyoya Takano, Kosuke Katayama, Takeshi Yoshida, Shuhei Amakawa, Minoru Fujishima	124-GHz CMOS quadrature voltage-controlled oscillator with fundamental injection locking.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Toshihiro Ozaki, Tetsuya Hirose, Hiroki Asano, Nobutaka Kuroki, Masahiro Numa	A fully-integrated, high-conversion-ratio and dual-output voltage boost converter with MPPT for low-voltage energy harvesting.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Zhaoyang Weng, Shaoquan Gao, Jingjing Dong, Kai Yang, Hanjun Jiang, Fule Li, Zhihua Wang 0001, Yanqing Ning, Xinkai Chen	Dedicated ICs for wearable body sound monitoring.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Li-Yang Chen, Pen-Jui Peng, Chiro Kao, Yu-Lun Chen, Jri Lee	CW/FMCW/pulse radar engines for 24/26GHz multi-standard applications in 65nm CMOS.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Fengwei An, Keisuke Mihara, Shogo Yamazaki, Lei Chen 0001, Hans Jürgen Mattausch	Word-parallel associative memory for k-nearest-neighbor with configurable storage space of reference vectors.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Qixian Shi, Davide Guermandi, Jan Craninckx, Piet Wambacq	Flicker noise upconversion mechanisms in K-band CMOS VCOs.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Chia-Liang Tai, Alan Roth, Eric G. Soenen	A digital low drop-out regulator with wide operating range in a 16nm FinFET CMOS process.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Leo Li	IC challenges in 5G.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Jianwei Liu 0005, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins	A 89fJ-FOM 6-bit 3.4GS/s flash ADC with 4x time-domain interpolation.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Yang Zhao 0007, Jian Zhao 0004, Guo Ming Xia, An Ping Qiu, Yan Su, Xi Wang 0004, Yong Ping Xu	A 0.57°/h bias instability 0.067°/√h angle random walk MEMS gyroscope with CMOS readout circuit.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Yutao Wang, Zhangming Zhu, Jiaojiao Yao, Yintang Yang	A 0.45 V, 15.6 nW MOSFET-only sub-threshold voltage reference with no amplifiers.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Jiacheng Wang 0005, Wang Ling Goh, Xin Liu 0015, Jun Zhou 0017	A 12.77-MHz on-chip relaxation oscillator with digital compensation for loop delay variation.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Jan A. Angevare, Lorenzo Pedala, Ugur Sonmez, Fabio Sebastiano, Kofi A. A. Makinwa	A 2800-μm2 thermal-diffusivity temperature sensor with VCO-based readout in 160-nm CMOS.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Chung-Yu Wu, Chia-Shiung Ho	An 8-channel chopper-stabilized analog front-end amplifier for EEG acquisition in 65-nm CMOS.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Liang-Ting Kuo, Chun-Chih Hou, Meng-Hsuan Wu, Yun-Shiang Shu	A 1V 9pA analog front end with compressed sensing for electrocardiogram monitoring.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Yen-Ting Lin, Shin-Chi Lai, Shin-Hao Chen, Shen-Yu Peng, Ke-Horng Chen, Sheng Kang, Kevin Cheng 0002, Ying-Hsi Lin, Chen-Chih Huang, Chao-Cheng Lee	99.4% peak audio signal recovery rate and ultra-low 0.32dB matching error with 10Hz high resolution filter fitting wearable aided speech compensation system.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Zhichao Tan, Mick Mueck, Xiao Hong Du, Larry Getzin, Michael Guidry, Flow Zhao, Baoxing Chen	A fully isolated delta-sigma ADC for shunt based current sensing.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Nicholas Preyss, Christian Senning, Andreas Burg, Wei-Chang Liu, Chun-Yi Liu 0001, Shyh-Jye Jou	A 3.52 Gb/s mmWave baseband with delayed decision feedback sequence estimation in 40 nm.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Jingcheng Wang, Nathaniel Ross Pinckney, David T. Blaauw, Dennis Sylvester	Reconfigurable self-timed regenerators for wide-range voltage scaled interconnect.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Ronald Perez	Silicon systems security and building a root of trust.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Ka-Meng Lei, Pui-In Mak, Man-Kay Law, Rui Paulo Martins	A μNMR CMOS transceiver using a butterfly-coil input for integration with a digital microfluidic device inside a portable magnet.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Athanasios Sarafianos, Joachim Pichler, Christoph Sandner, Michiel Steyaert	A folding dickson-based fully integrated wide input range capacitive DC-DC converter achieving Vout/2-resolution and 71% average efficiency.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Babak Mohammadi, Joachim Neves Rodrigues	Ultra low energy and area efficient charge pump with automatic clock controller in 65 nm CMOS.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Tsun-Yuan Fan, Tsung-Yi Chou, Wen-Hua Chang	A 0.11mm⁁2 150mW 10GBase-T transmitter in 28nm CMOS process.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Injoon Hong, Seongwook Park, Junyoung Park 0002, Hoi-Jun Yoo	A 1.9nJ/pixel embedded deep neural network processor for high speed visual attention in a mobile vision recognition SoC.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Kok-Hin Teng, Tong Wu 0001, Zhi Yang 0002, Chun-Huat Heng, Xiayun Liu	A 400-MHz wireless neural signal processing IC with 625× on-chip data reduction and reconfigurable BFSK/QPSK transmitter based on sequential injection locking.	A-SSCC	2015	DBLP DOI BibTeX RDF
1		IEEE Asian Solid-State Circuits Conference, A-SSCC 2015, Xia'men, China, November 9-11, 2015	A-SSCC	2015	DBLP BibTeX RDF
1	Shon-Hang Wen, Chien-Ming Chen, Cheng-Chung Yang, Chieh-Hung Chen, Jia-Feng Jiang, Keng-Jan Hsiao, Cheng-Yu Chien	A 130dB PSRR, 108dB DR and 95dB SNDR, ground-referenced audio decoder with PSRR-enhanced load-adaptive Class-G 16Ohm headphone amplifiers.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Wouter Steyaert, Patrick Reynaert	A THz signal source with integrated antenna for non-destructive testing in 28nm bulk CMOS.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Zhao-yang Liu, Liyuan Liu, Jie Yang 0033, Nanjian Wu	A fully-integrated 860-GHz CMOS terahertz sensor.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Jui-Che Su, Wei-Chung Chen, Wei-Tin Lin, Ying-Wei Chou, Meng-Wei Chien, Chin-Long Wey, Ke-Horng Chen, Ying-Hsi Lin, Chao-Cheng Lee, Shian-Ru Lin, Tsung-Yen Tsai	Pseudo AC current synthesizer and DC offset-corrected technique in constant-on-time control buck converter for werable electronics.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Masahiko Maruyama, Shigenari Taguchi, Masafumi Yamanoue, Kunihiko Iizuka	A 24-bit multi-functional sensor analog front end employing low noise biasing technique with 8.2nV/√Hz input referred noise.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Chan-Hsiang Weng, Wei-Hsiang Huang, Erkan Alpman, Tsung-Hsien Lin	A 13-MHz 68-dB SNDR CTDSM using SAB loop filter and interpolating flash quantizer with random-skip IDWA function in 90-nm CMOS.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Sungwook Choi, KyuTae Park, Marco Passerini, HeeJoung Park, DoYoung Kim, ChiHyun Kim, Kunwoo Park, Jinwoong Kim	A cell current compensation scheme for 3D NAND FLASH memory.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Yang You, Sudipto Chakraborty, Rui Wang 0035, Jinghong Chen	A 21-Gb/s, 0.96-pJ/bit serial receiver with non-50% duty-cycle clocking 1-tap decision feedback equalizer in 65nm CMOS.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Hideto Hidaka	How future mobility meets IT: Cyber-physical system designs revisit semiconductor technology.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Chi-Huan Chiang, Chang-Cheng Huang, Shen-Iuan Liu	A digital bang-bang phase-locked loop with bandwidth calibration.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Gyu-Seob Jeong, Sang-Hyeok Chu, Yoonsoo Kim, Sungchun Jang, Sungwoo Kim, Woo-Rham Bae, Sung-Yong Cho, Haram Ju, Deog-Kyoon Jeong	A 20 Gb/s 0.4 pJ/b energy-efficient transmitter driver architecture utilizing constant Gm.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Daisaburo Takashima, Masato Endo, Kazuhiro Shimazaki, Manabu Sai, Masaaki Tanino	A 7T-SRAM with data-write technique by capacitive coupling.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Tomohiko Yano, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada	A calibration-free time difference accumulator using two pulses propagating on a single buffer ring.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Yoshisato Yokoyama, Yuichiro Ishii, Toshihiro Inada, Koji Tanaka, Miki Tanaka, Yoshiki Tsujihashi, Koji Nii	A cost effective test screening method on 40-nm 4-Mb embedded SRAM for low-power MCU.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Xiaoyang Zhang, Zhe Zhang 0008, Yongfu Li 0002, Changrong Liu, Yongxin Guo, Yong Lian 0001	A 2.89-μW clockless wireless dry-electrode ECG SoC for wearable sensors.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Sheng-Lyang Jang, Wen-Cheng Lai, Shune-Shing Tzeng, Ching-Wen Hsue	A wide-band divide-by-3 injection-locked frequency divider using tunable MOS resistor.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Dang Liu, Xiaofeng Liu, Woogeun Rhee, Zhihua Wang 0001	A 7.6mW 2Gb/s proximity transmitter for smartphone-mirrored display applications.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Wei-Hsin Tseng, Wei-Liang Lee, Chang-Yang Huang, Pao-Cheng Chiu	A 12-bit 104-MS/s SAR ADC in 28nm CMOS for digitally-assisted wireless transmitters.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Yi-Chieh Huang, Che-Fu Liang, Ping-Ying Wang	A 1V fractional-N PLL with nonlinearity-insensitive modulator.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Lei Yao, Peng Li, Minkyu Je	A pulse-width-adaptive active charge balancing circuit with pulse-insertion based residual charge compensation and quantization for electrical stimulation applications.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Ni Xu, Yiyu Shen, Sitao Lv, Woogeun Rhee, Zhihua Wang 0001	A spread-spectrum clock generator with FIR-embedded binary phase detection and 1-bit high-order ΔΣ modulation.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Woo-Rham Bae, Haram Ju, Kwanseo Park, Sung-Yong Cho, Deog-Kyoon Jeong	A 7.6 mW, 214-fs RMS jitter 10-GHz phase-locked loop for 40-Gb/s serial link transmitter based on two-stage ring oscillator in 65-nm CMOS.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Guansheng Li, Wooram Lee, Delong Cui, Bo Zhang 0029, Afshin Momtaz, Jun Cao 0001	Standing wave based clock distribution technique with application to a 10 × 11 Gbps transceiver in 28 nm CMOS.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Chen-Kai Hsu, Tai-Cheng Lee	A single-channel 10-b 400-MS/s 8.7-mW pipeline ADC in a 90-nm technology.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Hyeon-June Kim, Sun-Il Hwang, Ji-Wook Kwon, Dong-Hwan Jin, Byoung Soo Choi, Sang-Gwon Lee, Jong-Ho Park, Jang-Kyoo Shin, Seung-Tak Ryu	Delta readout scheme for image-dependent power savings in a CMOS image sensor with multi-column-parallel SAR ADCs.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Bertrand Parvais, Piet Wambacq, Abdelkarim Mercha, Diederik Verkest, Aaron Thean, Ken Sawada, Kazuki Nomoto, Tetsuya Oishi, Hiroaki Ammo	A digital intensive circuit for low-frequency noise monitoring in 28nm CMOS.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Zule Xu, Masaya Miyahara, Akira Matsuzawa	A 3.6 GHz fractional-N digital PLL using SAR-ADC-based TDC with-110 dBc/Hz in-band phase noise.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Sung-Yong Kim, Xuefan Jin, Jung-Hoon Chun, Kee-Won Kwon	A digital DLL with 4-cycle lock time and 1/4 NAND-delay accuracy.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Yong Wang 0026, Hui Wu 0007	A K-band pulse radar transceiver with highly digital closed-loop time-of-flight measurement.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Hideki Shinohara, Kousuke Miyaji	A ZVS CMOS active diode rectifier with voltage-time-conversion delay-locked loop for wireless power transmission.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Marco Vigilante, Patrick Reynaert	A 25-102GHz 2.81-5.64mW tunable divide-by-4 in 28nm CMOS.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Burak Erbagci, Fangfei Liu, Cagla Cakir, Nail Etkin Can Akkaya, Ruby B. Lee, Ken Mai	A 32kB secure cache memory with dynamic replacement mapping in 65nm bulk CMOS.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Pai-Yi Wang, Szu-Yu Huang, Kuan-Yu Fang, Tai-Haur Kuo	An undershoot/overshoot-suppressed current-mode buck converter with voltage-setting control for type-II compensator.	A-SSCC	2015	DBLP DOI BibTeX RDF
1	Yoshisato Yokoyama, Yuichiro Ishii, Koji Tanaka, Tatsuya Fukuda, Yoshiki Tsujihashi, Atsushi Miyanishi, Shinobu Asayama, Keiichi Maekawa, Kazutoshi Shiba, Koji Nii	40 nm Dual-port and two-port SRAMs for automotive MCU applications under the wide temperature range of -40 to 170°C with test screening against write disturb issues.	A-SSCC	2014	DBLP DOI BibTeX RDF
1	Wenfeng Zhao, Rui Pan, Yajun Ha, Zhi Yang	A 0.4V 280-nW frequency reference-less nearly all-digital hybrid domain temperature sensor.	A-SSCC	2014	DBLP DOI BibTeX RDF
1	Kensuke Nakajima, Akihiro Maruyama, Masato Kohtani, Tsuyoshi Sugiura, Eiichiro Otobe, Jaejin Lee, Shinhee Cho, Kyusub Kwak, Jeongseok Lee, Toshihiko Yoshimasu, Minoru Fujishima	23Gbps 9.4pJ/bit 80/100GHz band CMOS transceiver with on-board antenna for short-range communication.	A-SSCC	2014	DBLP DOI BibTeX RDF
1	Jian Hong Jiang, Samir Parikh, Mark Lionbarger, Nikola Nedovic, Takuji Yamamoto	A DC-46Gb/s 2: 1 multiplexer and source-series terminated driver in 20nm CMOS technology.	A-SSCC	2014	DBLP DOI BibTeX RDF
1	Shita Guo, Tianzuo Xi, Ping Gui, Jing Zhang, Wooyeol Choi 0001, Kenneth K. O, Yanli Fan, Daquan Huang, Richard Gu, Mark Morgan	54 GHz CMOS LNAs with 3.6 dB NF and 28.2 dB gain using transformer feedback Gm-boosting technique.	A-SSCC	2014	DBLP DOI BibTeX RDF
1	Yi Zhang 0023, Chia-Hung Chen, Tao He 0001, Xin Meng, Nancy Qian, Ed Liu, Phillip Elliott, Gabor C. Temes	A 1 V 59 fJ/Step 15 MHz BW 74 dB SNDR continuous-time ΔΣ modulator with digital ELD compensation and multi-bit FIR feedback.	A-SSCC	2014	DBLP DOI BibTeX RDF
1	Kai-Hsiang Chiang, Soon-Jyh Chang, Guan-Ying Huang, Ying-Zu Lin	A 10b 100kS/s SAR ADC with charge recycling switching method.	A-SSCC	2014	DBLP DOI BibTeX RDF
1	Yifan YangGong, Sebastian Turullols, Daniel Woo, Changku Huang, King C. Yen, Venkatram Krishnaswamy, Kalon Holdbrook, Jinuk Luke Shin	Asymmetric Frequency Locked Loop (AFLL) for adaptive clock generation in a 28nm SPARC M6 processor.	A-SSCC	2014	DBLP DOI BibTeX RDF
1	Hiroyuki Ohshima	Mobile display technologies: Past, present and future.	A-SSCC	2014	DBLP DOI BibTeX RDF
1	Tzi-Dar Chiueh, Toru Shimizu, Gregory Chen, Chen-Yi Lee, Charles Hsu, Tihao Chiang, Zhihua Wang 0001, Junghwan Choi, Jongwoo Lee, Yasumoto Tomita, Takayuki Kawahara	What is a good way to expand a silicon value to a solution value?	A-SSCC	2014	DBLP DOI BibTeX RDF
1	Li-Hung Chiueh, Tai-Cheng Lee	A 6-Gb/s adaptive-loop-bandwidth clock and data recovery (CDR) circuit.	A-SSCC	2014	DBLP DOI BibTeX RDF
1	Yousr Ismail, Chih-Kong Ken Yang	A 12-V charge pump-based square wave driver in 65-nm CMOS technology.	A-SSCC	2014	DBLP DOI BibTeX RDF

Publications at "A-SSCC"( http://dblp.L3S.de/Venues/A-SSCC )