Search results for "ASP-DAC"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Pedro Benedicte, Jaume Abella 0001, Carles Hernández 0001, Enrico Mezzetti, Francisco J. Cazorla	Towards limiting the impact of timing anomalies in complex real-time processors.	ASP-DAC	2019	DBLP DOI BibTeX RDF
1	Chuhan Min, Jiachen Mao, Hai Li 0001, Yiran Chen 0001	NeuralHMC: an efficient HMC-based accelerator for deep neural networks.	ASP-DAC	2019	DBLP DOI BibTeX RDF
1	Cunxi Yu, Tiankai Su, Atif Yasin, Maciej J. Ciesielski	Spectral approach to verifying non-linear arithmetic circuits.	ASP-DAC	2019	DBLP DOI BibTeX RDF
1	S. Rasoul Faraji, Kia Bazargan	Hybrid binary-unary hardware accelerator.	ASP-DAC	2019	DBLP DOI BibTeX RDF
1	Bing Li 0017, Bonan Yan, Chenchen Liu, Hai (Helen) Li	Build reliable and efficient neuromorphic design with memristor technology.	ASP-DAC	2019	DBLP DOI BibTeX RDF
1	Sheng Xu, Xiaoming Chen 0003, Ying Wang 0001, Yinhe Han 0001, Xiaowei Li 0001	CuckooPIM: an efficient and less-blocking coherence mechanism for processing-in-memory systems.	ASP-DAC	2019	DBLP DOI BibTeX RDF
1	Mason Chern, Shih-Wei Lee, Shi-Yu Huang, Yu Huang 0005, Gaurav Veda, Kun-Han Hans Tsai, Wu-Tung Cheng	Improving scan chain diagnostic accuracy using multi-stage artificial neural networks.	ASP-DAC	2019	DBLP DOI BibTeX RDF
1	Hsuan-Hsuan Hsiao, Hong-Wen Chiou, Yu-Min Lee	Multi-angle bended heat pipe design using x-architecture routing with dynamic thermal weight on mobile devices.	ASP-DAC	2019	DBLP DOI BibTeX RDF
1	Pu Zhao 0001, Kaidi Xu, Sijia Liu 0001, Yanzhi Wang, Xue Lin	ADMM attack: an enhanced adversarial attack for deep neural networks with undetectable distortions.	ASP-DAC	2019	DBLP DOI BibTeX RDF
1	Shih-Yu Chen, Jie-Hong R. Jiang, Shou-Hung Welkin Ling, Shih-Hao Liang, Mao-Cheng Huang	An approximation algorithm to the optimal switch control of reconfigurable battery packs.	ASP-DAC	2019	DBLP DOI BibTeX RDF
1	Wen Li, Ying Wang 0001, Huawei Li 0001, Xiaowei Li 0001	P3M: a PIM-based neural network model protection scheme for deep learning accelerator.	ASP-DAC	2019	DBLP DOI BibTeX RDF
1	Xianwei Zhang, Rujia Wang, Youtao Zhang, Jun Yang 0002	Boosting chipkill capability under retention-error induced reliability emergency.	ASP-DAC	2019	DBLP DOI BibTeX RDF
1	Gengjie Chen, Chak-Wa Pui, Haocheng Li, Jingsong Chen, Bentian Jiang, Evangeline F. Y. Young	Detailed routing by sparse grid graph and minimum-area-captured path search.	ASP-DAC	2019	DBLP DOI BibTeX RDF
1	Hyeon Uk Sim, Jason Helge Anderson, Jongeun Lee	XOMA: exclusive on-chip memory architecture for energy-efficient deep learning acceleration.	ASP-DAC	2019	DBLP DOI BibTeX RDF
1	Zhuwei Qin, Fuxun Yu, Chenchen Liu, Xiang Chen 0010	CAPTOR: a class adaptive filter pruning framework for convolutional neural networks in mobile applications.	ASP-DAC	2019	DBLP DOI BibTeX RDF
1	Xingquan Li, Bei Yu 0001, Jianli Chen, Wenxing Zhu	A local optimal method on DSA guiding template assignment with redundant/dummy via insertion.	ASP-DAC	2019	DBLP DOI BibTeX RDF
1	Ryosuke Matsuo, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi	BDD-based synthesis of optical logic circuits exploiting wavelength division multiplexing.	ASP-DAC	2019	DBLP DOI BibTeX RDF
1	Yuanqi Shen, You Li, Amin Rezaei 0001, Shuyu Kong, David Dlott, Hai Zhou 0001	BeSAT: behavioral SAT-based attack on cyclic logic encryption.	ASP-DAC	2019	DBLP DOI BibTeX RDF
1	Bo-Yi Yu, Yong Zhong, Shao-Yun Fang, Hung-Fei Kuo	Deep learning-based framework for comprehensive mask optimization.	ASP-DAC	2019	DBLP DOI BibTeX RDF
1	Tung-Che Liang, Yun-Sheng Chan, Tsung-Yi Ho, Krishnendu Chakrabarty, Chen-Yi Lee	Sample preparation for multiple-reactant bioassays on micro-electrode-dot-array biochips.	ASP-DAC	2019	DBLP DOI BibTeX RDF
1	Guohao Dai, Tianhao Huang, Yu Wang 0002, Huazhong Yang, John Wawrzynek	GraphSAR: a sparsity-aware processing-in-memory architecture for large-scale graph processing on ReRAMs.	ASP-DAC	2019	DBLP DOI BibTeX RDF
1	Dawen Xu 0002, Li Li, Ying Wang 0001, Cheng Liu 0008, Huawei Li 0001	Exploring emerging CNFET for efficient last level cache design.	ASP-DAC	2019	DBLP DOI BibTeX RDF
1	Hong-Wen Chiou, Yu-Min Lee, Shin-Yu Shiau, Chi-Wen Pan, Tai-Yu Chen	Phone-nomenon: a system-level thermal simulator for handheld devices.	ASP-DAC	2019	DBLP DOI BibTeX RDF
1	Alwin Zulehner, Michael P. Frank, Robert Wille	Design automation for adiabatic circuits.	ASP-DAC	2019	DBLP DOI BibTeX RDF
1	Daewoo Kim, Sugil Lee, Jongeun Lee	On-chip memory optimization for high-level synthesis of multi-dimensional data on FPGA.	ASP-DAC	2019	DBLP DOI BibTeX RDF
1	Yinghui Fan, Xiaoxi Wu, Jiying Dong, Zhi Qi	AxDNN: towards the cross-layer design of approximate DNNs.	ASP-DAC	2019	DBLP DOI BibTeX RDF
1	Hyungjun Kim, Yulhwa Kim, Jae-Joon Kim	In-memory batch-normalization for resistive memory based binary neural network hardware.	ASP-DAC	2019	DBLP DOI BibTeX RDF
1	Atsuki Kobayashi, Yuya Nishio, Kenya Hayashi, Shigeki Arata, Kiichi Niitsu	Design of gate-leakage-based timer using an amplifier-less replica-bias switching technique in 55-nm DDC CMOS.	ASP-DAC	2019	DBLP DOI BibTeX RDF
1	Taiki Nakanishi, Maya Matsunaga, Shunya Murakami, Atsuki Kobayashi, Kiichi Niitsu	A 65-nm CMOS fully-integrated circulating tumor cell and exosome analyzer using an on-chip vector network analyzer and a transmission-line-based detection window.	ASP-DAC	2019	DBLP DOI BibTeX RDF
1	Shaahin Angizi, Zhezhi He, Deliang Fan	ParaPIM: a parallel processing-in-memory accelerator for binary-weight deep neural networks.	ASP-DAC	2019	DBLP DOI BibTeX RDF
1	Mengyun Liu, Lixue Xia, Yu Wang 0002, Krishnendu Chakrabarty	Fault tolerance in neuromorphic computing systems.	ASP-DAC	2019	DBLP DOI BibTeX RDF
1	Mohsen Imani, Sahand Salamat, Saransh Gupta, Jiani Huang, Tajana Rosing	FACH: FPGA-based acceleration of hyperdimensional computing by reducing computational complexity.	ASP-DAC	2019	DBLP DOI BibTeX RDF
1	Mateus Fogaça, Andrew B. Kahng, Ricardo Reis 0001, Lutong Wang	Finding placement-relevant clusters with fast modularity-based clustering.	ASP-DAC	2019	DBLP DOI BibTeX RDF
1	Jiajun Li, Ying Wang 0001, Bosheng Liu, Yinhe Han 0001, Xiaowei Li 0001	Simulate-the-hardware: training accurate binarized neural networks for low-precision neural accelerators.	ASP-DAC	2019	DBLP DOI BibTeX RDF
1	Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler	Maximizing power state cross coverage in firmware-based power management.	ASP-DAC	2019	DBLP DOI BibTeX RDF
1	Wei Ye 0008, Yibo Lin, Meng Li 0004, Qiang Liu 0001, David Z. Pan	LithoROC: lithography hotspot detection with explicit ROC optimization.	ASP-DAC	2019	DBLP DOI BibTeX RDF
1	Gereon Onnebrink, Ahmed Hallawa, Rainer Leupers, Gerd Ascheid, Awaid-Ud-Din Shaheen	A heuristic for multi objective software application mappings on heterogeneous MPSoCs.	ASP-DAC	2019	DBLP DOI BibTeX RDF
1	Jinshan Yue, Yongpan Liu, Fang Su, Shuangchen Li, Zhe Yuan, Zhibo Wang 0004, Wenyu Sun, Xueqing Li, Huazhong Yang	AERIS: area/energy-efficient 1T2R ReRAM based processing-in-memory neural network system-on-a-chip.	ASP-DAC	2019	DBLP DOI BibTeX RDF
1	Nimesh Shah, Manaar Alam, Durga Prasad Sahoo, Debdeep Mukhopadhyay, Arindam Basu	A 0.16pJ/bit recurrent neural network based PUF for enhanced machine learning attack resistance.	ASP-DAC	2019	DBLP DOI BibTeX RDF
1	Kiichi Niitsu, Yuuki Yamaji, Atsuki Kobayashi, Kazuo Nakazato	A low-voltage CMOS electrophoresis IC using electroless gold plating for small-form-factor biomolecule manipulation.	ASP-DAC	2019	DBLP DOI BibTeX RDF
1	Wenbin Xu, Lang Feng, Jeyavijayan Rajendran, Jiang Hu	Layout recognition attacks on split manufacturing.	ASP-DAC	2019	DBLP DOI BibTeX RDF
1	Ashkan Vakil, Houman Homayoun, Avesta Sasan	IR-ATA: IR annotated timing analysis, a flow for closing the loop between PDN design, IR analysis & timing closure.	ASP-DAC	2019	DBLP DOI BibTeX RDF
1	Zheng Zhao 0003, Derong Liu 0002, Meng Li 0004, Zhoufeng Ying, Lu Zhang, Biying Xu, Bei Yu 0001, Ray T. Chen, David Z. Pan	Hardware-software co-design of slimmed optical neural networks.	ASP-DAC	2019	DBLP DOI BibTeX RDF
1	Sun ik Heo, Andrew B. Kahng, Minsoo Kim, Lutong Wang	Diffusion break-aware leakage power optimization and detailed placement in sub-10nm VLSI.	ASP-DAC	2019	DBLP DOI BibTeX RDF
1	Yi Cao, Andrew B. Kahng, Joseph Li, Abinash Roy, Vaishnav Srinivas, Bangqi Xu	Learning-based prediction of package power delivery network quality.	ASP-DAC	2019	DBLP DOI BibTeX RDF
1	Neil Veira, Zissis Poulos, Andreas G. Veneris	Suspect2vec: a suspect prediction model for directed RTL debugging.	ASP-DAC	2019	DBLP DOI BibTeX RDF
1	Bruno de O. Schmitt, Alan Mishchenko, Robert K. Brayton	SAT-based area recovery in structural technology mapping.	ASP-DAC	2018	DBLP DOI BibTeX RDF
1	Yuanjing Shi, Zhaoyan Shen, Zili Shao	SQLiteKV: An efficient LSM-tree-based SQLite-like database engine for mobile devices.	ASP-DAC	2018	DBLP DOI BibTeX RDF
1	Byung-Su Kim, Joon-Sung Yang	System level performance analysis and optimization for the adaptive clocking based multi-core processor.	ASP-DAC	2018	DBLP DOI BibTeX RDF
1	Dongin Kim, SeongHwan Cho	A supply noise insensitive PLL with a rail-to-rail swing ring oscillator and a wideband noise suppression loop.	ASP-DAC	2018	DBLP DOI BibTeX RDF
1	Leilai Shao, Tsung-Ching Huang, Ting Lei, Zhenan Bao, Raymond G. Beausoleil, Kwang-Ting Cheng	Process design kit for flexible hybrid electronics.	ASP-DAC	2018	DBLP DOI BibTeX RDF
1	Necati Uysal, Rickard Ewetz	OCV guided clock tree topology reconstruction.	ASP-DAC	2018	DBLP DOI BibTeX RDF
1	Matthias Becker 0004, Saad Mubeen, Dakshina Dasari, Moris Behnam, Thomas Nolte	Scheduling multi-rate real-time applications on clustered many-core architectures with memory constraints.	ASP-DAC	2018	DBLP DOI BibTeX RDF
1	Atul Prasad Deb Nath, Sandip Ray, Abhishek Basak, Swamp Bhunia	System-on-chip security architecture and CAD framework for hardware patch.	ASP-DAC	2018	DBLP DOI BibTeX RDF
1	Pu Zhao 0001, Yanzhi Wang, Naehyuck Chang, Qi Zhu 0002, Xue Lin	A deep reinforcement learning framework for optimizing fuel economy of hybrid electric vehicles.	ASP-DAC	2018	DBLP DOI BibTeX RDF
1	Yongsun Lee, Taeho Seong, Seyeon Yoo, Jaehyouk Choi	A switched-loop-filter PLL with fast phase-error correction technique.	ASP-DAC	2018	DBLP DOI BibTeX RDF
1	Hossein Sayadi, Divya Pathak, Ioannis Savidis, Houman Homayoun	Power conversion efficiency-aware mapping of multithreaded applications on heterogeneous architectures: A comprehensive parameter tuning.	ASP-DAC	2018	DBLP DOI BibTeX RDF
1	Fan Chen 0001, Zheng Li, Wang Kang 0001, Weisheng Zhao, Hai Li 0001, Yiran Chen 0001	Process variation aware data management for magnetic skyrmions racetrack memory.	ASP-DAC	2018	DBLP DOI BibTeX RDF
1	Vikkitharan Gnanasambandapillai, Arash Bayat, Sri Parameswaran	MESGA: An MPSoC based embedded system solution for short read genome alignment.	ASP-DAC	2018	DBLP DOI BibTeX RDF
1	Sunmean Kim, Taeho Lim, Seokhyeong Kang	An optimal gate design for the synthesis of ternary logic circuits.	ASP-DAC	2018	DBLP DOI BibTeX RDF
1	Meng Li 0004, Bei Yu 0001, Yibo Lin, Xiaoqing Xu, Wuxi Li, David Z. Pan	A practical split manufacturing framework for Trojan prevention via simultaneous wire lifting and cell insertion.	ASP-DAC	2018	DBLP DOI BibTeX RDF
1	Fan Chen 0001, Linghao Song, Yiran Chen 0001	ReGAN: A pipelined ReRAM-based accelerator for generative adversarial networks.	ASP-DAC	2018	DBLP DOI BibTeX RDF
1	Rui Wu 0008, M. Ashkan Seyedi, Yuyang Wang 0003, Jared Hulme, Marco Fiorentino, Raymond G. Beausoleil, Kwang-Ting Cheng	Pairing of microring-based silicon photonic transceivers for tuning power optimization.	ASP-DAC	2018	DBLP DOI BibTeX RDF
1	Hao-Yu Chi, Hwa-Yi Tseng, Chien-Nan Jimmy Liu, Hung-Ming Chen	Performance-preserved analog routing methodology via wire load reduction.	ASP-DAC	2018	DBLP DOI BibTeX RDF
1	Andrew B. Kahng	New directions for learning-based IC design tools and methodologies.	ASP-DAC	2018	DBLP DOI BibTeX RDF
1	Xizi Chen, Jingbo Jiang, Jingyang Zhu, Chi-Ying Tsui	A high-throughput and energy-efficient RRAM-based convolutional neural network using data encoding and dynamic quantization.	ASP-DAC	2018	DBLP DOI BibTeX RDF
1	Alwin Zulehner, Robert Wille	Exploiting coding techniques for logic synthesis of reversible circuits.	ASP-DAC	2018	DBLP DOI BibTeX RDF
1	Kyeong-min Park, Joohyeb Song, Franklin Bien	Highly sensitive fingerprint readout IC for glass-covered mutual capacitive fingerprint sensor.	ASP-DAC	2018	DBLP DOI BibTeX RDF
1	Junmin Jiang, Wing-Hung Ki, Yan Lu 0002	A digital SC converter with high efficiency and low voltage ripple.	ASP-DAC	2018	DBLP DOI BibTeX RDF
1	Youngwoo Ji, Cheonhoo Jeon, Hyunwoo Son, Byungsub Kim, Hong-June Park, Jae-Yoon Sim	A 9.3 nW all-in-one bandgap voltage and current reference circuit using leakage-based PTAT generation and DIBL characteristic.	ASP-DAC	2018	DBLP DOI BibTeX RDF
1	David M. Moore, Jeffrey A. Fredenburgh, Muhammad Faisal, David D. Wentzloff	Static timing analysis for ring oscillators.	ASP-DAC	2018	DBLP DOI BibTeX RDF
1	Wenxuan Wang, Aijiao Cui, Gang Qu 0001, Huawei Li 0001	A low-overhead PUF based on parallel scan design.	ASP-DAC	2018	DBLP DOI BibTeX RDF
1	Chuan Yean Tan, Rickard Ewetz, Cheng-Kok Koh	Clustering of flip-flops for useful-skew clock tree synthesis.	ASP-DAC	2018	DBLP DOI BibTeX RDF
1	Zhongyuan Tian, Zhe Wang 0003, Haoran Li 0002, Peng Yang 0003, Rafael Kioji Vivas Maeda, Jiang Xu 0001	Multi-device collaborative management through knowledge sharing.	ASP-DAC	2018	DBLP DOI BibTeX RDF
1	Canran Jin, Heming Sun, Shinji Kimura	Sparse ternary connect: Convolutional neural networks using ternarized weights with enhanced sparsity.	ASP-DAC	2018	DBLP DOI BibTeX RDF
1	Christian Pilato, Luca P. Carloni	DarkMem: Fine-grained power management of local memories for accelerators in embedded systems.	ASP-DAC	2018	DBLP DOI BibTeX RDF
1	Jeff Burns	Keynote I: "Designing heterogeneous systems in the AI era: Challenges and opportunities".	ASP-DAC	2018	DBLP DOI BibTeX RDF
1	Tian Wang, Xiaoxin Cui, Dunshan Yu, Omid Aramoon, Timothy Dunlap, Gang Qu 0001, Xiaole Cui	Polymorphic gate based IC watermarking techniques.	ASP-DAC	2018	DBLP DOI BibTeX RDF
1	Barend Harris, Mansureh S. Moghaddam, Duseok Kang, Inpyo Bae, Euiseok Kim, Hyemi Min, Hansu Cho, Sukjin Kim, Bernhard Egger 0002, Soonhoi Ha, Kiyoung Choi	Architectures and algorithms for user customization of CNNs.	ASP-DAC	2018	DBLP DOI BibTeX RDF
1	Tongxin Yang, Tomoaki Ukezono, Toshinori Sato	A low-power high-speed accuracy-controllable approximate multiplier design.	ASP-DAC	2018	DBLP DOI BibTeX RDF
1	Hong-Thu Nguyen, Xuan-Thuan Nguyen, Cong-Kha Pham	An efficient fixed-point arithmetic processor using a hybrid CORDIC algorithm.	ASP-DAC	2018	DBLP DOI BibTeX RDF
1	Enes Eken, Ismail Bayram, Hai Helen Li, Yiran Chen 0001	Modeling of biaxial magnetic tunneling junction for multi-level cell STT-RAM realization.	ASP-DAC	2018	DBLP DOI BibTeX RDF
1	Wenyu Sun, Yuxuan Huang, Qinghang Zhao, Fei Qiao, Tsung-Yi Ho, Xiaojun Guo, Huazhong Yang, Yongpan Liu	Mechanical strain and temperature aware design methodology for thin-film transistor based pseudo-CMOS logic array.	ASP-DAC	2018	DBLP DOI BibTeX RDF
1	Shuyan Jiang, Qiong Wu, Shuyu Chen, Junshi Wang, Masoumeh Ebrahimi, Letian Huang, Qiang Li 0021	Optimizing dynamic mapping techniques for on-line NoC test.	ASP-DAC	2018	DBLP DOI BibTeX RDF
1	Sina Boroumand, Hadi Parandeh-Afshar, Philip Brisk, Siamak Mohammadi	Exploration of approximate multipliers design space using carry propagation free compressors.	ASP-DAC	2018	DBLP DOI BibTeX RDF
1	Daijoon Hyun, Youngsoo Shin	Automatic insertion of airgap with design rule constraints.	ASP-DAC	2018	DBLP DOI BibTeX RDF
1	Mingxi Cheng, Ji Li 0006, Shahin Nazarian	DRL-cloud: Deep reinforcement learning-based resource provisioning and task scheduling for cloud service providers.	ASP-DAC	2018	DBLP DOI BibTeX RDF
1	Xiaoyu Sun 0001, Xiaochen Peng, Pai-Yu Chen, Rui Liu 0005, Jae-sun Seo, Shimeng Yu	Fully parallel RRAM synaptic array for implementing binary neural network with (+1, -1) weights and (+1, 0) neurons.	ASP-DAC	2018	DBLP DOI BibTeX RDF
1	Dong-Soo Lee, Sung-Jin Kim, SeongJin Oh, Gyusub Won, Thi Kim Nga Truong, Imran Ali, Hamed Abbasizadeh, Behnam Samadpoor Rikan, Kang-Yoon Lee	Low power FSK transceiver using ADPLL with direct modulation and integrated SPDT for BLE application.	ASP-DAC	2018	DBLP DOI BibTeX RDF
1	Zhifeng Zhang, Dajiang Zhou, Shihao Wang, Shinji Kimura	Quad-multiplier packing based on customized floating point for convolutional neural networks on FPGA.	ASP-DAC	2018	DBLP DOI BibTeX RDF
1	Shaahin Angizi, Zhezhi He, Farhana Parveen, Deliang Fan	IMCE: Energy-efficient bit-wise in-memory convolution engine for deep neural network.	ASP-DAC	2018	DBLP DOI BibTeX RDF
1	Zhufei Chu, Mathias Soeken, Yinshui Xia, Giovanni De Micheli	Functional decomposition using majority.	ASP-DAC	2018	DBLP DOI BibTeX RDF
1	Xiaoxiao Liu 0001, Wei Wen, Xuehai Qian, Hai Li 0001, Yiran Chen 0001	Neu-NoC: A high-efficient interconnection network for accelerated neuromorphic systems.	ASP-DAC	2018	DBLP DOI BibTeX RDF
1	Gabriel Cadilha Marques, Farhan Rasheed, Jasmin Aghassi-Hagmann, Mehdi Baradaran Tahoori	From silicon to printed electronics: A coherent modeling and design flow approach based on printed electrolyte gated FETs.	ASP-DAC	2018	DBLP DOI BibTeX RDF
1	Chenguang Wang 0003, Yici Cai, Qiang Zhou 0001	HLIFT: A high-level information flow tracking method for detecting hardware Trojans.	ASP-DAC	2018	DBLP DOI BibTeX RDF
1	Younghyun Lim, Jeonghyun Lee, Suneui Park, Jaehyouk Choi	An external-capacitor-less high-PSR low-dropout regulator using an adaptive supply-ripple cancellation technique to the body-gate.	ASP-DAC	2018	DBLP DOI BibTeX RDF
1	Qi Nie, Sharad Malik	MemFlow: Memory-driven data scheduling with datapath co-design in accelerators for large-scale inference applications.	ASP-DAC	2018	DBLP DOI BibTeX RDF
1	Kaiwei Zou, Ying Wang 0001, Huawei Li 0001, Xiaowei Li 0001	XORiM: A case of in-memory bit-comparator implementation and its performance implications.	ASP-DAC	2018	DBLP DOI BibTeX RDF
1	Boyu Zhang 0001, Azadeh Davoodi, Yu Hen Hu	Exploring energy and accuracy tradeoff in structure simplification of trained deep neural networks.	ASP-DAC	2018	DBLP DOI BibTeX RDF
1	Oh-Yong Jung, Hyun-Gi Seok, Anjana Dissanayake, Sang-Gug Lee 0001	A 2.4GHz, -102dBm-sensitivity, 25kb/s, 0.466mW interference resistant BFSK multi-channel sliding-IF ULP receiver.	ASP-DAC	2018	DBLP DOI BibTeX RDF

Publications at "ASP-DAC"( http://dblp.L3S.de/Venues/ASP-DAC )