Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
1 | Peter Gutberlet, Heinrich Krämer, Wolfgang Rosenstiel |
CASCH: a scheduling algorithm for "high level"-synthesis. |
EURO-DAC |
1991 |
DBLP BibTeX RDF |
|
1 | Akhilesh Tyagi |
An algebraic model for design space with applications to function module generation. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | Hans Eveking, Christoph Mai |
Formal verification of timing conditions. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | Hélène Collavizza |
Functional semantics of microprocessors at the microprogram level and correspondence with the machine instruction level. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | Carlo Marazzini, Mauro Santomauro, Michele Taliercio |
CIRCE: a program for parasitic parameter extraction. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | H. Warmers, D. Sass, Ernst-Helmut Horneber |
Switch-level timing models in the MOS simulator BRASIL. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | Steve Hodgson, Len Theobald, W. B. Hughes, Richard Illman |
ASTA: an integrated system for bist analysis & automatic test generation. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | Tomás Pérez Segovia, Anne-Françoise Joanblanq |
CACTUS: a symbolic CMOS two-dimensional compactor. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | Bernd Becker 0001, Thomas Burch, Günter Hotz, D. Kiel, Reiner Kolla, Paul Molitor, Hans-Georg Osthof, Gisela Pitsch, Uwe Sparmann |
A graphical system for hierarchical specifications and checkups of VLSI circuits. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | Frédéric Mailhot 0001, Giovanni De Micheli |
Technology mapping using boolean matching and don't care sets. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | Bruno Poterie |
Storage mechanism for VHDL intermediate form. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | Ankan K. Pramanick, Sudhakar M. Reddy |
On the fault coverage of delay fault detecting tests. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | Olivier Coudert, Christian Berthet, Jean Christophe Madre |
Formal boolean manipulations for the verification of sequential machines. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | Christian Masson, Denis Barbier, Remy Escassut, Daniel Winer, Gregory Chevallier, Pierre François Zeegers |
CHEOPS: an integrated VLSI floor planning and chip assembly system implemented in object oriented LISP. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | H. J. Kappen, F. M. J. de Bont |
An efficient placement method for large standard-cell and sea-of-gates designs. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
optimization, Quadratic Assignment Problem, recursive partitioning, Standard Cell placement |
1 | Werner Grass |
A branch-and-bound method for optimal transformation of data flow graphs for observing hardware constraints. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | F. Darlay, Bernard Courtois |
Robust tests for stuck-open faults and design for testability of reconvergent fan-out CMOS logic networks. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | Thomas Kathöfer, W. Fox, D. Nolte, K. Pielsticker, R. Quester, F. Rupprecht, M. Schrewe |
A database interface for phased tool integration. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | Reiner Kolla |
A dynamic programming approach to the power supply net sizing problem. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | Marie-Lise Flottes, Christian Landrault, Serge Pravossoudovitch |
Fault modelling and fault equivalence in CMOS technology. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
Fault modelling, Test pattern generation, Fault collapsing |
1 | Neerav Berry, Barry M. Pangrle |
SCHALLOC: an algorithm for simultaneous scheduling & connectivity binding in a datapath synthesis system. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | Peter Marwedel |
Matching system and component behaviour in MIMOLA synthesis tools. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | Paolo Camurati, Antonio Lioy, Paolo Prinetto, Matteo Sonza Reorda |
Diagnosis oriented test pattern generation. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | R. Burgess, C. Wouters |
PARAGON: a new package for gate matrix layout synthesis. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
cell generation, gate-matrix layout, routing, simulated annealing, optimisation, placement, logic synthesis, physical design |
1 | F. Theeuwen |
Logic optimization on a concurrent processing computer. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | Raul Camposano, Reinaldo A. Bergamaschi |
Redesign using state splitting. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | M. T. van Stiphout, Jos T. J. van Eijndhoven, H. W. Buurman |
PLATO: a new piecewise linear simulation tool. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | M. Y. Yu, Xiaoyan Hong, Y. E. Lien, Z. Z. Ma, J. G. Bo, W. J. Zhuang |
A new clustering approach and its application to BBL placement. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | Noritake Yonezawa, Nobuyuki Nishiguchi, Atsushi Etani, Fumiaki Tsukuda, Ryuichi Hashishita |
A VLSI floorplanner based on "balloon" expansion. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | Arvind Srinivasan 0004, Ernest S. Kuh |
MOLE: a sea-of-gates detailed router. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
physical design, global routing, detailed routing |
1 | T. C. O. Young, Hilary J. Kahn |
A procedural interface to CAD data based on EDIF. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | Daniele D. Caviglia, Giacomo M. Bisio, Francesco Curatelli, L. Giovannacci, Luigi Raffo |
Pre-placement of VLSI blocks through learning neural networks. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
Neural Net Models, Placement, Optimization Techniques |
1 | Tuomo Tikkanen, Timo Lappänen, Jorma Kivelä |
Structured analysis and VHDL in embedded ASIC design and verification. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | Jaan Haabma, Bernd Steinmüller |
The NMP-CADLAB framework: a common framework for tool integration and development. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | Rene David, S. Rahal, J. L. Rainard |
Some relationships between delay testing and stuck-open testing in CMOS circuits. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
stuck-open, combinational circuits, CMOS, Delay testing, robust test |
1 | Kevin McCullen, John Thorvaldson, David Demaris, Patrick Lampin |
A system for floorplanning with hierarchical placement and wiring. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | Mikael R. K. Patel |
A design representation for high level synthesis. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
Data Structures, High Level Synthesis, Design Automation, Design Representation |
1 | Pieter van der Wolf, Peter Bingley, Patrick M. Dewilde |
On the architecture of a CAD framework: the NELSIS approach. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | Ahmed Hemani, Adam Postula |
A neural net based self organising scheduling algorithm. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
Behavioural Synthesis, Scheduling, Neural Nets, Self Organisation, Optimisation Techniques |
1 | Mattie N. Sim, Patrick M. Dewilde |
An object-oriented persistent database interface for CAD. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | João Paulo Teixeira 0001, Isabel C. Teixeira, Carlos F. Beltrán Almeida, Fernando M. Gonçalves, Júlio Gonçalves, R. Crespo |
A strategy for testability enhancement at layout level. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | Rolf Ernst, S. Sutarwala, J.-Y. Jou, M. Tong |
Simulation based verification of register-transfer level behavioral synthesis tools. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | M. Razaz, J. Gan |
Fuzzy set based initial placement for IC layout. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | Dirk Lanneer, Francky Catthoor, Gert Goossens, Marc Pauwels, Jef L. van Meerbergen, Hugo De Man |
Open-ended system for high-level synthesis of flexible signal processors. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | M. Pipponzi, Fabio Somenzi |
An iterative algorithm for the binate covering problem. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | Keith R. Dimond, Samir Hassan |
An incremental functional simulator implemented on a network of transputers. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | Xianjin Yao, C. L. Liu 0001 |
Solution of a module orientation and rotation problem. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | Pedro Reis dos Santos, Helena Sarmento, Luís M. Vidigal |
Ghost/Spook: user interface and process management in the PACE framework. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | David T. Blaauw, Daniel G. Saab, Junsheng Long, Jacob A. Abraham |
Derivation of signal flow for switch-level simulation. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | Gordon F. Taylor |
Design to test migration: a tester and a simulator. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | D. Patrick, Colin Lyden |
An event-driven transient simulation algorithm for MOS and bipolar circuits. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | G. W. Sloof, Peter Bingley, Patrick M. Dewilde, T. G. R. M. van Leuken, Pieter van der Wolf |
Design data management in a distributed hardware environment. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | Antoine Delaruelle, O. McArdle, Jef L. van Meerbergen, Cees Niessen |
Synthesis of delay functions in DSP compilers. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | Jos T. J. van Eijndhoven, M. T. van Stiphout, H. W. Buurman |
Multirate integration in a direct simulation method. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
Multirate Integration, Timing, Circuit Simulation |
1 | Che W. Chiou, Ted C. Yang |
Fully testable PLA design with minimal extra input. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | Georges G. E. Gielen, Koen Swings, Willy M. C. Sansen |
An intelligent design system for analogue integrated circuits. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | Maria J. Avedillo, José M. Quintana, José Luis Huertas |
A new method for the state reduction of incompletely specified finite sequential machines. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | Chang-Sheng Ying, Joshua Sook-Leung Wong, X. L. Hong, E. Q. Wang |
Path search on rectangular floorplan. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | P. Johannes, P. Das, Luc J. M. Claesen, Hugo De Man |
SLOCOP-II: a versatile timing verification system for MOSVLSI. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
Static timing verification |
1 | Allen C.-H. Wu, Nels Vander Zanden, Daniel Gajski |
A new algorithm for transistor sizing in CMOS circuits. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | Diederik Verkest, Luc J. M. Claesen, Hugo De Man |
Correctness proofs of parameterized hardware modules in the CATHEDRAL-II synthesis environment. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | Wolfgang Meier |
Hierarchical layout verification for submicron designs. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | Vishwani D. Agrawal, Kwang-Ting Cheng |
An architecture for synthesis of testable finite state machines. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | Robert Tjärnström |
Automatic generation of timing specifications for CMOS transistor subnetworks. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | Bryan Preas |
Channel routing with non-terminal doglegs. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | Martin Lefebvre 0001, Chong Chan, Grant Martin |
Transistor placement and interconnect algorithms for leaf cell synthesis. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | J. Zegers, Paul Six, Jan M. Rabaey, Hugo De Man |
CGE: automatic generation of controllers in the CATHEDRAL-II silicon compiler. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | Carles Ferrer 0001, Joan Oliver, Elena Valderrama |
A new switch-level test pattern generation algorithm based on single path over a graph representation. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | Mehrdad Negahban, Daniel Gajski |
Silicon compilation of switched: capacitor networks. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | Uwe Hinsberger, Reiner Kolla |
Cell based performance optimization of combinational circuits. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | Frank H. Huentemann, Utz G. Baitinger |
A gate-matrix oriented partitioning approach for multilevel logical networks. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | Grazia Arato, Giuseppe Bussolino, Anna M. Fiammengo, Roberto Manione |
ACCORDO: second generation floor planning. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | Lukas P. P. P. van Ginneken, Ralph H. J. M. Otten |
Optimal slicing of plane point placements. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | Jason Cong, C. L. Liu 0001 |
On the k-layer planar subset and via minimization problems. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | Wu-Tung Cheng, Janak H. Patel |
PROOFS: a super fast fault simulator for sequential circuits. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | Robert A. Cottrell |
Event-driven behavioural simulation of analogue transfer functions. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
Behavioural Simulation, Mixed Analogue-Digital Simulation, Modelling |
1 | Philippe Bondono, Ahmed Amine Jerraya, Armand Hornik, Bernard Courtois, D. Bonifas |
NAUTILE: a safe environment for silicon compilation. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | J. P. Schupp, Johan Cockx, Luc J. M. Claesen, Hugo De Man |
SPI: an open interface integrating highly interactive electronic CAD tools. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | Veronika Eisele, Bernhard Hoppe, Oliver Kiehl |
Transmission gate delay models for circuit optimization. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | Torsten Grüning, Udo Mahlstedt, Wilfried Daehn, Cengiz Özcan |
Accelerated test pattern generation by cone-oriented circuit partitioning. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | Saleem M. Haider, Peng H. Ang |
A data-structuring technique for gridded VLSI layouts. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | Leon Stok |
Interconnect optimisation during data path allocation. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | David J. Mallon, Peter B. Denyer |
A new approach to pipeline optimisation. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | Magdy S. Abadir, Jack Ferguson |
An improved layout verification algorithm (LAVA). |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | Mart Altmäe |
MINT: a VHDL simulation system. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | Sybille Hellebrand, Hans-Joachim Wunderlich |
Tools and devices supporting the pseudo-exhaustive test. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
automatic design for testability, Pseudo-exhaustive test |
1 | Christian Jay |
Experience in functional-level test generation and fault coverage in a silicon compiler. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | Kaushik Roy 0001, Jacob A. Abraham |
High level test generation using data flow descriptions. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | Gordon Adshead, Jochen A. G. Jess (eds.) |
European Design Automation Conference, EURO-DAC 1990, Glasgow, Scotland, UK, March 12-15, 1990 |
EURO-DAC |
1990 |
DBLP BibTeX RDF |
|
1 | Khushro Shahookar, Pinaki Mazumder |
GASP: a Genetic Algorithm for Standard cell Placement. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | Niraj K. Jha, Qiao Tong |
Detection of multiple input bridging and stuck-on faults in CMOS logic circuits using current monitoring. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | Lech Józwiak |
Efficent suboptimal state assignment for large sequential machines. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | Abdelhakim Safir, Bertrand Y. Zavidovique |
Towards a global solution to high level synthesis problems. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | Chong-Min Kyung, Josef Widder, Dieter A. Mlynski |
Adaptive Cluster Growth (ACG): a new algorithm for circuit packing in rectilinear region. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | Patrick Odent, Luc J. M. Claesen, Hugo De Man |
A combined waveform relaxation: waveform relaxation newton algorithm for efficient parallel circuit simulation. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | Liliana Díaz-Olavarrieta, Safwat G. Zaky |
A new synthesis technique for multilevel combinational circuits. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
testing, mappings, synthesis, Combinational |
1 | Eleanor Wu, Paul W. Rutkowski |
PEST: a tool for implementing pseudo-exhaustive self test. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | Robi Dutta, Maurice Marks, Craig Morrissey, Ravi Rao, Lee Sapiro |
A flexible hierarchical 3-D module assembler. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | Martin Klimke, Christian Winkelmeyr, Herbert Eichinger |
Development of test programs with the aid of a testeroriented pattern language. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
1 | Richard I. Hartley, Kenneth Welles II, Michael J. Hartman, Paul Delano, Abhijit Chatterjee |
Rapid prototyping using high density interconnects. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|