Search results for "FMCAD"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Michael J. C. Gordon, James Reynolds, Warren A. Hunt Jr., Matt Kaufmann	An Integration of HOL and ACL2.	FMCAD	2006	DBLP DOI BibTeX RDF
1	Florian Pigorsch, Christoph Scholl 0001, Stefan Disch	Advanced Unbounded Model Checking Based on AIGs, BDD Sweeping, And Quantifier Scheduling.	FMCAD	2006	DBLP DOI BibTeX RDF
1	Alessandro Cimatti, Marco Roveri, Simone Semprini, Stefano Tonetta	From PSL to NBA: a Modular Symbolic Encoding.	FMCAD	2006	DBLP DOI BibTeX RDF
1	Sagar Chaki, Nishant Sinha 0001	Assume-Guarantee Reasoning for Deadlock.	FMCAD	2006	DBLP DOI BibTeX RDF
1	Jun Sawada, Erik Reeber	ACL2SIX: A Hint used to Integrate a Theorem Prover and an Automated Verification Tool.	FMCAD	2006	DBLP DOI BibTeX RDF
1	Hossein M. Sheini, Karem A. Sakallah	Ario: A Linear Integer Arithmetic Logic Solver.	FMCAD	2006	DBLP DOI BibTeX RDF
1	Ashish Darbari	Symmetry Reduction for STE Model Checking.	FMCAD	2006	DBLP DOI BibTeX RDF
1	Éric Grégoire, Bertrand Mazure, Cédric Piette	Tracking MUSes and Strict Inconsistent Covers.	FMCAD	2006	DBLP DOI BibTeX RDF
1	Amir Hossein Ghamarian, Marc Geilen, Twan Basten, Bart D. Theelen, Mohammad Reza Mousavi 0001, Sander Stuijk	Liveness and Boundedness of Synchronous Data Flow Graphs.	FMCAD	2006	DBLP DOI BibTeX RDF
1	Tilman Glökler, Jason Baumgartner, Devi Shanmugam, A. E. (Rick) Seigler, Gary A. Van Huben, Barinjato Ramanandray, Hari Mony, Paul Roessler	Enabling Large-Scale Pervasive Logic Verification through Multi-Algorithmic Formal Reasoning.	FMCAD	2006	DBLP DOI BibTeX RDF
1	Barbara Jobstmann, Roderick Bloem	Optimizations for LTL Synthesis.	FMCAD	2006	DBLP DOI BibTeX RDF
1	Shiva Nejati, Mihaela Gheorghiu, Marsha Chechik	Thorough Checking Revisited.	FMCAD	2006	DBLP DOI BibTeX RDF
1	Byron Cook, Daniel Kroening, Natasha Sharygina	Over-Approximating Boolean Programs with Unbounded Thread Creation.	FMCAD	2006	DBLP DOI BibTeX RDF
1	Zurab Khasidashvili, Marcelo Skaba, Daher Kaiss, Ziyad Hanna	Post-reboot Equivalence and Compositional Verification of Hardware.	FMCAD	2006	DBLP DOI BibTeX RDF
1	Abu Nasser Mohammed Abdullah, Behzad Akbarpour, Sofiène Tahar	Formal Analysis and Verification of an OFDM Modem Design using HOL.	FMCAD	2006	DBLP DOI BibTeX RDF
1	Cameron Brien, Sharad Malik	Understanding the Dynamic Behavior of Modern DPLL SAT Solvers through Visual Analysis.	FMCAD	2006	DBLP DOI BibTeX RDF
1	Husam Abu-Haimed, David L. Dill, Sergey Berezin	A Refinement Method for Validity Checking of Quantified First-Order Formulas in Hardware Verification.	FMCAD	2006	DBLP DOI BibTeX RDF
1	Xiaofang Chen, Yu Yang 0013, Ganesh Gopalakrishnan, Ching-Tsun Chou	Reducing Verification Complexity of a Multicore Coherence Protocol Using Assume/Guarantee.	FMCAD	2006	DBLP DOI BibTeX RDF
1	Neha Rungta, Eric G. Mercer	An Improved Distance Heuristic Function for Directed Software Model Checking.	FMCAD	2006	DBLP DOI BibTeX RDF
1	Claude Helmstetter, Florence Maraninchi, Laurent Maillet-Contoz, Matthieu Moy	Automatic Generation of Schedulings for Improving the Test Coverage of Systems-on-a-Chip.	FMCAD	2006	DBLP DOI BibTeX RDF
1	Namrata Shekhar, Priyank Kalla, M. Brandon Meredith, Florian Enescu	Simulation Bounds for Equivalence Verification of Arithmetic Datapaths with Finite Word-Length Operands.	FMCAD	2006	DBLP DOI BibTeX RDF
1	Johannes Faber, Roland Meyer 0001	Model Checking Data-Dependent Real-Time Properties of the European Train Control System.	FMCAD	2006	DBLP DOI BibTeX RDF
1		Formal Methods in Computer-Aided Design, 6th International Conference, FMCAD 2006, San Jose, California, USA, November 12-16, 2006, Proceedings	FMCAD	2006	DBLP BibTeX RDF
1	Julien Schmaltz	A Formal Model of Lower System Layers.	FMCAD	2006	DBLP DOI BibTeX RDF
1	Haja Moinudeen, Ali Habibi, Sofiène Tahar	Design for Verification of the PCI-X Bus.	FMCAD	2006	DBLP DOI BibTeX RDF
1	Hyondeuk Kim, Fabio Somenzi	Finite Instantiations for Integer Difference Logic.	FMCAD	2006	DBLP DOI BibTeX RDF
1	Sava Krstic, Jordi Cortadella, Michael Kishinevsky, John O'Leary	Synchronous Elastic Networks.	FMCAD	2006	DBLP DOI BibTeX RDF
1	Lubos Brim, Ivana Cerná, Pavel Moravec 0002, Jirí Simsa	Accepting Predecessors Are Better than Back Edges in Distributed LTL Model-Checking.	FMCAD	2004	DBLP DOI BibTeX RDF
1	Enrico Giunchiglia, Massimo Narizzano, Armando Tacchella	QuBE++: An Efficient QBF Solver.	FMCAD	2004	DBLP DOI BibTeX RDF
1	Emmanuel Zarpas	Simple Yet Efficient Improvements of SAT Based Bounded Model Checking.	FMCAD	2004	DBLP DOI BibTeX RDF
1	Panagiotis Manolios, Daron Vroon 0001	Integrating Reasoning About Ordinal Arithmetic into ACL2.	FMCAD	2004	DBLP DOI BibTeX RDF
1	Alan J. Hu, Andrew K. Martin (eds.)	Formal Methods in Computer-Aided Design, 5th International Conference, FMCAD 2004, Austin, Texas, USA, November 15-17, 2004, Proceedings	FMCAD	2004	DBLP DOI BibTeX RDF
1	Mary Sheeran	Generating Fast Multipliers Using Clever Circuits.	FMCAD	2004	DBLP DOI BibTeX RDF
1	Zijiang Yang 0006, Rajeev Alur	Variable Reuse for Efficient Image Computation.	FMCAD	2004	DBLP DOI BibTeX RDF
1	Ching-Tsun Chou, Phanindra K. Mannava, Seungjoon Park	A Simple Method for Parameterized Verification of Cache Coherence Protocols.	FMCAD	2004	DBLP DOI BibTeX RDF
1	Mohammad Awedh, Fabio Somenzi	Increasing the Robustness of Bounded Model Checking by Computing Lower Bounds on the Reachable States.	FMCAD	2004	DBLP DOI BibTeX RDF
1	Behzad Akbarpour, Sofiène Tahar	A Methodology for the Formal Verification of FFT Algorithms in HOL.	FMCAD	2004	DBLP DOI BibTeX RDF
1	Sandip Ray, J Strother Moore	Proof Styles in Operational Semantics.	FMCAD	2004	DBLP DOI BibTeX RDF
1	Alessandro Cimatti, Marco Roveri, Daniel Sheridan	Bounded Verification of Past LTL.	FMCAD	2004	DBLP DOI BibTeX RDF
1	Mark D. Aagaard, Vlad C. Ciubotariu, Jason T. Higgins, Farzad Khalvati	Combining Equivalence Verification and Completion Functions.	FMCAD	2004	DBLP DOI BibTeX RDF
1	Giuseppe Della Penna, Benedetto Intrigila, Igor Melatti, Enrico Tronci, Marisa Venturini Zilli	Bounded Probabilistic Model Checking with the Muralpha Verifier.	FMCAD	2004	DBLP DOI BibTeX RDF
1	Orna Grumberg, Assaf Schuster, Avi Yadgar	Memory Efficient All-Solutions SAT Solver and Its Application for Reachability Analysis.	FMCAD	2004	DBLP DOI BibTeX RDF
1	Tobias Nopper, Christoph Scholl 0001	Approximate Symbolic Model Checking for Incomplete Designs.	FMCAD	2004	DBLP DOI BibTeX RDF
1	Julien Schmaltz, Dominique Borrione	A Functional Approach to the Formal Specification of Networks on Chip.	FMCAD	2004	DBLP DOI BibTeX RDF
1	Nina Amla, Kenneth L. McMillan	A Hybrid of Counterexample-Based and Proof-Based Abstraction.	FMCAD	2004	DBLP DOI BibTeX RDF
1	In-Ho Moon, Carl Pixley	Non-miter-based Combinational Equivalence Checking by Comparing BDDs with Different Variable Orders.	FMCAD	2004	DBLP DOI BibTeX RDF
1	Debashis Sahoo, Subramanian K. Iyer, Jawahar Jain, Christian Stangier, Amit Narayan, David L. Dill, E. Allen Emerson	A Partitioning Methodology for BDD-Based Verification.	FMCAD	2004	DBLP DOI BibTeX RDF
1	Mark D. Aagaard, Nancy A. Day, Robert B. Jones	Synchronization-at-Retirement for Pipeline Verification.	FMCAD	2004	DBLP DOI BibTeX RDF
1	Timo Latvala, Armin Biere, Keijo Heljanko, Tommi A. Junttila	Simple Bounded LTL Model Checking.	FMCAD	2004	DBLP DOI BibTeX RDF	linear translation, bounded model checking, LTL, NuSMV
1	Koen Claessen, Johan Mårtensson	An Operational Semantics for Weak PSL.	FMCAD	2004	DBLP DOI BibTeX RDF
1	Thao Dang 0001, Alexandre Donzé, Oded Maler	Verification of Analog and Mixed-Signal Circuits Using Hybrid System Techniques.	FMCAD	2004	DBLP DOI BibTeX RDF
1	Peter C. Dillinger, Panagiotis Manolios	Bloom Filters in Probabilistic Verification.	FMCAD	2004	DBLP DOI BibTeX RDF
1	Hari Mony, Jason Baumgartner, Viresh Paruthi, Robert Kanzelman, Andreas Kuehlmann	Scalable Automated Verification via Expert-System Guided Transformations.	FMCAD	2004	DBLP DOI BibTeX RDF
1	Wayne H. Wolf	Challenges in System-Level Design.	FMCAD	2004	DBLP DOI BibTeX RDF
1	Christian Stangier, Thomas Sidle	Invariant Checking Combining Forward and Backward Traversal.	FMCAD	2004	DBLP DOI BibTeX RDF
1	Arie Gurfinkel, Marsha Chechik	Extending Extended Vacuity.	FMCAD	2004	DBLP DOI BibTeX RDF
1	Marko Samer, Helmut Veith	Parameterized Vacuity.	FMCAD	2004	DBLP DOI BibTeX RDF
1	Laurent Arditi, Gérard Berry, Michael Kishinevsky	Late Design Changes (ECOs) for Sequentially Optimized Esterel Designs.	FMCAD	2004	DBLP DOI BibTeX RDF
1	Jin Yang 0006, Carl-Johan H. Seger	Generalized Symbolic Trajectory Evaluation - Abstraction in Action.	FMCAD	2002	DBLP DOI BibTeX RDF
1	Richard Sharp	Functional Design Using Behavioural and Structural Components.	FMCAD	2002	DBLP DOI BibTeX RDF
1	Fabio Somenzi, Kavita Ravi, Roderick Bloem	Analysis of Symbolic SCC Hull Algorithms.	FMCAD	2002	DBLP DOI BibTeX RDF
1	Vijay Ganesh, Sergey Berezin, David L. Dill	Deciding Presburger Arithmetic by Model Checking and Comparisons with Other Methods.	FMCAD	2002	DBLP DOI BibTeX RDF
1	Ofer Strichman	On Solving Presburger and Linear Arithmetic with SAT.	FMCAD	2002	DBLP DOI BibTeX RDF
1	Gianfranco Ciardo, Radu Siminiceanu	Using Edge-Valued Decision Diagrams for Symbolic Generation of Shortest Paths.	FMCAD	2002	DBLP DOI BibTeX RDF
1	Jun Sawada, Ruben Gamboa	Mechanical Verification of a Square Root Algorithm Using Taylor's Theorem.	FMCAD	2002	DBLP DOI BibTeX RDF
1	In-Ho Moon, Hee-Hwan Kwak, James H. Kukula, Thomas R. Shiple, Carl Pixley	Simplifying Circuits for Formal Verification Using Parametric Representation.	FMCAD	2002	DBLP DOI BibTeX RDF
1	Abdelwaheb Ayari, David A. Basin	QUBOS: Deciding Quantified Boolean Logic Using Propositional Satisfiability Solvers.	FMCAD	2002	DBLP DOI BibTeX RDF
1	David Harel, Hillel Kugler, Rami Marelly, Amir Pnueli	Smart Play-out of Behavioral Requirements.	FMCAD	2002	DBLP DOI BibTeX RDF
1	Alan M. Frisch, Daniel Sheridan, Toby Walsh	A Fixpoint Based Encoding for Bounded Model Checking.	FMCAD	2002	DBLP DOI BibTeX RDF
1	Shuvendu K. Lahiri, Sanjit A. Seshia, Randal E. Bryant	Modeling and Verification of Out-of-Order Microprocessors in UCLID.	FMCAD	2002	DBLP DOI BibTeX RDF
1	Giuseppe Della Penna, Benedetto Intrigila, Enrico Tronci, Marisa Venturini Zilli	Exploiting Transition Locality in the Disk Based Mur phi Verifier.	FMCAD	2002	DBLP DOI BibTeX RDF
1	Steve McKeever, Wayne Luk, Arran Derbyshire	Compiling Hardware Descriptions with Relative Placement Information for Parametrised Libraries.	FMCAD	2002	DBLP DOI BibTeX RDF
1	Prosenjit Chatterjee, Ganesh Gopalakrishnan	A Specification and Verification Framework for Developing Weak Shared Memory Consistency Protocols.	FMCAD	2002	DBLP DOI BibTeX RDF
1	Satyaki Das, David L. Dill	Counter-Example Based Predicate Discovery in Predicate Abstraction.	FMCAD	2002	DBLP DOI BibTeX RDF
1	Mark D. Aagaard, John W. O'Leary (eds.)	Formal Methods in Computer-Aided Design, 4th International Conference, FMCAD 2002, Portland, OR, USA, November 6-8, 2002, Proceedings	FMCAD	2002	DBLP DOI BibTeX RDF
1	Chao Wang 0001, Gary D. Hachtel	Sharp Disjunctive Decomposition for Language Emptiness Checking.	FMCAD	2002	DBLP DOI BibTeX RDF
1	Marc Solé, Enric Pastor	Traversal Techniques for Concurrent Systems.	FMCAD	2002	DBLP DOI BibTeX RDF
1	Thomas F. Melham, Robert B. Jones	Abstraction by Symbolic Indexing Transformations.	FMCAD	2002	DBLP DOI BibTeX RDF
1	Mark D. Aagaard, Nancy A. Day, Meng Lou	Relating Multi-step and Single-Step Microprocessor Correctness Statements.	FMCAD	2002	DBLP DOI BibTeX RDF
1	Pankaj Chauhan, Edmund M. Clarke, James H. Kukula, Samir Sapra, Helmut Veith, Dong Wang	Automated Abstraction Refinement for Model Checking Large State Spaces Using SAT Based Conflict Analysis.	FMCAD	2002	DBLP DOI BibTeX RDF
1	Meine van der Meulen	Model Checking the Design of an Unrestricted, Stuck-at Fault Tolerant, Asynchronous Sequential Circuit Using SMV.	FMCAD	2002	DBLP DOI BibTeX RDF
1	Josep Carmona 0001, Jordi Cortadella	Input/Output Compatibility of Reactive Systems.	FMCAD	2002	DBLP DOI BibTeX RDF	Input/Output compatibility, Synchronous product, Petri nets, Reactive systems, Conformation, Observational equivalence, Trace theory
1	Gerd Ritter	Sequential Equivalence Checking by Symbolic Simulation.	FMCAD	2000	DBLP DOI BibTeX RDF
1	John Harrison 0001	Formal Verification of Floating Point Trigonometric Functions.	FMCAD	2000	DBLP DOI BibTeX RDF
1	Kanna Shimizu, David L. Dill, Alan J. Hu	Monitor-Based Formal Specification of PCI.	FMCAD	2000	DBLP DOI BibTeX RDF
1	Chris Wilson, David L. Dill, Randal E. Bryant	Symbolic Simulation with Approximate Values.	FMCAD	2000	DBLP DOI BibTeX RDF
1	Jin Hou, Eduard Cerny	Model Reductions and a Case Study.	FMCAD	2000	DBLP DOI BibTeX RDF
1	Shoham Ben-David, Tamir Heyman, Orna Grumberg, Assaf Schuster	Scalable Distributed On-the-Fly Symbolic Model Checking.	FMCAD	2000	DBLP DOI BibTeX RDF
1	Kiyoharu Hamaguchi, Hidekazu Urushihara, Toshinobu Kashiwabara	Symbolic Checking of Signal-Transition Consistency for Verifying High-Level Designs.	FMCAD	2000	DBLP DOI BibTeX RDF
1	Christoph Meinel, Christian Stangier	Speeding Up Image Computation by Using RTL Information.	FMCAD	2000	DBLP DOI BibTeX RDF
1	Nina Amla, E. Allen Emerson, Robert P. Kurshan, Kedar S. Namjoshi	Model Checking Synchronous Timing Diagrams.	FMCAD	2000	DBLP DOI BibTeX RDF
1	Mark D. Aagaard, Robert B. Jones, Thomas F. Melham, John W. O'Leary, Carl-Johan H. Seger	A Methodology for Large-Scale Hardware Verification.	FMCAD	2000	DBLP DOI BibTeX RDF
1	Gordon J. Pace	The Semantics of Verilog Using Transition System Combinators.	FMCAD	2000	DBLP DOI BibTeX RDF
1	Kavita Ravi, Roderick Bloem, Fabio Somenzi	A Comparative Study of Symbolic Algorithms for the Computation of Fair Cycles.	FMCAD	2000	DBLP DOI BibTeX RDF
1	David M. Russinoff	A Case Study in Fomal Verification of Register-Transfer Logic with ACL2: The Floating Point Adder of the AMD AthlonTM Processor.	FMCAD	2000	DBLP DOI BibTeX RDF
1	Adilson Luiz Bonifácio, Arnaldo Vieira Moura	Modeling and Parameters Synthesis for an Air Traffic Management System.	FMCAD	2000	DBLP DOI BibTeX RDF
1	In-Ho Moon, Gary D. Hachtel, Fabio Somenzi	Border-Block Triangular Form and Conjunction Schedule in Image Computation.	FMCAD	2000	DBLP DOI BibTeX RDF
1	Michael D. Jones, Ganesh Gopalakrishnan	Verifying Transaction Ordering Properties in Unbounded Bus Networks through Combined Deductive/Algorithmic Methods.	FMCAD	2000	DBLP DOI BibTeX RDF
1	Edmund M. Clarke, Steven M. German, Yuan Lu 0004, Helmut Veith, Dong Wang	Executable Protocol Specification in ESL.	FMCAD	2000	DBLP DOI BibTeX RDF
1	David A. Basin, Stefan Friedrich 0001, Sebastian Mödersheim	B2M: A Semantic Based Tool for BLIF Hardware Descriptions.	FMCAD	2000	DBLP DOI BibTeX RDF

Publications at "FMCAD"( http://dblp.L3S.de/Venues/FMCAD )