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Publication years (Num. hits)
1980-1992 (15) 1993-1995 (21) 1996-1997 (34) 1998 (22) 1999 (30) 2000 (41) 2001 (23) 2002 (30) 2003 (44) 2004 (39) 2005 (53) 2006 (57) 2007 (50) 2008 (40) 2009 (21) 2010 (24) 2011-2012 (24) 2013 (15) 2014-2015 (20) 2016-2017 (24) 2018-2019 (23) 2020-2021 (25) 2022 (18) 2023-2024 (16)
Publication types (Num. hits)
article(113) book(2) incollection(3) inproceedings(586) phdthesis(5)
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Found 709 publication records. Showing 709 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
10Leonid B. Goldgeisser Creating implicit homotopy methods using Hardware Description Languages. Search on Bibsonomy ISCAS (3) The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
10Ki-seon Cho, Jong-on Park, Jin-seok Hong, Goang-Seog Choi 54x54-bit radix-4 multiplier based on modified booth algorithm. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2003 DBLP  DOI  BibTeX  RDF compressor, adder, multiplier, booth encoder, wallace tree
10Lorena Anghel, Raoul Velazco, S. Saleh, S. Deswaertes, A. El Moucary Preliminary Validation of an Approach Dealing with Processor Obsolescence. Search on Bibsonomy DFT The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
10Miroslav N. Velev Collection of High-Level Microprocessor Bugs from Formal Verification of Pipelined and Superscalar Designs. Search on Bibsonomy ITC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
10Lukás Sekanina Towards Evolvable IP Cores for FPGAs. Search on Bibsonomy Evolvable Hardware The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
10Norihiro Fujii, Shûichi Yukita, Nobuhiko Koike, Tosiyasu L. Kunii Top-Down eLearning Tools for Hardware Logic Design. Search on Bibsonomy CW The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
10Yu-Chin Hsu, Bassam Tabbara, Yirng-An Chen, Fur-Shing Tsai Advanced techniques for RTL debugging. Search on Bibsonomy DAC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF simulation, visualization, verification, debug, reasoning
10Robert Schreiber, Shail Aditya, Scott A. Mahlke, Vinod Kathail, B. Ramakrishna Rau, Darren C. Cronquist, Mukund Sivaraman PICO-NPA: High-Level Synthesis of Nonprogrammable Hardware Accelerators. Search on Bibsonomy J. VLSI Signal Process. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF high-level hardware synthesis, automatic parallelization, datapath synthesis
10Amit Chowdhary, Rajesh K. Gupta 0001 A Methodology for Synthesis of Data Path Circuitse. Search on Bibsonomy IEEE Des. Test Comput. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
10Shoham Ben-David, Anna Gringauze, Baruch Sterin, Yaron Wolfsthal PathFinder: A Tool for Design Exploration. Search on Bibsonomy CAV The full citation details ... 2002 DBLP  DOI  BibTeX  RDF Model Checking, Debugging, Design Exploration, PathFinder
10Shengchao Qin, Jifeng He 0001, Zongyan Qiu, Naixiao Zhang Hardware/Software Partitioning in Verilog. Search on Bibsonomy ICFEM The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
10William W. LaRue, Sherry Solden, Bishnupriya Bhattacharya Functional and Performance Modeling of Concurrency in VCC. Search on Bibsonomy Concurrency and Hardware Design The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
10Jacir Luiz Bordim, Yasuaki Ito, Koji Nakano Accelerating the CKY Parsing Using FPGAs. Search on Bibsonomy HiPC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
10Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou Effective Error Diagnosis for RTL Designs in HDLs. Search on Bibsonomy Asian Test Symposium The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
10Akira Miyashita, Toshihito Fujiwara, Tsutomu Maruyama A Placement/Routing Approach for FPGA Accelerators. Search on Bibsonomy FPL The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
10Haiyan Xiong, Paul Curzon, Sofiène Tahar, Ann Blandford Formally Linking MDG and HOL Based on a Verified MDG System. Search on Bibsonomy IFM The full citation details ... 2002 DBLP  DOI  BibTeX  RDF hybrid verification systems, deductive theorem proving, symbolic state enumeration, usability verification, hardware verification
10Akira Kitajima, Toshiyuki Sasaki, Yoshinori Takeuchi, Masaharu Imai Design of Application Specific CISC Using PEAS-III. Search on Bibsonomy IEEE International Workshop on Rapid System Prototyping The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
10Christophe Bobda, Nils Steenbock A Rapid Prototyping Environment for Distributed Reconfigurable Systems. Search on Bibsonomy IEEE International Workshop on Rapid System Prototyping The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
10Hong Peng, Yassine Mokhtari, Sofiène Tahar Environment Synthesis for Compositional Model Checking. Search on Bibsonomy ICCD The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
10Ivan Blunno, Luciano Lavagno Designing an Asynchronous Microcontroller Using Pipefitter. Search on Bibsonomy ICCD The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
10Sumit Ghosh In Search of the Origin of VHDL's Delta Delays. Search on Bibsonomy ISQED The full citation details ... 2002 DBLP  DOI  BibTeX  RDF Delta delay, simulation accuracy, BCL, Conlan, continuous systems, simulation, timing, discrete event simulation, VHDL, hardware, hardware description language, HDLs
10Oliver Schliebusch, Andreas Hoffmann 0002, Achim Nohl, Gunnar Braun, Heinrich Meyr Architecture Implementation Using the Machine Description Language LISA. Search on Bibsonomy ASP-DAC/VLSI Design The full citation details ... 2002 DBLP  DOI  BibTeX  RDF Design, Implementation, Synthesis, VHDL, Exploration, SystemC, ASIP, Verilog, LISA
10Irfan Darmawan, W. T. Hartono, Eril Mozef, Sarwono Sutikno, Kuspriyanto VHDL design and simulation of MAM memory for LAPCAM parallel architecture for image processing. Search on Bibsonomy APCCAS (1) The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
10Teppei Nakano, Takashi Morie, Makoto Nagata, Atsushi Iwata A cellular-automaton-type image extraction algorithm and its implementation using an FPGA. Search on Bibsonomy APCCAS (2) The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
10Srihari Cadambi, Chandra Mulpuri, Pranav Ashar A fast, inexpensive and scalable hardware acceleration technique for functional simulation. Search on Bibsonomy DAC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF FPGA, hardware acceleration, VLIW, functional simulation
10Luc Séméria, Renu Mehra, Barry M. Pangrle, Arjuna Ekanayake, Andrew Seawright, Daniel Ng RTL c-based methodology for designing and verifying a multi-threaded processor. Search on Bibsonomy DAC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF formal equivalence, design, verification, RTL, checking, C/C++
10Chung-Yang Huang, Kwang-Ting Cheng Using word-level ATPG and modular arithmetic constraint-solvingtechniques for assertion property checking. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
10Jordan Dimitrov Operational Semantics for Verilog. Search on Bibsonomy APSEC The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
10Chien-Nan Jimmy Liu, I-Ling Chen, Jing-Yang Jou An efficient design-for-verification technique for HDLs. Search on Bibsonomy ASP-DAC The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
10Satnam Singh, Philip James-Roxby Rapid Construction of Partial Configuration Datastreams from High-Level Constructs Using JBits. Search on Bibsonomy FPL The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
10Jim Armstrong, Amy Bell, Gail Gray An Intra-Disciplinary Capstone Project in Digital Filter Design. Search on Bibsonomy MSE The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
10Hardy J. Pottinger Design Contests as Class Projects: Are They Worth the Effort? Search on Bibsonomy MSE The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
10Taek Won Kwon, Chang-Seok You, Won-Seok Heo, Yong-Kyu Kang, Jun Rim Choi Two implementation methods of a 1024-bit RSA cryptoprocessor based on modified Montgomery algorithm. Search on Bibsonomy ISCAS (4) The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
10Keishi Chikamura, Tomonori Izumi, Takao Onoye, Yukihiro Nakamura IEEE1394 system simulation environment and a design of its link layer controller. Search on Bibsonomy ISCAS (5) The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
10Dae Won Kim, Taek Won Kwon, Jung Min Seo, Jae Kun Yu, Kyu Lee, Jung Hee Suk, Jun Rim Choi A compatible DCT/IDCT architecture using hardwired distributed arithmetic. Search on Bibsonomy ISCAS (2) The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
10Chien-Nan Jimmy Liu, Chia-Chih Yen, Jing-Yang Jou Automatic Functional Vector Generation Using the Interacting FSM Model. Search on Bibsonomy ISQED The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
10Xiaoliang Bai, Sujit Dey High-level Crosstalk Defect Simulation for System-on-Chip Interconnects. Search on Bibsonomy VTS The full citation details ... 2001 DBLP  DOI  BibTeX  RDF System-on-Chip, Crosstalk, Interconnect test, Defect simulation, High level
10Shengchao Qin, Zongyan Qiu, Jifeng He 0001 Constructing Hardware/Software Interface Using Protocol Converters. Search on Bibsonomy APAQS The full citation details ... 2001 DBLP  DOI  BibTeX  RDF protocol converter, program algebra, Hardware/software partition
10Jin-Hyuk Yang, Byoung-Woon Kim, Sang-Joon Nam, Young-Su Kwon, Dae-Hyun Lee, Jong-Yeol Lee, Chan-Soo Hwang, Yong Hoon Lee, Seung Ho Hwang, In-Cheol Park, Chong-Min Kyung MetaCore: an application-specific programmable DSP development system. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
10Franco Fummi, Donatella Sciuto A Hierarchical Test Generation Approach for Large Controllers. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2000 DBLP  DOI  BibTeX  RDF hierarchical FSM, sequential circuits, automatic test pattern generation, Functional testing, functional fault model
10Jian Shen, Jacob A. Abraham An RTL Abstraction Technique for Processor Microarchitecture Validation and Test Generation. Search on Bibsonomy J. Electron. Test. The full citation details ... 2000 DBLP  DOI  BibTeX  RDF microprocessor design validation, coverage measurement, test generation
10Wen-Jong Fang, Allen C.-H. Wu Multiway FPGA partitioning by fully exploiting design hierarchy. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2000 DBLP  DOI  BibTeX  RDF fine-grained synthesis, functional clustering, multi-way partitioning, multiple-FPGA synthesis
10Alessandro Bogliolo, Luca Benini, Giovanni De Micheli Regression-based RTL power modeling. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2000 DBLP  DOI  BibTeX  RDF RTL power modeling, adaptive characterization, functional macros, regression models, RTL design
10Oskar Mencer, Luc Séméria, Martin Morf, Jean-Marc Delosme Application of Reconfigurable CORDIC Architectures. Search on Bibsonomy J. VLSI Signal Process. The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
10Jonathan P. Bowen, Jifeng He 0001, Qiwen Xu An Animatable Operational Semantics of the Verilog Hardware Description Language. Search on Bibsonomy ICFEM The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
10Manuela Anton, Mauro Chinosi, Daniele Sirtori, Roberto Zafalon Architectural Design Space Exploration Achieved through Innovative RTL Power Estimation Techniques. Search on Bibsonomy PATMOS The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
10Achim Freimann Framework for High-Level Power Estimation of Signal Processing Architectures. Search on Bibsonomy PATMOS The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
10J. W. Smith The gsim gate-level simulator. Search on Bibsonomy ACM Southeast Regional Conference The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
10Ou Yamamoto, Yuichiro Shibata, Hitoshi Kurosawa, Hideharu Amano A Reconfigurable Stochastic Model Simulator for Analysis of Parallel Systems. Search on Bibsonomy FPL The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
10Steve Guccione Run-Time Reconfiguration at Xilinx. Search on Bibsonomy IPDPS Workshops The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
10Ou Yamamoto, Yuichiro Shibata, Hitoshi Kurosawa, Hideharu Amano A Reconfigurable Stochastic Model Simulator for Analysis of Parallel Systems. Search on Bibsonomy FCCM The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
10Tsutomu Yoshinaga, Masaya Hayashi, Maki Horita, Sayuri Nakamura, Kanemitsu Ootsu, Takanobu Baba Recover-X: An Adaptive Router with Limited Escape Channels. Search on Bibsonomy ICPADS The full citation details ... 2000 DBLP  DOI  BibTeX  RDF wormhole routers, adaptive routing, hardware description language, hardware cost, deadlock recovery
10Jonathan P. Bowen Combining Operational Semantics, Logic Programming and Literate Programming in the Specification and Animation of the Verilog Hardware Description Language. Search on Bibsonomy IFM The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
10Bernardo Kastrup, Orlando Moreira A Novel Approach to Minimizing the Logic of Combinatorial Multiplexing Circuits in Product-Term-Based Hardware. Search on Bibsonomy EUROMICRO The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
10Andrew Stone, Elias S. Manolakos Minimal Complexity Hierarchical Loop Representations of SFG Processors for Optimal High Level Synthesis. Search on Bibsonomy ASAP The full citation details ... 2000 DBLP  DOI  BibTeX  RDF Optimal VHDL, DG2VHDL, Hierarchical CDFG, High Level Synthesis, Dependence Graph, Signal Flow Graph, Design Complexity
10Erik A. McShane, Krishna Shenai Correct-by-Design CAD Enhancement for EMI Signal Integrity. Search on Bibsonomy ISQED The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
10Carlo Guardiani, Andrzej J. Strojwas Design-Manufacturing Interface in the Deep Submicron: Is Technology Independent Design Dead? Search on Bibsonomy ISQED The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
10Roberto Zafalon, Massimo Rossello, Enrico Macii, Massimo Poncino Power Macromodeling for a High Quality RT-Level Power Estimation. Search on Bibsonomy ISQED The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
10Timour Paltashev, Gheni Abla, Navin Govind Simulation of Hardware Support for OpenGL Graphics Architecture. Search on Bibsonomy ITCC The full citation details ... 2000 DBLP  DOI  BibTeX  RDF performance evaluation, computer graphics, computer architecture, computer simulation, OpenGL
10Yang Xia, Pranav Ashar Verification of a Combinational Loop Based Arbitration Scheme in a System-On-Chip Integration Architecture. Search on Bibsonomy VLSI Design The full citation details ... 2000 DBLP  DOI  BibTeX  RDF Combinational Loop, Model Checking, Formal Verification, Temporal Logic, Time Division Multiplexing, Token Ring, Computational Tree Logic, Bus Protocol
10Steven Trimberger, Raymond Pang, Amit Singh A 12 Gbps DES Encryptor/Decryptor Core in an FPGA. Search on Bibsonomy CHES The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
10Chung-Yang Huang, Kwang-Ting Cheng Assertion checking by combined word-level ATPG and modular arithmetic constraint-solving techniques. Search on Bibsonomy DAC The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
10Xiaoliang Bai, Sujit Dey, Janusz Rajski Self-test methodology for at-speed test of crosstalk in chip interconnects. Search on Bibsonomy DAC The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
10Jens Horstmannshoff, Heinrich Meyr Efficient building block based RTL code generation from synchronous data flow graphs. Search on Bibsonomy DAC The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
10Cindy Eisner, Irit Shitsevalov, Russ Hoover, Wayne G. Nation, Kyle L. Nelson, Ken Valk A methodology for formal design of hardware control with application to cache coherence protocols. Search on Bibsonomy DAC The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
10Katsuyuki Ochiai, Hiroe Iwasaki, Jiro Naganuma, Makoto Endo, Takeshi Ogura High-speed Software-based Platform for Embedded Software of a Single-chip MPEG-2 Video Encoder LSI with HDTV Scalabilit. Search on Bibsonomy DATE The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
10Abhijit Ghosh, Joachim Kunkel, Stan Y. Liao Hardware Synthesis from C/C++. Search on Bibsonomy DATE The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
10Stefan Höreth, Rolf Drechsler Formal Verification of Word-Level Specifications. Search on Bibsonomy DATE The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
10Shin'ichi Wakabayashi, Tetsushi Koide, Naoyoshi Toshine, Mutsuaki Goto, Yoshikatsu Nakayama, Koichi Hatta An LSI Implementation of an Adaptive Genetic Algorithm with On-The Fly Crossover Operator Selection. Search on Bibsonomy ASP-DAC The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
10Rainer Leupers, Johann Elste, Birger Landwehr Generation of Interpretive and Compiled Instruction Set Simulators. Search on Bibsonomy ASP-DAC The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
10Nadeem Malik, Jason Baumgartner, Steven Roberts, Ryan Dobson A toolset for assisted formal verification. Search on Bibsonomy IPCCC The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
10Thomas Zimmer, N. Milet-Lewis, Ahmed Fakhfakh, B. Ardouin, Hervé Levi, J. B. Duluc, Pascal Fouillat Hierarchical Analogue Design and Behavioural Modelling. Search on Bibsonomy MSE The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
10Edmund M. Clarke, Masahiro Fujita, Sreeranga P. Rajan, Thomas W. Reps, Subash Shankar, Tim Teitelbaum Program Slicing of Hardware Description Languages. Search on Bibsonomy CHARME The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
10Jens Horstmannshoff, Heinrich Meyr Optimized System Synthesis of Complex RT Level Building Blocks from Multirate Dataflow Graphs. Search on Bibsonomy ISSS The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
10Junhyung Um, Taewhan Kim, C. L. Liu 0001 Optimal allocation of carry-save-adders in arithmetic optimization. Search on Bibsonomy ICCAD The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
10Jacob K. White 0001, Gary K. Fedder, Tamal Mukherjee Path toward future CAD environments for MEMS (tutorial abstract). Search on Bibsonomy ICCAD The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
10Atsushi Takayama, Yuichiro Shibata, Keisuke Iwai, Hidenori Miyazaki, Koichi Higure, Xiao-ping Ling, Hideharu Amano Implementation and Evaluation of the Compiler for WASMII, a Virtual Hardware System. Search on Bibsonomy ICPP Workshops The full citation details ... 1999 DBLP  DOI  BibTeX  RDF FPGA, compiler, partitioning, data-flow, reconfigurable system
10A. Vasilliou, K. Gounaris, Kostas Adaos, D. Mitsainas, George Alexiou, Dimitris Nikolos Development of a Reusable E1 Transceiver Suitable for Rapid Prototyping. Search on Bibsonomy IEEE International Workshop on Rapid System Prototyping The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
10Walling R. Cyre, Jeffrey Hess, Andreas Gunawan, Ritesh Sojitra A Rapid Modeling Tool for Virtual Prototypes. Search on Bibsonomy IEEE International Workshop on Rapid System Prototyping The full citation details ... 1999 DBLP  DOI  BibTeX  RDF Information Extraction, Software, Behavioral Modeling, Virtual Prototype, Natural Language Understanding
10Pradip K. Jha, Steven Barnfield, John B. Weaver, Rudra Mukherjee, Reinaldo A. Bergamaschi Synthesis of Arrays and Records. Search on Bibsonomy ICCD The full citation details ... 1999 DBLP  DOI  BibTeX  RDF Aggregate data types, Synthesis, Array, Record
10P. P. Jain Cost-effective co-verification using RTL-accurate C models. Search on Bibsonomy ISCAS (6) The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
10C.-C. Wang, C. J. Huang, G.-C. Lin A chip design of radix-4/2 64b/32b signed and unsigned integer divider using Compass cell library. Search on Bibsonomy ISCAS (1) The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
10K. C. Chang 0001, C. A. Lomasney Obsolete integrated circuit replacement methodology using advanced electronic design automation technology. Search on Bibsonomy ISCAS (1) The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
10Jian Shen, Jacob A. Abraham Verification of Processor Microarchitectures. Search on Bibsonomy VTS The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
10D. V. R. Murthy, Seetharaman Ramachandran, S. Srinivasan 0001 Parallel Implementation of 2D-Discrete Cosine Transform Using EPLDs. Search on Bibsonomy VLSI Design The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
10Stephan W. Gehring, Stefan H.-M. Ludwig Fast Integrated Tools for Circuit Design with FPGAs. Search on Bibsonomy FPGA The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
10Juan Carlos Diaz, Pierre Plaza, Jesus Crespo ATM Traffic Shaper: ATS. Search on Bibsonomy DATE The full citation details ... 1998 DBLP  DOI  BibTeX  RDF ATM, Traffic Shaping, FPGA Prototyping
10A. C. Verschueren Rule Base Driven Conversion of an Object Oriented Design Data Structure into Standard Hardware Description Languages. Search on Bibsonomy EUROMICRO The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
10S. Srivastava, S. C. Bose, B. P. Mathur, Arti Noor, Raj Singh, A. S. Mandal, K. Prabhakaran, Arindam Karmakar, Chandra Shekhar 0001, Sudhir Kumar, Amit K. Agarwal Evolution of Architectural Concepts and Design Methods of Microprocessors. Search on Bibsonomy VLSI Design The full citation details ... 1998 DBLP  DOI  BibTeX  RDF Microprocessor Evolution, Synthesis, VHDL, Microprocessor Design
10Patrick Schaumont, Serge Vernalde, Luc Rijnders, Marc Engels, Ivo Bolsens A Programming Environment for the Design of Complex High Speed ASICs. Search on Bibsonomy DAC The full citation details ... 1998 DBLP  DOI  BibTeX  RDF C++, congestion, global routing, quadratic placement, routing models, supply-demand, relaxed pins
10Jin-Hyuk Yang, Byoung-Woon Kim, Sang-Jun Nam, Jang-Ho Cho, Sung-Won Seo, Chang-Ho Ryu, Young-Su Kwon, Dae-Hyun Lee, Jong-Yeol Lee, Jong-Sun Kim, Hyun-Dhong Yoon, Jae-Yeol Kim, Kun-Moo Lee, Chan-Soo Hwang, In-Hyung Kim, Jun Sung Kim, Kwang-Il Park, Kyu Ho Park, Yong Hoon Lee, Seung Ho Hwang, In-Cheol Park, Chong-Min Kyung MetaCore: An Application Specific DSP Development System. Search on Bibsonomy DAC The full citation details ... 1998 DBLP  DOI  BibTeX  RDF high-level synthesis, telecommunication
10Andrew B. Kahng, John C. Lach, William H. Mangione-Smith, Stefanus Mantik, Igor L. Markov, Miodrag Potkonjak, Paul Tucker, Huijuan Wang, Gregory Wolfe Watermarking Techniques for Intellectual Property Protection. Search on Bibsonomy DAC The full citation details ... 1998 DBLP  DOI  BibTeX  RDF system-on-chip test, testing embedded core, intellectual property test
10James Smith 0001, Giovanni De Micheli Automated Composition of Hardware Components. Search on Bibsonomy DAC The full citation details ... 1998 DBLP  DOI  BibTeX  RDF reconstruction, emulation, visibility, functional simulation
10Alessandro Bogliolo, Luca Benini, Giovanni De Micheli, Bruno Riccò Gate-level power and current simulation of CMOS integrated circuits. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
10Franco Fummi, U. Rovati, Donatella Sciuto Functional design for testability of control-dominated architectures. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 1997 DBLP  DOI  BibTeX  RDF interacting FSMs, functional testing
10Srinivasa Rao Arikati, Ravi Varadarajan A signature based approach to regularity extraction. Search on Bibsonomy ICCAD The full citation details ... 1997 DBLP  DOI  BibTeX  RDF regular structure extraction, Physical design
10Charles J. DeVane Efficient circuit partitioning to extend cycle simulation beyond synchronous circuits. Search on Bibsonomy ICCAD The full citation details ... 1997 DBLP  DOI  BibTeX  RDF cycle simulation, levelized compiled code, logic simulation, circuit partitioning
10Sung-Whan Moon, Kang G. Shin, Jennifer Rexford Scalable Hardware Priority Queue Architectures for High-Speed Packet Switches. Search on Bibsonomy IEEE Real Time Technology and Applications Symposium The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
10Franco Fummi, Mariagiovanna Sami, F. Tartarini Use of Statecharts-Related Description to Achieve Testable Design of Control Subsystems. Search on Bibsonomy Great Lakes Symposium on VLSI The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
10Samir Agrawal, Rajesh K. Gupta 0001 Data-Flow Assisted Behavioral Partitioning for Embedded Systems. Search on Bibsonomy DAC The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
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