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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 429 occurrences of 291 keywords
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Results
Found 709 publication records. Showing 709 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
10 | Leonid B. Goldgeisser |
Creating implicit homotopy methods using Hardware Description Languages. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 200-203, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
10 | Ki-seon Cho, Jong-on Park, Jin-seok Hong, Goang-Seog Choi |
54x54-bit radix-4 multiplier based on modified booth algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, Washington, DC, USA, April 28-29, 2003, pp. 233-236, 2003, ACM, 1-58113-677-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
compressor, adder, multiplier, booth encoder, wallace tree |
10 | Lorena Anghel, Raoul Velazco, S. Saleh, S. Deswaertes, A. El Moucary |
Preliminary Validation of an Approach Dealing with Processor Obsolescence. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 3-5 November 2003, Boston, MA, USA, Proceedings, pp. 493-, 2003, IEEE Computer Society, 0-7695-2042-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
10 | Miroslav N. Velev |
Collection of High-Level Microprocessor Bugs from Formal Verification of Pipelined and Superscalar Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, USA, pp. 138-147, 2003, IEEE Computer Society, 0-7803-8106-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
10 | Lukás Sekanina |
Towards Evolvable IP Cores for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Evolvable Hardware ![In: 5th NASA / DoD Workshop on Evolvable Hardware (EH 2003), 9-11 July 2002, Chicago, IL, USA, pp. 145-154, 2003, IEEE Computer Society, 0-7695-1977-6. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
10 | Norihiro Fujii, Shûichi Yukita, Nobuhiko Koike, Tosiyasu L. Kunii |
Top-Down eLearning Tools for Hardware Logic Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CW ![In: 2nd International Conference on Cyberworlds (CW 2003), 3-5 December 2003, Singapore, pp. 410-417, 2003, IEEE Computer Society, 0-7695-1922-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
10 | Yu-Chin Hsu, Bassam Tabbara, Yirng-An Chen, Fur-Shing Tsai |
Advanced techniques for RTL debugging. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 362-367, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
simulation, visualization, verification, debug, reasoning |
10 | Robert Schreiber, Shail Aditya, Scott A. Mahlke, Vinod Kathail, B. Ramakrishna Rau, Darren C. Cronquist, Mukund Sivaraman |
PICO-NPA: High-Level Synthesis of Nonprogrammable Hardware Accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 31(2), pp. 127-142, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
high-level hardware synthesis, automatic parallelization, datapath synthesis |
10 | Amit Chowdhary, Rajesh K. Gupta 0001 |
A Methodology for Synthesis of Data Path Circuitse. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 19(6), pp. 90-100, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
10 | Shoham Ben-David, Anna Gringauze, Baruch Sterin, Yaron Wolfsthal |
PathFinder: A Tool for Design Exploration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 14th International Conference, CAV 2002,Copenhagen, Denmark, July 27-31, 2002, Proceedings, pp. 510-514, 2002, Springer, 3-540-43997-8. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Model Checking, Debugging, Design Exploration, PathFinder |
10 | Shengchao Qin, Jifeng He 0001, Zongyan Qiu, Naixiao Zhang |
Hardware/Software Partitioning in Verilog. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICFEM ![In: Formal Methods and Software Engineering, 4th International Conference on Formal Engineering Methods, ICFEM 2002 Shanghai, China, October 21-25, 2002, Proceedings, pp. 168-179, 2002, Springer, 3-540-00029-1. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
10 | William W. LaRue, Sherry Solden, Bishnupriya Bhattacharya |
Functional and Performance Modeling of Concurrency in VCC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Concurrency and Hardware Design ![In: Concurrency and Hardware Design, Advances in Petri Nets, pp. 191-227, 2002, Springer, 3-540-00199-9. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
10 | Jacir Luiz Bordim, Yasuaki Ito, Koji Nakano |
Accelerating the CKY Parsing Using FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPC ![In: High Performance Computing - HiPC 2002, 9th International Conference, Bangalore, India, December 18-21, 2002, Proceedings, pp. 41-51, 2002, Springer, 3-540-00303-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
10 | Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou |
Effective Error Diagnosis for RTL Designs in HDLs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, pp. 362-367, 2002, IEEE Computer Society, 0-7695-1825-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
10 | Akira Miyashita, Toshihito Fujiwara, Tsutomu Maruyama |
A Placement/Routing Approach for FPGA Accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, Reconfigurable Computing Is Going Mainstream, 12th International Conference, FPL 2002, Montpellier, France, September 2-4, 2002, Proceedings, pp. 1177-1182, 2002, Springer, 3-540-44108-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
10 | Haiyan Xiong, Paul Curzon, Sofiène Tahar, Ann Blandford |
Formally Linking MDG and HOL Based on a Verified MDG System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IFM ![In: Integrated Formal Methods, Third International Conference, IFM 2002, Turku, Finland, May 15-18, 2002, Proceedings, pp. 205-224, 2002, Springer, 3-540-43703-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
hybrid verification systems, deductive theorem proving, symbolic state enumeration, usability verification, hardware verification |
10 | Akira Kitajima, Toshiyuki Sasaki, Yoshinori Takeuchi, Masaharu Imai |
Design of Application Specific CISC Using PEAS-III. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE International Workshop on Rapid System Prototyping ![In: 13th IEEE International Workshop on Rapid System Prototyping (RSP 2002), 1-3 July 2002, Darmstadt, Germany, pp. 12-17, 2002, IEEE Computer Society, 0-7695-1703-X. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
10 | Christophe Bobda, Nils Steenbock |
A Rapid Prototyping Environment for Distributed Reconfigurable Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE International Workshop on Rapid System Prototyping ![In: 13th IEEE International Workshop on Rapid System Prototyping (RSP 2002), 1-3 July 2002, Darmstadt, Germany, pp. 153-158, 2002, IEEE Computer Society, 0-7695-1703-X. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
10 | Hong Peng, Yassine Mokhtari, Sofiène Tahar |
Environment Synthesis for Compositional Model Checking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 20th International Conference on Computer Design (ICCD 2002), VLSI in Computers and Processors, 16-18 September 2002, Freiburg, Germany, Proceedings, pp. 70-, 2002, IEEE Computer Society, 0-7695-1700-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
10 | Ivan Blunno, Luciano Lavagno |
Designing an Asynchronous Microcontroller Using Pipefitter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 20th International Conference on Computer Design (ICCD 2002), VLSI in Computers and Processors, 16-18 September 2002, Freiburg, Germany, Proceedings, pp. 488-493, 2002, IEEE Computer Society, 0-7695-1700-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
10 | Sumit Ghosh |
In Search of the Origin of VHDL's Delta Delays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 3rd International Symposium on Quality of Electronic Design, ISQED 2002, San Jose, CA, USA, March 18-21, 2002, pp. 310-315, 2002, IEEE Computer Society, 0-7695-1561-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Delta delay, simulation accuracy, BCL, Conlan, continuous systems, simulation, timing, discrete event simulation, VHDL, hardware, hardware description language, HDLs |
10 | Oliver Schliebusch, Andreas Hoffmann 0002, Achim Nohl, Gunnar Braun, Heinrich Meyr |
Architecture Implementation Using the Machine Description Language LISA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 239-244, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Design, Implementation, Synthesis, VHDL, Exploration, SystemC, ASIP, Verilog, LISA |
10 | Irfan Darmawan, W. T. Hartono, Eril Mozef, Sarwono Sutikno, Kuspriyanto |
VHDL design and simulation of MAM memory for LAPCAM parallel architecture for image processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS (1) ![In: IEEE Asia Pacific Conference on Circuits and Systems 2002, APCCAS 2002, Singapore, 16-18 December 2002, pp. 389-392, 2002, IEEE, 0-7803-7690-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
10 | Teppei Nakano, Takashi Morie, Makoto Nagata, Atsushi Iwata |
A cellular-automaton-type image extraction algorithm and its implementation using an FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS (2) ![In: IEEE Asia Pacific Conference on Circuits and Systems 2002, APCCAS 2002, Singapore, 16-18 December 2002, pp. 197-200, 2002, IEEE, 0-7803-7690-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
10 | Srihari Cadambi, Chandra Mulpuri, Pranav Ashar |
A fast, inexpensive and scalable hardware acceleration technique for functional simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002, pp. 570-575, 2002, ACM, 1-58113-461-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
FPGA, hardware acceleration, VLIW, functional simulation |
10 | Luc Séméria, Renu Mehra, Barry M. Pangrle, Arjuna Ekanayake, Andrew Seawright, Daniel Ng |
RTL c-based methodology for designing and verifying a multi-threaded processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002, pp. 123-128, 2002, ACM, 1-58113-461-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
formal equivalence, design, verification, RTL, checking, C/C++ |
10 | Chung-Yang Huang, Kwang-Ting Cheng |
Using word-level ATPG and modular arithmetic constraint-solvingtechniques for assertion property checking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(3), pp. 381-391, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
10 | Jordan Dimitrov |
Operational Semantics for Verilog. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APSEC ![In: 8th Asia-Pacific Software Engineering Conference (APSEC 2001), 4-7 December 2001, Macau, China, pp. 161-168, 2001, IEEE Computer Society, 0-7695-1408-1. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
10 | Chien-Nan Jimmy Liu, I-Ling Chen, Jing-Yang Jou |
An efficient design-for-verification technique for HDLs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of ASP-DAC 2001, Asia and South Pacific Design Automation Conference 2001, January 30-February 2, 2001, Yokohama, Japan, pp. 103-108, 2001, ACM, 0-7803-6634-4. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
10 | Satnam Singh, Philip James-Roxby |
Rapid Construction of Partial Configuration Datastreams from High-Level Constructs Using JBits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, 11th International Conference, FPL 2001, Belfast, Northern Ireland, UK, August 27-29, 2001, Proceedings, pp. 346-356, 2001, Springer, 3-540-42499-7. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
10 | Jim Armstrong, Amy Bell, Gail Gray |
An Intra-Disciplinary Capstone Project in Digital Filter Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MSE ![In: 2001 International Conference on Microelectronics Systems Education, MSE 2001, Las Vegas, NV, USA, July 17-18, 2001, pp. 52-53, 2001, IEEE Computer Society, 0-7695-1156-2. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
10 | Hardy J. Pottinger |
Design Contests as Class Projects: Are They Worth the Effort? ![Search on Bibsonomy](Pics/bibsonomy.png) |
MSE ![In: 2001 International Conference on Microelectronics Systems Education, MSE 2001, Las Vegas, NV, USA, July 17-18, 2001, pp. 96-97, 2001, IEEE Computer Society, 0-7695-1156-2. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
10 | Taek Won Kwon, Chang-Seok You, Won-Seok Heo, Yong-Kyu Kang, Jun Rim Choi |
Two implementation methods of a 1024-bit RSA cryptoprocessor based on modified Montgomery algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 650-653, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
10 | Keishi Chikamura, Tomonori Izumi, Takao Onoye, Yukihiro Nakamura |
IEEE1394 system simulation environment and a design of its link layer controller. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 1-4, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
10 | Dae Won Kim, Taek Won Kwon, Jung Min Seo, Jae Kun Yu, Kyu Lee, Jung Hee Suk, Jun Rim Choi |
A compatible DCT/IDCT architecture using hardwired distributed arithmetic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 457-460, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
10 | Chien-Nan Jimmy Liu, Chia-Chih Yen, Jing-Yang Jou |
Automatic Functional Vector Generation Using the Interacting FSM Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 26-28 March 2001, San Jose, CA, USA, pp. 372-377, 2001, IEEE Computer Society, 0-7695-1025-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
10 | Xiaoliang Bai, Sujit Dey |
High-level Crosstalk Defect Simulation for System-on-Chip Interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April - 3 May 2001, Marina Del Rey, CA, USA, pp. 169-177, 2001, IEEE Computer Society, 0-7695-1122-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
System-on-Chip, Crosstalk, Interconnect test, Defect simulation, High level |
10 | Shengchao Qin, Zongyan Qiu, Jifeng He 0001 |
Constructing Hardware/Software Interface Using Protocol Converters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APAQS ![In: 2nd Asia-Pacific Conference on Quality Software (APAQS 2001), 10-11 December 2001, Hong Kong, China, Proceedings, pp. 141-148, 2001, IEEE Computer Society, 0-7695-1287-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
protocol converter, program algebra, Hardware/software partition |
10 | Jin-Hyuk Yang, Byoung-Woon Kim, Sang-Joon Nam, Young-Su Kwon, Dae-Hyun Lee, Jong-Yeol Lee, Chan-Soo Hwang, Yong Hoon Lee, Seung Ho Hwang, In-Cheol Park, Chong-Min Kyung |
MetaCore: an application-specific programmable DSP development system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 8(2), pp. 173-183, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
10 | Franco Fummi, Donatella Sciuto |
A Hierarchical Test Generation Approach for Large Controllers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 49(4), pp. 289-302, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
hierarchical FSM, sequential circuits, automatic test pattern generation, Functional testing, functional fault model |
10 | Jian Shen, Jacob A. Abraham |
An RTL Abstraction Technique for Processor Microarchitecture Validation and Test Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 16(1-2), pp. 67-81, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
microprocessor design validation, coverage measurement, test generation |
10 | Wen-Jong Fang, Allen C.-H. Wu |
Multiway FPGA partitioning by fully exploiting design hierarchy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 5(1), pp. 34-50, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
fine-grained synthesis, functional clustering, multi-way partitioning, multiple-FPGA synthesis |
10 | Alessandro Bogliolo, Luca Benini, Giovanni De Micheli |
Regression-based RTL power modeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 5(3), pp. 337-372, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
RTL power modeling, adaptive characterization, functional macros, regression models, RTL design |
10 | Oskar Mencer, Luc Séméria, Martin Morf, Jean-Marc Delosme |
Application of Reconfigurable CORDIC Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 24(2-3), pp. 211-221, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
10 | Jonathan P. Bowen, Jifeng He 0001, Qiwen Xu |
An Animatable Operational Semantics of the Verilog Hardware Description Language. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICFEM ![In: 3rd IEEE International Conference on Formal Engineering Methods, ICFEM 2000, York, England, UK, September 4-7, 2000, Proceedings, pp. 199-208, 2000, IEEE Computer Society, 0-7695-0822-7. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
10 | Manuela Anton, Mauro Chinosi, Daniele Sirtori, Roberto Zafalon |
Architectural Design Space Exploration Achieved through Innovative RTL Power Estimation Techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation, 10th International Workshop, PATMOS 2000, Göttingen, Germany, September 13-15, 2000, Proceedings, pp. 3-13, 2000, Springer, 3-540-41068-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
10 | Achim Freimann |
Framework for High-Level Power Estimation of Signal Processing Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation, 10th International Workshop, PATMOS 2000, Göttingen, Germany, September 13-15, 2000, Proceedings, pp. 56-65, 2000, Springer, 3-540-41068-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
10 | J. W. Smith |
The gsim gate-level simulator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Southeast Regional Conference ![In: Proceedings of the 38th Annual Southeast Regional Conference, 2000, Clemson, South Carolina, USA, April 7-8, 2000, pp. 67-76, 2000, ACM, 1-58113-250-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
10 | Ou Yamamoto, Yuichiro Shibata, Hitoshi Kurosawa, Hideharu Amano |
A Reconfigurable Stochastic Model Simulator for Analysis of Parallel Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 475-484, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
10 | Steve Guccione |
Run-Time Reconfiguration at Xilinx. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS Workshops ![In: Parallel and Distributed Processing, 15 IPDPS 2000 Workshops, Cancun, Mexico, May 1-5, 2000, Proceedings, pp. 873-873, 2000, Springer, 3-540-67442-X. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
10 | Ou Yamamoto, Yuichiro Shibata, Hitoshi Kurosawa, Hideharu Amano |
A Reconfigurable Stochastic Model Simulator for Analysis of Parallel Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), 17-19 April 2000, Napa Valley, CA, USA, Proceedings, pp. 291-294, 2000, IEEE Computer Society, 0-7695-0871-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
10 | Tsutomu Yoshinaga, Masaya Hayashi, Maki Horita, Sayuri Nakamura, Kanemitsu Ootsu, Takanobu Baba |
Recover-X: An Adaptive Router with Limited Escape Channels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPADS ![In: Seventh International Conference on Parallel and Distributed Systems, ICPADS 2000, Iwate, Japan, July 4-7, 2000, pp. 272-279, 2000, IEEE Computer Society, 0-7695-0568-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
wormhole routers, adaptive routing, hardware description language, hardware cost, deadlock recovery |
10 | Jonathan P. Bowen |
Combining Operational Semantics, Logic Programming and Literate Programming in the Specification and Animation of the Verilog Hardware Description Language. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IFM ![In: Integrated Formal Methods, Second International Conference, IFM 2000, Dagstuhl Castle, Germany, November 1-3, 2000, Proceedings, pp. 277-296, 2000, Springer, 3-540-41196-8. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
10 | Bernardo Kastrup, Orlando Moreira |
A Novel Approach to Minimizing the Logic of Combinatorial Multiplexing Circuits in Product-Term-Based Hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 26th EUROMICRO 2000 Conference, Informatics: Inventing the Future, 5-7 September 2000, Maastricht, The Netherlands, pp. 1164-1171, 2000, IEEE Computer Society, 0-7695-0780-8. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
10 | Andrew Stone, Elias S. Manolakos |
Minimal Complexity Hierarchical Loop Representations of SFG Processors for Optimal High Level Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 12th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2000), 10-12 July 2000, Boston, MA, USA, pp. 92-102, 2000, IEEE Computer Society, 0-7695-0716-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Optimal VHDL, DG2VHDL, Hierarchical CDFG, High Level Synthesis, Dependence Graph, Signal Flow Graph, Design Complexity |
10 | Erik A. McShane, Krishna Shenai |
Correct-by-Design CAD Enhancement for EMI Signal Integrity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 1st International Symposium on Quality of Electronic Design (ISQED 2000), 20-22 March 2000, San Jose, CA, USA, pp. 341-346, 2000, IEEE Computer Society, 0-7695-0525-2. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
10 | Carlo Guardiani, Andrzej J. Strojwas |
Design-Manufacturing Interface in the Deep Submicron: Is Technology Independent Design Dead? ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 1st International Symposium on Quality of Electronic Design (ISQED 2000), 20-22 March 2000, San Jose, CA, USA, pp. 447-, 2000, IEEE Computer Society, 0-7695-0525-2. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
10 | Roberto Zafalon, Massimo Rossello, Enrico Macii, Massimo Poncino |
Power Macromodeling for a High Quality RT-Level Power Estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 1st International Symposium on Quality of Electronic Design (ISQED 2000), 20-22 March 2000, San Jose, CA, USA, pp. 59-, 2000, IEEE Computer Society, 0-7695-0525-2. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
10 | Timour Paltashev, Gheni Abla, Navin Govind |
Simulation of Hardware Support for OpenGL Graphics Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITCC ![In: 2000 International Symposium on Information Technology (ITCC 2000), 27-29 March 2000, Las Vegas, NV, USA, pp. 295-301, 2000, IEEE Computer Society, 0-7695-0540-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
performance evaluation, computer graphics, computer architecture, computer simulation, OpenGL |
10 | Yang Xia, Pranav Ashar |
Verification of a Combinational Loop Based Arbitration Scheme in a System-On-Chip Integration Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 13th International Conference on VLSI Design (VLSI Design 2000), 4-7 January 2000, Calcutta, India, pp. 449-, 2000, IEEE Computer Society, 0-7695-0487-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Combinational Loop, Model Checking, Formal Verification, Temporal Logic, Time Division Multiplexing, Token Ring, Computational Tree Logic, Bus Protocol |
10 | Steven Trimberger, Raymond Pang, Amit Singh |
A 12 Gbps DES Encryptor/Decryptor Core in an FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2000, Second International Workshop, Worcester, MA, USA, August 17-18, 2000, Proceedings, pp. 156-163, 2000, Springer, 3-540-41455-X. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
10 | Chung-Yang Huang, Kwang-Ting Cheng |
Assertion checking by combined word-level ATPG and modular arithmetic constraint-solving techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000., pp. 118-123, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
10 | Xiaoliang Bai, Sujit Dey, Janusz Rajski |
Self-test methodology for at-speed test of crosstalk in chip interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000., pp. 619-624, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
10 | Jens Horstmannshoff, Heinrich Meyr |
Efficient building block based RTL code generation from synchronous data flow graphs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000., pp. 552-555, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
10 | Cindy Eisner, Irit Shitsevalov, Russ Hoover, Wayne G. Nation, Kyle L. Nelson, Ken Valk |
A methodology for formal design of hardware control with application to cache coherence protocols. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000., pp. 724-729, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
10 | Katsuyuki Ochiai, Hiroe Iwasaki, Jiro Naganuma, Makoto Endo, Takeshi Ogura |
High-speed Software-based Platform for Embedded Software of a Single-chip MPEG-2 Video Encoder LSI with HDTV Scalabilit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1999 Design, Automation and Test in Europe (DATE '99), 9-12 March 1999, Munich, Germany, pp. 303-308, 1999, IEEE Computer Society / ACM, 0-7695-0078-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
10 | Abhijit Ghosh, Joachim Kunkel, Stan Y. Liao |
Hardware Synthesis from C/C++. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1999 Design, Automation and Test in Europe (DATE '99), 9-12 March 1999, Munich, Germany, pp. 387-389, 1999, IEEE Computer Society / ACM, 0-7695-0078-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
10 | Stefan Höreth, Rolf Drechsler |
Formal Verification of Word-Level Specifications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1999 Design, Automation and Test in Europe (DATE '99), 9-12 March 1999, Munich, Germany, pp. 52-57, 1999, IEEE Computer Society / ACM, 0-7695-0078-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
10 | Shin'ichi Wakabayashi, Tetsushi Koide, Naoyoshi Toshine, Mutsuaki Goto, Yoshikatsu Nakayama, Koichi Hatta |
An LSI Implementation of an Adaptive Genetic Algorithm with On-The Fly Crossover Operator Selection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 1999 Conference on Asia South Pacific Design Automation, Wanchai, Hong Kong, China, January 18-21, 1999, pp. 37-40, 1999, IEEE Computer Society, 0-7803-5012-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
10 | Rainer Leupers, Johann Elste, Birger Landwehr |
Generation of Interpretive and Compiled Instruction Set Simulators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 1999 Conference on Asia South Pacific Design Automation, Wanchai, Hong Kong, China, January 18-21, 1999, pp. 339-342, 1999, IEEE Computer Society, 0-7803-5012-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
10 | Nadeem Malik, Jason Baumgartner, Steven Roberts, Ryan Dobson |
A toolset for assisted formal verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPCCC ![In: Proceedings of the IEEE International Performance Computing and Communications Conference, IPCCC 1999, Phoenix/Scottsdale, Arizona, USA, 10-12 February 1999, pp. 489-492, 1999, IEEE, 0-7803-5258-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
10 | Thomas Zimmer, N. Milet-Lewis, Ahmed Fakhfakh, B. Ardouin, Hervé Levi, J. B. Duluc, Pascal Fouillat |
Hierarchical Analogue Design and Behavioural Modelling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MSE ![In: IEEE International Conference on Microelectronic Systems Education, MSE 1999, Arlington, Virginia, USA, July 19-21, 1999, pp. 59-60, 1999, IEEE Computer Society, 0-7695-0312-8. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
10 | Edmund M. Clarke, Masahiro Fujita, Sreeranga P. Rajan, Thomas W. Reps, Subash Shankar, Tim Teitelbaum |
Program Slicing of Hardware Description Languages. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHARME ![In: Correct Hardware Design and Verification Methods, 10th IFIP WG 10.5 Advanced Research Working Conference, CHARME '99, Bad Herrenalb, Germany, September 27-29, 1999, Proceedings, pp. 298-312, 1999, Springer, 3-540-66559-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
10 | Jens Horstmannshoff, Heinrich Meyr |
Optimized System Synthesis of Complex RT Level Building Blocks from Multirate Dataflow Graphs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 12th International Symposium on System Synthesis, ISSS '99, Boca Raton, Florida, USA, November 1-4, 1999., pp. 38-43, 1999, ACM / IEEE Computer Society, 0-7695-0356-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
10 | Junhyung Um, Taewhan Kim, C. L. Liu 0001 |
Optimal allocation of carry-save-adders in arithmetic optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999, San Jose, California, USA, November 7-11, 1999, pp. 410-413, 1999, IEEE Computer Society, 0-7803-5832-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
10 | Jacob K. White 0001, Gary K. Fedder, Tamal Mukherjee |
Path toward future CAD environments for MEMS (tutorial abstract). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999, San Jose, California, USA, November 7-11, 1999, pp. 606, 1999, IEEE Computer Society, 0-7803-5832-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
10 | Atsushi Takayama, Yuichiro Shibata, Keisuke Iwai, Hidenori Miyazaki, Koichi Higure, Xiao-ping Ling, Hideharu Amano |
Implementation and Evaluation of the Compiler for WASMII, a Virtual Hardware System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP Workshops ![In: Proceedings of the 1999 International Conference on Parallel Processing Workshops, ICPPW 1999, Wakamatsu, Japan, September 21-24, 1999, pp. 346-351, 1999, IEEE Computer Society, 0-7695-0353-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
FPGA, compiler, partitioning, data-flow, reconfigurable system |
10 | A. Vasilliou, K. Gounaris, Kostas Adaos, D. Mitsainas, George Alexiou, Dimitris Nikolos |
Development of a Reusable E1 Transceiver Suitable for Rapid Prototyping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE International Workshop on Rapid System Prototyping ![In: Proceedings of the Tenth IEEE International Workshop on Rapid System Prototyping (RSP 1999), Clearwater, Florida, USA, June 16-18, 1999, pp. 21-, 1999, IEEE Computer Society, 0-7695-0246-6. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
10 | Walling R. Cyre, Jeffrey Hess, Andreas Gunawan, Ritesh Sojitra |
A Rapid Modeling Tool for Virtual Prototypes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE International Workshop on Rapid System Prototyping ![In: Proceedings of the Tenth IEEE International Workshop on Rapid System Prototyping (RSP 1999), Clearwater, Florida, USA, June 16-18, 1999, pp. 178-183, 1999, IEEE Computer Society, 0-7695-0246-6. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Information Extraction, Software, Behavioral Modeling, Virtual Prototype, Natural Language Understanding |
10 | Pradip K. Jha, Steven Barnfield, John B. Weaver, Rudra Mukherjee, Reinaldo A. Bergamaschi |
Synthesis of Arrays and Records. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design, VLSI in Computers and Processors, ICCD '99, Austin, Texas, USA, October 10-13, 1999, pp. 614-619, 1999, IEEE Computer Society, 0-7695-0406-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Aggregate data types, Synthesis, Array, Record |
10 | P. P. Jain |
Cost-effective co-verification using RTL-accurate C models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (6) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 460-463, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
10 | C.-C. Wang, C. J. Huang, G.-C. Lin |
A chip design of radix-4/2 64b/32b signed and unsigned integer divider using Compass cell library. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 439-442, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
10 | K. C. Chang 0001, C. A. Lomasney |
Obsolete integrated circuit replacement methodology using advanced electronic design automation technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 400-403, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
10 | Jian Shen, Jacob A. Abraham |
Verification of Processor Microarchitectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 17th IEEE VLSI Test Symposium (VTS '99), 25-30 April 1999, San Diego, CA, USA, pp. 189-194, 1999, IEEE Computer Society, 0-7695-0146-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
10 | D. V. R. Murthy, Seetharaman Ramachandran, S. Srinivasan 0001 |
Parallel Implementation of 2D-Discrete Cosine Transform Using EPLDs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 12th International Conference on VLSI Design (VLSI Design 1999), 10-13 January 1999, Goa, India, pp. 336-339, 1999, IEEE Computer Society, 0-7695-0013-7. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
10 | Stephan W. Gehring, Stefan H.-M. Ludwig |
Fast Integrated Tools for Circuit Design with FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, FPGA 1998, Monterey, CA, USA, February 22-24, 1998, pp. 133-139, 1998, ACM, 0-89791-978-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
10 | Juan Carlos Diaz, Pierre Plaza, Jesus Crespo |
ATM Traffic Shaper: ATS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 96-101, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
ATM, Traffic Shaping, FPGA Prototyping |
10 | A. C. Verschueren |
Rule Base Driven Conversion of an Object Oriented Design Data Structure into Standard Hardware Description Languages. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 24th EUROMICRO '98 Conference, Engineering Systems and Software for the Next Decade, 25-27 August 1998, Vesteras, Sweden, pp. 10042-10045, 1998, IEEE Computer Society, 0-8186-8646-4. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
10 | S. Srivastava, S. C. Bose, B. P. Mathur, Arti Noor, Raj Singh, A. S. Mandal, K. Prabhakaran, Arindam Karmakar, Chandra Shekhar 0001, Sudhir Kumar, Amit K. Agarwal |
Evolution of Architectural Concepts and Design Methods of Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 11th International Conference on VLSI Design (VLSI Design 1991), 4-7 January 1998, Chennai, India, pp. 312-317, 1998, IEEE Computer Society, 0-8186-8224-8. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Microprocessor Evolution, Synthesis, VHDL, Microprocessor Design |
10 | Patrick Schaumont, Serge Vernalde, Luc Rijnders, Marc Engels, Ivo Bolsens |
A Programming Environment for the Design of Complex High Speed ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 315-320, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
C++, congestion, global routing, quadratic placement, routing models, supply-demand, relaxed pins |
10 | Jin-Hyuk Yang, Byoung-Woon Kim, Sang-Jun Nam, Jang-Ho Cho, Sung-Won Seo, Chang-Ho Ryu, Young-Su Kwon, Dae-Hyun Lee, Jong-Yeol Lee, Jong-Sun Kim, Hyun-Dhong Yoon, Jae-Yeol Kim, Kun-Moo Lee, Chan-Soo Hwang, In-Hyung Kim, Jun Sung Kim, Kwang-Il Park, Kyu Ho Park, Yong Hoon Lee, Seung Ho Hwang, In-Cheol Park, Chong-Min Kyung |
MetaCore: An Application Specific DSP Development System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 800-803, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
high-level synthesis, telecommunication |
10 | Andrew B. Kahng, John C. Lach, William H. Mangione-Smith, Stefanus Mantik, Igor L. Markov, Miodrag Potkonjak, Paul Tucker, Huijuan Wang, Gregory Wolfe |
Watermarking Techniques for Intellectual Property Protection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 776-781, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
system-on-chip test, testing embedded core, intellectual property test |
10 | James Smith 0001, Giovanni De Micheli |
Automated Composition of Hardware Components. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 14-19, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
reconstruction, emulation, visibility, functional simulation |
10 | Alessandro Bogliolo, Luca Benini, Giovanni De Micheli, Bruno Riccò |
Gate-level power and current simulation of CMOS integrated circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 5(4), pp. 473-488, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
10 | Franco Fummi, U. Rovati, Donatella Sciuto |
Functional design for testability of control-dominated architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 2(2), pp. 98-122, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
interacting FSMs, functional testing |
10 | Srinivasa Rao Arikati, Ravi Varadarajan |
A signature based approach to regularity extraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1997, San Jose, CA, USA, November 9-13, 1997, pp. 542-545, 1997, IEEE Computer Society / ACM, 0-8186-8200-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
regular structure extraction, Physical design |
10 | Charles J. DeVane |
Efficient circuit partitioning to extend cycle simulation beyond synchronous circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1997, San Jose, CA, USA, November 9-13, 1997, pp. 154-161, 1997, IEEE Computer Society / ACM, 0-8186-8200-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
cycle simulation, levelized compiled code, logic simulation, circuit partitioning |
10 | Sung-Whan Moon, Kang G. Shin, Jennifer Rexford |
Scalable Hardware Priority Queue Architectures for High-Speed Packet Switches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Real Time Technology and Applications Symposium ![In: 3rd IEEE Real-Time Technology and Applications Symposium, RTAS '97, Montreal, Canada, June 9-11, 1997, pp. 203-212, 1997, IEEE Computer Society, 0-8186-8016-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
10 | Franco Fummi, Mariagiovanna Sami, F. Tartarini |
Use of Statecharts-Related Description to Achieve Testable Design of Control Subsystems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 7th Great Lakes Symposium on VLSI (GLS-VLSI '97), 13-15 March 1997, Urbana, IL, USA, pp. 118-123, 1997, IEEE Computer Society, 0-8186-7904-2. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
10 | Samir Agrawal, Rajesh K. Gupta 0001 |
Data-Flow Assisted Behavioral Partitioning for Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 34st Conference on Design Automation, Anaheim, California, USA, Anaheim Convention Center, June 9-13, 1997., pp. 709-712, 1997, ACM Press, 0-89791-920-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
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