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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 851 occurrences of 523 keywords
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Results
Found 2201 publication records. Showing 2201 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
13 | Ahmed Kamaleldin, Diana Göhringer |
AGILER: An Adaptive Heterogeneous Tile-Based Many-Core Architecture for RISC-V Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 10, pp. 43895-43913, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Satyam Shukla, Kailash Chandra Ray |
A Low-Overhead Reconfigurable RISC-V Quad-Core Processor Architecture for Fault-Tolerant Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 10, pp. 44136-44146, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
13 | YoungBeom Kim, Seog Chung Seo |
Optimized Implementation of PIPO Block Cipher on 32-Bit ARM and RISC-V Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 10, pp. 97298-97309, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Shahriar Hadayeghparast, Siavash Bayat Sarmadi, Shahriar Ebrahimi |
High-Speed Post-Quantum Cryptoprocessor Based on RISC-V Architecture for IoT. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Internet Things J. ![In: IEEE Internet Things J. 9(17), pp. 15839-15846, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Yuanhu Cheng, Libo Huang, Yi-Jun Cui, Sheng Ma, Yongwen Wang, Bingcai Sui |
RV16: An Ultra-Low-Cost Embedded RISC-V Processor Core. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comput. Sci. Technol. ![In: J. Comput. Sci. Technol. 37(6), pp. 1307-1319, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Sankatali Venkateswarlu, Subrat Mishra, Herman Oprins, Bjorn Vermeersch, Moritz Brunion, Jun-Han Han, Mircea R. Stan, Pieter Weckx, Francky Catthoor |
Thermal Performance Analysis of Mempool RISC-V Multicore SoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 30(11), pp. 1668-1676, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Kleber Stangherlin, Manoj Sachdev |
Design and Implementation of a Secure RISC-V Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 30(11), pp. 1705-1715, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Cristián Ramírez, Adrián Castelló 0001, Enrique S. Quintana-Ortí |
A BLIS-like matrix multiplication for machine learning in the RISC-V ISA-based GAP8 processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 78(16), pp. 18051-18060, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Markku-Juhani O. Saarinen, G. Richard Newell, Ben Marshall |
Development of the RISC-V entropy source interface. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Cryptogr. Eng. ![In: J. Cryptogr. Eng. 12(4), pp. 371-386, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Atharva Kalsekar, Rasika Khade, Krupa Jariwala, Chiranjoy Chattopadhyay |
RISC-Net : rotation invariant siamese convolution network for floor plan image retrieval. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Multim. Tools Appl. ![In: Multim. Tools Appl. 81(28), pp. 41199-41223, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Marco Cococcioni, Federico Rossi 0003, Emanuele Ruffaldi, Sergio Saponara |
A Lightweight Posit Processing Unit for RISC-V Processors in Deep Neural Network Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Emerg. Top. Comput. ![In: IEEE Trans. Emerg. Top. Comput. 10(4), pp. 1898-1908, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
13 | David Mallasén, Raul Murillo 0001, Alberto A. Del Barrio, Guillermo Botella, Luis Piñuel, Manuel Prieto-Matías |
PERCIVAL: Open-Source Posit RISC-V Core With Quire Capability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Emerg. Top. Comput. ![In: IEEE Trans. Emerg. Top. Comput. 10(3), pp. 1241-1252, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Eiji Yoshiya, Tomoya Nakanishi, Tsuyoshi Isshiki |
Design Verification Methodology of Pipelined RISC-V Processor Using C2RTL Framework. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 105-A(7), pp. 1061-1069, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Rami Elkhatib, Brian Koziel, Reza Azarderakhsh, Mehran Mozaffari Kermani |
Accelerated RISC-V for Post-Quantum SIKE. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 69(6), pp. 2490-2501, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Yifan Zhao, Ruiqi Xie, Guozhu Xin, Jun Han 0003 |
A High-Performance Domain-Specific Processor With Matrix Extension of RISC-V for Module-LWE Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 69(7), pp. 2871-2884, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Yossi Eni, Shlomo Greenberg, Yehuda Ben-Shimol |
Efficient Hint-Based Event (EHE) Issue Scheduling for Hardware Multithreaded RISC-V Pipeline. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 69(2), pp. 735-745, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Rogério Paludo, Leonel Sousa |
NTT Architecture for a Linux-Ready RISC-V Fully-Homomorphic Encryption Accelerator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 69(7), pp. 2669-2682, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Lang Feng, Jiayi Huang 0001, Luyi Li, Haochen Zhang, Zhongfeng Wang 0001 |
RvDfi: A RISC-V Architecture With Security Enforcement by High Performance Complete Data-Flow Integrity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 71(10), pp. 2499-2512, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Piljoo Choi, Won Bae Kong, Ji-Hoon Kim, Mun-Kyu Lee, Dong Kyue Kim |
Architectural Supports for Block Ciphers in a RISC CPU Core by Instruction Overloading. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 71(11), pp. 2844-2857, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Bruno Sá, José Martins, Sandro Pinto 0001 |
A First Look at RISC-V Virtualization From an Embedded Systems Perspective. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 71(9), pp. 2177-2190, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Jipeng Zhang, Junhao Huang, Zhe Liu 0001, Sujoy Sinha Roy |
Time-Memory Trade-Offs for Saber+ on Memory-Constrained RISC-V Platform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 71(11), pp. 2996-3007, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Yuze Wang, Peng Liu 0016, Weidong Wang, Xiaohang Wang 0001, Yingtao Jiang |
On a Consistency Testing Model and Strategy for Revealing RISC Processor's Dark Instructions and Vulnerabilities. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 71(7), pp. 1586-1597, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Hela Belhadj Amor, Carolynn Bernier, Zdenek Prikryl |
A RISC-V ISA Extension for Ultra-Low Power IoT Wireless Signal Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 71(4), pp. 766-778, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Enrico Tabanelli, Giuseppe Tagliavini, Luca Benini |
Optimizing Random Forest-Based Inference on RISC-V MCUs at the Extreme Edge. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(11), pp. 4516-4526, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Jim Plusquellic, Donald E. Owen, Tom J. Mannos, Brian Dziki |
Information Leakage Analysis Using a Co-Design-Based Fault Injection Technique on a RISC-V Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(3), pp. 438-451, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Jubee Tada, Keiichi Sato |
An Implementation of a Grid Square Codes Generator on a RISC-V Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Netw. Comput. ![In: Int. J. Netw. Comput. 12(1), pp. 204-217, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP BibTeX RDF |
|
13 | Vladimir Herdt, Rolf Drechsler |
Advanced virtual prototyping for cyber-physical systems using RISC-V: implementation, verification and challenges. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sci. China Inf. Sci. ![In: Sci. China Inf. Sci. 65(1), 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Vaibhav Verma, Tommy Tracy II, Mircea R. Stan |
EXTREM-EDGE - EXtensions To RISC-V for Energy-efficient ML inference at the EDGE of IoT. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sustain. Comput. Informatics Syst. ![In: Sustain. Comput. Informatics Syst. 35, pp. 100742, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Jhalak Sharma, Nanditha Rao |
The Characterization of Errors in an FPGA-Based RISC-V Processor due to Single Event Transients. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 123, pp. 105392, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Fernando Fernandes dos Santos, Angeliki Kritikakou, Olivier Sentieys |
Experimental evaluation of neutron-induced errors on a multicore RISC-V platform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2206.08639, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Kleber Stangherlin, Manoj Sachdev |
Design and Implementation of a Secure RISC-V Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2205.05095, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Xuanle Ren, Xiaoxia Cui |
An Enclave-based TEE for SE-in-SoC in RISC-V Industry. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2208.03631, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Kevin Cheang, Cameron Rasmussen, Dayeol Lee, David W. Kohlbrenner, Krste Asanovic, Sanjit A. Seshia |
Verifying RISC-V Physical Memory Protection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2211.02179, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Luca Bertaccini, Gianna Paulin, Tim Fischer 0001, Stefan Mach, Luca Benini |
MiniFloat-NN and ExSdotp: An ISA Extension and a Modular Open Hardware Unit for Low-Precision Training on RISC-V cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2207.03192, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Yvan Tortorella, Luca Bertaccini, Davide Rossi, Luca Benini, Francesco Conti 0001 |
RedMulE: A Compact FP16 Matrix-Multiplication Accelerator for Adaptive Deep Learning on RISC-V-Based Ultra-Low-Power SoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2204.11192, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Nazareno Bruschi, Germain Haugou, Giuseppe Tagliavini, Francesco Conti 0001, Luca Benini, Davide Rossi |
GVSoC: A Highly Configurable, Fast and Accurate Full-Platform Simulator for RISC-V based IoT Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2201.08166, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP BibTeX RDF |
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13 | Luca Valente, Yvan Tortorella, Mattia Sinigaglia, Giuseppe Tagliavini, Alessandro Capotondi, Luca Benini, Davide Rossi |
HULK-V: a Heterogeneous Ultra-low-power Linux capable RISC-V SoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2211.14944, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Marco Bertuletti, Yichao Zhang, Alessandro Vanelli-Coralli, Luca Benini |
Efficient Parallelization of 5G-PUSCH on a Scalable RISC-V Many-core Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2210.09196, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Vladimir Ushakov, Sampo Sovio, Qingchao Qi, Vijayanand Nayani, Valentin Manea, Philip Ginzboorg, Jan-Erik Ekberg |
Trusted Hart for Mobile RISC-V Security. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2211.10299, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Jiulong Wang, Ruopu Wu, Guokai Chen, Xuhao Chen 0004, Boran Liu, Jixiang Zong, Di Zhao |
RISC-V Toolchain and Agile Development based Open-source Neuromorphic Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2210.00562, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Andrea Bartolini, Federico Ficarelli, Emanuele Parisi, Francesco Beneventi, Francesco Barchi, Daniele Gregori, Fabrizio Magugliani, Marco Cicala, Cosimo Gianfreda, Daniele Cesarini, Andrea Acquaviva, Luca Benini |
Monte Cimone: Paving the Road for the First Generation of RISC-V High-Performance Computers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2205.03725, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Ralf Ramsauer, Stefan Huber, Konrad Schwarz, Jan Kiszka, Wolfgang Mauerer |
Static Hardware Partitioning on RISC-V - Shortcomings, Limitations, and Prospects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2208.02703, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Francesco Daghero, Chen Xie, Daniele Jahier Pagliari, Alessio Burrello, Marco Castellano, Luca Gandolfi, Andrea Calimera, Enrico Macii, Massimo Poncino |
Ultra-compact Binary Neural Networks for Human Activity Recognition on RISC-V Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2205.12781, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | David Demicco, Matthew Cole, Gokturk Yuksek, Ravi Theja Gollapudi, Aravind Prakash, Kanad Ghose, Zerksis Umrigar |
Generic Tagging for RISC-V Binaries. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2212.05614, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Matteo Perotti, Matheus A. Cavalcante, Nils Wistoff, Renzo Andri, Lukas Cavigelli, Luca Benini |
A "New Ara" for Vector Computing: An Open Source Highly Efficient RISC-V V 1.0 Vector Processor Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2210.08882, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Pablo Andreu, Carles Hernández 0001, Tomás Picornell, Pedro López 0001, Sergi Alcaide, Francisco Bas, Pedro Benedicte, Guillem Cabo, Feng Chang, Francisco Fuentes, Jaume Abella 0001 |
End-to-End QoS for the Open Source Safety-Relevant RISC-V SELENE Platform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2210.04683, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Joseph Zuckerman, Paolo Mantovani, Davide Giri, Luca P. Carloni |
Enabling Heterogeneous, Multicore SoC Research with RISC-V and ESP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2206.01901, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Ruxandra Balucea, Paul Irofti |
Software Mitigation of RISC-V Spectre Attacks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2206.04507, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Md. Ashraful Islam, Kenji Kise |
An Efficient Resource Shared RISC-V Multicore Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Inf. Syst. ![In: IEICE Trans. Inf. Syst. 105-D(9), pp. 1506-1515, September 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Takuto Kanamori, Takashi Odan, Kazuki Hirohata, Kenji Kise |
RVCar: An FPGA-Based Simple and Open-Source Mini Motor Car System with a RISC-V Soft Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Inf. Syst. ![In: IEICE Trans. Inf. Syst. 105-D(12), pp. 1999-2007, December 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Shoei Nashimoto, Daisuke Suzuki, Rei Ueno, Naofumi Homma |
Bypassing Isolated Execution on RISC-V using Side-Channel-Assisted Fault-Injection and Its Countermeasure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IACR Trans. Cryptogr. Hardw. Embed. Syst. ![In: IACR Trans. Cryptogr. Hardw. Embed. Syst. 2022(1), pp. 28-68, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Hao Cheng 0009, Johann Großschädl, Ben Marshall, Dan Page, Thinh Hung Pham |
RISC-V Instruction Set Extensions for Lightweight Symmetric Cryptography. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IACR Cryptol. ePrint Arch. ![In: IACR Cryptol. ePrint Arch. 2022, pp. 1697, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP BibTeX RDF |
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13 | Patrick Karl, Jonas Schupp, Tim Fritzmann, Georg Sigl |
Post-Quantum Signatures on RISC-V with Hardware Acceleration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IACR Cryptol. ePrint Arch. ![In: IACR Cryptol. ePrint Arch. 2022, pp. 538, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP BibTeX RDF |
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13 | Gheorghe Pojoga, Kostas Papagiannopoulos |
Low-latency implementation of the GIFT cipher on RISC-V architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IACR Cryptol. ePrint Arch. ![In: IACR Cryptol. ePrint Arch. 2022, pp. 1399, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP BibTeX RDF |
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13 | Huimin Li 0004, Nele Mentens, Stjepan Picek |
Maximizing the Potential of Custom RISC-V Vector Extensions for Speeding up SHA-3 Hash Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IACR Cryptol. ePrint Arch. ![In: IACR Cryptol. ePrint Arch. 2022, pp. 868, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP BibTeX RDF |
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13 | Yuehai Chen, Huarun Chen, Shaozhen Chen, Chao Han, Wujian Ye, Yijun Liu, Huihui Zhou |
DITES: A Lightweight and Flexible Dual-Core Isolated Trusted Execution SoC Based on RISC-V. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sensors ![In: Sensors 22(16), pp. 5981, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Seonghwan Park, Dongwook Kang, Jeonghwan Kang, Donghyun Kwon |
Bratter: An Instruction Set Extension for Forward Control-Flow Integrity in RISC-V. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sensors ![In: Sensors 22(4), pp. 1392, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | María José Belda, Katzalin Olcoz, Fernando Castro, Francisco Tirado |
Optimization of a line detection algorithm for autonomous vehicles on a RISC-V with accelerator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comput. Sci. Technol. ![In: J. Comput. Sci. Technol. 22(2), pp. 10, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Meng Liu |
A co-design method of customized ISA design space exploration and fixed-point library construction for RISC-V dedicated processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 19(13), pp. 20220244, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Davide Zoni, Andrea Galimberti |
Cost-effective fixed-point hardware support for RISC-V embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Syst. Archit. ![In: J. Syst. Archit. 126, pp. 102476, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Sallar Ahmadi-Pour, Vladimir Herdt, Rolf Drechsler |
The MicroRV32 framework: An accessible and configurable open source RISC-V cross-level platform for education and research. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Syst. Archit. ![In: J. Syst. Archit. 133, pp. 102757, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Yu Wang, Jinting Wu, Tai Yue, Zhenyu Ning, Fengwei Zhang |
RetTag: hardware-assisted return address integrity on RISC-V. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EuroSec@EUROSYS ![In: EuroSec@EUROSYS 2022: Proceedings of the 15th European Workshop on Systems Security, Rennes, France, April 5-8, 2022, pp. 50-56, 2022, ACM, 978-1-4503-9255-6. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Milan Funck, Vladimir Herdt, Rolf Drechsler |
Virtual Prototype driven Design, Implementation and Evaluation of RISC-V Instruction Set Extensions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2022, Prague, Czech Republic, April 6-8, 2022, pp. 14-19, 2022, IEEE, 978-1-6654-9431-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Weiyan Zhang, Mehran Goli, Rolf Drechsler |
Early Performance Estimation of Embedded Software on RISC-V Processor using Linear Regression. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2022, Prague, Czech Republic, April 6-8, 2022, pp. 20-25, 2022, IEEE, 978-1-6654-9431-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Patrick Karl, Tim Fritzmann, Georg Sigl |
Hardware Accelerated FrodoKEM on RISC-V. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2022, Prague, Czech Republic, April 6-8, 2022, pp. 154-159, 2022, IEEE, 978-1-6654-9431-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Quentin Ducasse, Guillermo Polito, Pablo Tesone, Pascal Cotret, Loïc Lagadec |
Porting a JIT Compiler to RISC-V: Challenges and Opportunities. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MPLR ![In: Proceedings of the 19th International Conference on Managed Programming Languages and Runtimes, MPLR 2022, Brussels, Belgium, September 14-15, 2022, pp. 112-118, 2022, ACM, 978-1-4503-9696-7. The full citation details ...](Pics/full.jpeg) |
2022 |
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13 | Blaise Tine, Varun Saxena, Santosh Srivatsan, Joshua R. Simpson, Fadi Alzammar, Liam Paul Cooper, Sam Jijina, Swetha Rajagoplan, Tejaswini Anand Kumar, Jeffrey Young 0001, Hyesoon Kim |
Accelerating Graphic Rendering on Programmable RISC-V GPUs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HCS ![In: 2022 IEEE Hot Chips 34 Symposium, HCS 2022, Cupertino, CA, USA, August 21-23, 2022, pp. 1-15, 2022, IEEE, 978-1-6654-6028-6. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Francesco Cosimi, Fabrizio Tronci, Sergio Saponara, Paolo Gai |
Analysis, Hardware Specification and Design of a Programmable Performance Monitoring Unit (PPMU) for RISC-V ECUs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SMARTCOMP ![In: 2022 IEEE International Conference on Smart Computing, SMARTCOMP 2022, Helsinki, Finland, June 20-24, 2022, pp. 213-218, 2022, IEEE, 978-1-6654-8152-6. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Davide Nadalini, Manuele Rusci, Giuseppe Tagliavini, Leonardo Ravaglia, Luca Benini, Francesco Conti 0001 |
PULP-TrainLib: Enabling On-Device Training for RISC-V Multi-core MCUs Through Performance-Driven Autotuning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Embedded Computer Systems: Architectures, Modeling, and Simulation - 22nd International Conference, SAMOS 2022, Samos, Greece, July 3-7, 2022, Proceedings, pp. 200-216, 2022, Springer, 978-3-031-15073-9. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Alessandro Ottaviano, Robert Balas, Giovanni Bambini, Corrado Bonfanti, Simone Benatti, Davide Rossi, Luca Benini, Andrea Bartolini |
ControlPULP: A RISC-V Power Controller for HPC Processors with Parallel Control-Law Computation Acceleration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Embedded Computer Systems: Architectures, Modeling, and Simulation - 22nd International Conference, SAMOS 2022, Samos, Greece, July 3-7, 2022, Proceedings, pp. 120-135, 2022, Springer, 978-3-031-15073-9. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Keisuke Sakamoto, Masanori Natsui, Takahiro Hanyu |
Energy-Efficient Nonvolatile RISC-V CPU with a Custom Instruction-Controlled Accelerator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MWSCAS ![In: 65th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2022, Fukuoka, Japan, August 7-10, 2022, pp. 1-4, 2022, IEEE, 978-1-6654-0279-8. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Hidetaro Tanaka, Tomoaki Tanaka, Ryosuke Higashi, Tsutomu Sekibe, Shuichi Takada, Hironori Nakajo |
Implementation of a RISC-V SMT Core in an AI processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoICT ![In: The 11th International Symposium on Information and Communication Technology, SoICT 2022, Hanoi, Vietnam, December 1-3, 2022, pp. 15-22, 2022, ACM, 978-1-4503-9725-4. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Lucas Klemmer, Daniel Große |
An Exploration Platform for Microcoded RISC-V Cores leveraging the One Instruction Set Computer Principle. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2022, Nicosia, Cyprus, July 4-6, 2022, pp. 38-43, 2022, IEEE, 978-1-6654-6605-9. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Adeboye Stephen Oyeniran, Maksim Jenihhin, Jaan Raik, Raimund Ubar |
High-Level Fault Diagnosis in RISC Processors with Implementation-Independent Functional Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2022, Nicosia, Cyprus, July 4-6, 2022, pp. 32-37, 2022, IEEE, 978-1-6654-6605-9. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Halil Kükner, Gökhan Kaplayan, Ahmet Efe, Mehmet Ali Gülden |
RISC-V Processor Trace Encoder with Multiple Instructions Retirement Support. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022, pp. 1-6, 2022, IEEE, 978-1-6654-9005-4. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Nicolas Gerlin, Endri Kaja, Monideep Bora, Keerthikumara Devarajegowda, Dominik Stoffel, Wolfgang Kunz, Wolfgang Ecker |
Design of a Tightly-Coupled RISC-V Physical Memory Protection Unit for Online Error Detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022, pp. 1-6, 2022, IEEE, 978-1-6654-9005-4. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Chun-Jen Tsai, Yi-De Lee |
Embedded TCP/IP Controller for a RISC-V SoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022, pp. 1-6, 2022, IEEE, 978-1-6654-9005-4. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Simon Butler 0001, Jonas Gamalielsson, Björn Lundell, Christoffer Brax, Tomas Persson, Anders Mattsson, Tomas Gustavsson, Jonas Feist, Jonas Öberg |
An Exploration of Openness in Hardware and Software Through Implementation of a RISC-V Based Desktop Computer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
OpenSym ![In: OpenSym 2022: The 18th International Symposium on Open Collaboration, Madrid, Spain, September 7 - 9, 2022, pp. 4:1-4:11, 2022, ACM, 978-1-4503-9845-9. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Yvan Tortorella, Luca Bertaccini, Davide Rossi, Luca Benini, Francesco Conti 0001 |
RedMulE: A Compact FP16 Matrix-Multiplication Accelerator for Adaptive Deep Learning on RISC-V-Based Ultra-Low-Power SoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2022 Design, Automation & Test in Europe Conference & Exhibition, DATE 2022, Antwerp, Belgium, March 14-23, 2022, pp. 1099-1102, 2022, IEEE, 978-3-9819263-6-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Vincenzo Maisto, Alessandro Cilardo |
A Pluggable Vector Unit for RISC-V Vector Extension. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2022 Design, Automation & Test in Europe Conference & Exhibition, DATE 2022, Antwerp, Belgium, March 14-23, 2022, pp. 1143-1148, 2022, IEEE, 978-3-9819263-6-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Dongyun Kam, Jung Gyu Min, Jongho Yoon, Sunmean Kim, Seokhyeong Kang, Youngjoo Lee |
Design and Evaluation Frameworks for Advanced RISC-based Ternary Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2022 Design, Automation & Test in Europe Conference & Exhibition, DATE 2022, Antwerp, Belgium, March 14-23, 2022, pp. 1077-1082, 2022, IEEE, 978-3-9819263-6-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Wolfgang Ecker, Peer Adelt, Wolfgang Müller 0003, Reinhold Heckmann, Milos Krstic, Vladimir Herdt, Rolf Drechsler, Gerhard Angst, Ralf Wimmer 0001, Andreas Mauderer, Rafael Stahl, Karsten Emrich, Daniel Mueller-Gritschneder, Bernd Becker 0001, Philipp Scholl, Eyck Jentzsch, Jan Schlamelcher, Kim Grüttner, Paul Palomero Bernardo, Oliver Bringmann 0001, Mihaela Damian, Julian Oppermann, Andreas Koch 0001, Jörg Bormann, Johannes Partzsch, Christian Mayr 0001, Wolfgang Kunz |
The Scale4Edge RISC-V Ecosystem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2022 Design, Automation & Test in Europe Conference & Exhibition, DATE 2022, Antwerp, Belgium, March 14-23, 2022, pp. 808-813, 2022, IEEE, 978-3-9819263-6-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Zhanyuan Gao, Laiping Zhao, Haonan Chen |
A Trigonometric Function Instruction Set Extension Method Based on RISC-V. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICIS ![In: 22nd IEEE/ACIS International Conference on Computer and Information Science, ICIS 2022, Zhuhai, China, June 26-28, 2022, pp. 119-126, 2022, IEEE, 978-1-6654-9463-2. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Anu Verma, Priyamvada Sharma, Bishnu Prasad Das |
RISC-V Core with Approximate Multiplier for Error-Tolerant Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 25th Euromicro Conference on Digital System Design, DSD 2022, Maspalomas, Spain, August 31 - Sept. 2, 2022, pp. 239-246, 2022, IEEE, 978-1-6654-7404-7. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Parangat Sud, Shekoufeh Neisarian, Elif Bilge Kavun |
Evaluating Cryptographic Extensions On A RISC-V Simulation Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 25th Euromicro Conference on Digital System Design, DSD 2022, Maspalomas, Spain, August 31 - Sept. 2, 2022, pp. 548-555, 2022, IEEE, 978-1-6654-7404-7. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Víctor Soria Pardos, Max Doblas, Guillem López-Paradís, Gerard Candón, Narcís Rodas, Xavier Carril, Pau Fontova-Musté, Neiel Leyva, Santiago Marco-Sola, Miquel Moretó |
Sargantana: A 1 GHz+ In-Order RISC-V Processor with SIMD Vector Extensions in 22nm FD-SOI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 25th Euromicro Conference on Digital System Design, DSD 2022, Maspalomas, Spain, August 31 - Sept. 2, 2022, pp. 254-261, 2022, IEEE, 978-1-6654-7404-7. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Tobias Scheipel, Florian Angermair, Marcel Baunach |
moreMCU: A Runtime-reconfigurable RISC-V Platform for Sustainable Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 25th Euromicro Conference on Digital System Design, DSD 2022, Maspalomas, Spain, August 31 - Sept. 2, 2022, pp. 24-31, 2022, IEEE, 978-1-6654-7404-7. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Anthony Zgheib, Olivier Potin, Jean-Baptiste Rigaud, Jean-Max Dutertre |
A CFI Verification System based on the RISC-V Instruction Trace Encoder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 25th Euromicro Conference on Digital System Design, DSD 2022, Maspalomas, Spain, August 31 - Sept. 2, 2022, pp. 456-463, 2022, IEEE, 978-1-6654-7404-7. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Sallar Ahmadi-Pour, Sangeet Saha, Vladimir Herdt, Rolf Drechsler, Klaus D. McDonald-Maier |
Task Mapping and Scheduling in FPGA-based Heterogeneous Real-time Systems: A RISC-V Case-Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 25th Euromicro Conference on Digital System Design, DSD 2022, Maspalomas, Spain, August 31 - Sept. 2, 2022, pp. 134-141, 2022, IEEE, 978-1-6654-7404-7. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Antti Nurmi, Antti Rautakoura, Henri Lunnikivi, Timo D. Hämäläinen |
A Resilient System Design to Boot a RISC-V MPSoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 25th Euromicro Conference on Digital System Design, DSD 2022, Maspalomas, Spain, August 31 - Sept. 2, 2022, pp. 232-238, 2022, IEEE, 978-1-6654-7404-7. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Johannes Knödtel, Sebastian Rachuj, Marc Reichenbach |
Suitability of ISAs for Data Paths Based on Redundant Number Systems: Is RISC-V the best? ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 25th Euromicro Conference on Digital System Design, DSD 2022, Maspalomas, Spain, August 31 - Sept. 2, 2022, pp. 247-253, 2022, IEEE, 978-1-6654-7404-7. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Yinan Xu 0001, Zihao Yu, Dan Tang, Guokai Chen, Lu Chen, Lingrui Gou, Yue Jin, Qianruo Li, Xin Li, Zuojun Li, Jiawei Lin, Tong Liu, Zhigang Liu, Jiazhan Tan, Huaqiang Wang, Huizhe Wang, Kaifan Wang, Chuanqi Zhang, Fawang Zhang, Linjuan Zhang, Zifei Zhang, Yangyang Zhao, Yaoyang Zhou, Yike Zhou, Jiangrui Zou, Ye Cai, Dandan Huan, Zusong Li, Jiye Zhao, Zihao Chen, Wei He, Qiyuan Quan, Xingwu Liu, Sa Wang, Kan Shi, Ninghui Sun, Yungang Bao |
Towards Developing High Performance RISC-V Processors Using Agile Methodology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 55th IEEE/ACM International Symposium on Microarchitecture, MICRO 2022, Chicago, IL, USA, October 1-5, 2022, pp. 1178-1199, 2022, IEEE, 978-1-6654-6272-3. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Jien Hau Ng, Chee Hong Ang, Hwa Chaw Law |
A Realization of IO Physical Memory Protection for RISC-V Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MCSoC ![In: 15th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, MCSoC 2022, Penang, Malaysia, December 19-22, 2022, pp. 375-380, 2022, IEEE, 978-1-6654-6499-4. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Sih Pin Tan, Yung It Ho |
Scalability of Post-Silicon Test Generation for Multi-core RISC-V SOC Validation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MCSoC ![In: 15th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, MCSoC 2022, Penang, Malaysia, December 19-22, 2022, pp. 14-17, 2022, IEEE, 978-1-6654-6499-4. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai |
Evaluation of Different Microarchitectures for Energy-Efficient RISC-V Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MCSoC ![In: 15th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, MCSoC 2022, Penang, Malaysia, December 19-22, 2022, pp. 78-84, 2022, IEEE, 978-1-6654-6499-4. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Viktor Razilov, Emil Matús, Gerhard P. Fettweis |
Communications Signal Processing Using RISC-V Vector Extension. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWCMC ![In: 2022 International Wireless Communications and Mobile Computing, IWCMC 2022, Dubrovnik, Croatia, May 30 - June 3, 2022, pp. 690-695, 2022, IEEE, 978-1-6654-6749-0. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Tobias Kaiser, Friedel Gerfers |
Pasithea-1: An Energy-Efficient Self-contained CGRA with RISC-Like ISA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARCS ![In: Architecture of Computing Systems - 35th International Conference, ARCS 2022, Heilbronn, Germany, September 13-15, 2022, Proceedings, pp. 33-47, 2022, Springer, 978-3-031-21866-8. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Davide Bove |
Secure Services for Standard RISC-V Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARES ![In: ARES 2022: The 17th International Conference on Availability, Reliability and Security, Vienna,Austria, August 23 - 26, 2022, pp. 23:1-23:7, 2022, ACM, 978-1-4503-9670-7. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Amin Sarihi, Michael A. Schoenfelder, Abdel-Hameed A. Badawy |
Performance Evaluation of an Out-of-Order RISC-V CPU: A SPEC INT 2017 Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPCCC ![In: IEEE International Performance, Computing, and Communications Conference, IPCCC 2022, Austin, TX, USA, November 11-13, 2022, pp. 418-419, 2022, IEEE, 978-1-6654-8018-5. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Jihye Lee, Whijin Kim, Sohyeon Kim, Ji-Hoon Kim |
Post-Quantum Cryptography Coprocessor for RISC-V CPU Core. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICEIC ![In: International Conference on Electronics, Information, and Communication, ICEIC 2022, Jeju, Korea, Republic of, February 6-9, 2022, pp. 1-2, 2022, IEEE, 978-1-6654-0934-6. The full citation details ...](Pics/full.jpeg) |
2022 |
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