Search results for "Programmability"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
9	Yan Lin 0001, Fei Li 0003, Lei He 0001	Routing track duplication with fine-grained power-gating for FPGA interconnect power reduction.	ASP-DAC	2005	DBLP DOI BibTeX RDF
9	Sanjay Agrawal 0001, Surajit Chaudhuri, Lubor Kollár, Arunprasad P. Marathe, Vivek R. Narasayya, Manoj Syamala	Database tuning advisor for microsoft SQL server 2005: demo.	SIGMOD Conference	2005	DBLP DOI BibTeX RDF
9	Apostolos Malatras, George Pavlou, Stylianos Gouveris, Sivapathalingham Sivavakeesar, Vassilios Karakoidas	Self-Configuring and Optimizing Mobile Ad Hoc Networks.	ICAC	2005	DBLP DOI BibTeX RDF
9	Andrés David García García, Luis Fernando González Pérez, Reynaldo Félix Acuña	Power Consumption Management on FPGAs.	CONIELECOMP	2005	DBLP DOI BibTeX RDF	Genetic Algorithms, Field Programmable Gate Array, Power Consumption, Partial Reconfiguration, Circuit Design
9	Steven A. Guccione	Programming Configurable Multiprocessors.	IPDPS	2005	DBLP DOI BibTeX RDF
9	Zhong-Xin Feng, Min Tang 0001, Jinxiang Dong, Shang-Ching Chou	Real-Time Rain Simulation.	CSCWD (Selected papers)	2005	DBLP DOI BibTeX RDF
9	X. Baele, Nadine Warzée	Real Time L-System Generated Trees Based on Modern Graphics Hardware.	SMI	2005	DBLP DOI BibTeX RDF
9	Mario Cagalj, Saurabh Ganeriwal, Imad Aad, Jean-Pierre Hubaux	On selfish behavior in CSMA/CA networks.	INFOCOM	2005	DBLP DOI BibTeX RDF
9	Vivek Vaidya 0001, Rakesh Mullick, Navneeth Subramanian	Volume Exploration Using Spatially Linked Transfer Functions.	IEEE Visualization	2005	DBLP DOI BibTeX RDF
9	Tao Wang 0004, Nan Di, Jian Shen, Min Liu	LilyTask Parallel Language 3.5 - Approach towards Task Parallel Programming in Heterogeneous SMP-Clusters.	ICPP Workshops	2005	DBLP DOI BibTeX RDF
9	Suman Mamidi, Emily R. Blem, Michael J. Schulte, C. John Glossner, Daniel Iancu, Andrei Iancu, Mayan Moudgill, Sanjay Jinturkar	Instruction set extensions for software defined radio on a multithreaded processor.	CASES	2005	DBLP DOI BibTeX RDF	convolutional encoding, multithreading, forward error correction, software defined radio, Reed-Solomon coding, instruction set extensions, digital signal processor, Viterbi decoding, turbo decoding
9	Vasilis Dialinos, Rosa M. Badia, Raül Sirvent, Josep M. Pérez, Jesús Labarta	Implementing phylogenetic inference with GRID superscalar.	CCGRID	2005	DBLP DOI BibTeX RDF
9	Tao Liu, Xiao-Feng Li, Lixia Liu, Chengyong Wu, Roy Ju	Optimizing Packet Accesses for a Domain Specific Language on Network Processors.	LCPC	2005	DBLP DOI BibTeX RDF
9	Athon Zanikopoulos, Pieter Harpe, Hans Hegt, Arthur H. M. van Roermund	A flexible ADC approach for mixed-signal SoC platforms.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
9	Ravi Chawla, Christopher M. Twigg, Paul E. Hasler	An analog modulator/demodulator using a programmable arbitrary waveform generator.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
9	Johan Lambie, Francesc Moll Echeto, José Luis González 0001, Antonio Rubio 0001	Asynchronous pulse logic cell for threshold logic and Boolean networks.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
9	Jong-wan Seo, Myong-Chul Shin	A study on an ASIC design technique for digital protective relays.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
9	Phil Corbishley, Esther Rodríguez-Villegas	Programmable switched-current floating-gate cells.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
9	Qiong Zhang, Lu Ye, Zhigeng Pan	Physically-Based Sound Synthesis on GPUs.	ICEC	2005	DBLP DOI BibTeX RDF
9	Amilcar do Carmo Lucas, Rolf Ernst	An Image Processor for Digital Film.	ASAP	2005	DBLP DOI BibTeX RDF	weak-programing, stream-based architechture, digital .lm, recon.gurable, FPGA
9	Suman Mamidi, Daniel Iancu, Andrei Iancu, Michael J. Schulte, John Glossner	Instruction Set Extensions for Reed-Solomon Encoding and Decoding.	ASAP	2005	DBLP DOI BibTeX RDF
9	Kuan Zhou, John F. McDonald 0001	Multi-GHz SiGe design methodologies for reconfigurable computing.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	CLB, virtex, FPGA, SiGe
9	Piotr Augustyniak	Adaptive Wearable Vital Signs Monitor for Home Care and Sports.	CORES	2005	DBLP DOI BibTeX RDF
9	Chung-Kai Chen, Yu-Hao Chang, Cheng-Wei Chen, Yu-Tin Chen, Chih-Chieh Yang, Jenq Kuen Lee	Efficient Switching Supports of Distributed .NET Remoting with Network Processors.	ICPP	2005	DBLP DOI BibTeX RDF
9	Masaki Ito, Jin Nakazawa, Hideyuki Tokuda	mPATH: An Interactive Visualization Framework for Behavior History.	AINA	2005	DBLP DOI BibTeX RDF
9	Jingyi Yu, Jason C. Yang, Leonard McMillan	Real-time reflection mapping with parallax.	SI3D	2005	DBLP DOI BibTeX RDF	reflections, light fields, pixel shader
9	Fei Sun, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha	Synthesis of Application-Specific Heterogeneous Multiprocessor Architectures Using Extensible Processors.	VLSI Design	2005	DBLP DOI BibTeX RDF
9	Thomas Repantis, Christos D. Antonopoulos, Vana Kalogeraki, Theodore S. Papatheodorou	A Case for Dynamic Page Migration in Multiple-Writer Software DSM Systems.	CLUSTER	2005	DBLP DOI BibTeX RDF
9	Miro Milanovic, Mitja Truntic, Primoz Slibar	FPGA Implementation of Digital Controller for DC-DC Buck Converter.	IWSOC	2005	DBLP DOI BibTeX RDF
9	Yan Lin 0001, Lei He 0001	Leakage efficient chip-level dual-Vdd assignment with time slack allocation for FPGA power reduction.	DAC	2005	DBLP DOI BibTeX RDF	programmable-Vdd, time slack, FPGA, low power
9	Sean W. Smith	Outbound authentication for programmable secure coprocessors.	Int. J. Inf. Sec.	2004	DBLP DOI BibTeX RDF	Secure coprocessors, Authentication, Trust, Attestation
9	Alireza Hodjat, Ingrid Verbauwhede	High-Throughput Programmable Cryptocoprocessor.	IEEE Micro	2004	DBLP DOI BibTeX RDF
9	George Lawton	Will Network Processor Units Live Up to Their Promise?	Computer	2004	DBLP DOI BibTeX RDF
9	Zhining Huang, Sharad Malik, Nahri Moreano, Guido Araujo	The design of dynamically reconfigurable datapath coprocessors.	ACM Trans. Embed. Comput. Syst.	2004	DBLP DOI BibTeX RDF	coarse-grain reconfigurable fabric, reconfigurable datapath, Loop pipelining, interconnection design, datapath synthesis
9	Benjamin B. Bederson, Jesse Grosjean, Jon Meyer	Toolkit Design for Interactive Structured Graphics.	IEEE Trans. Software Eng.	2004	DBLP DOI BibTeX RDF
9	Max H. Garzon, Derrel Blain, Andrew Neel	Virtual test tubes.	Nat. Comput.	2004	DBLP DOI BibTeX RDF	molecular kinetics, simulations of Brownian motion, virtual test tubes, distributed computing, biomolecular computing
9	Manuel Díaz, Bartolomé Rubio, Enrique Soler, José M. Troya	SBASCO: Skeleton-Based Scientific Components.	PDP	2004	DBLP DOI BibTeX RDF
9	Zhenjiang Hu, Shin-Cheng Mu, Masato Takeichi	A programmable editor for developing structured documents based on bidirectional transformations.	PEPM	2004	DBLP DOI BibTeX RDF	bidirectional transformation, functional programming, editor, view updating, document engineering
9	Jian-Qin Liu, Katsunori Shimohara	A Novel Programmable Molecular Computing Method Based on Signaling Pathways Regulated by Rho-GTPases in Living MDCK Epithelial Mammalian Cells.	PPSN	2004	DBLP DOI BibTeX RDF
9	Peter Zipf, Claude Stötzler, Manfred Glesner	A Configurable Pipelined State Machine as a Hybrid ASIC and Configurable Architecture.	ISVLSI	2004	DBLP DOI BibTeX RDF
9	Shane Magrath, Robin Braun, Fernando Cuervo	Policy Interoperability and Network Autonomics.	WAC	2004	DBLP DOI BibTeX RDF
9	Fei Li 0003, Yan Lin 0001, Lei He 0001, Jason Cong	Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics.	FPGA	2004	DBLP DOI BibTeX RDF	FPGA, low power, power efficient, dual-Vdd, dual-Vt
9	Sumeet Sobti, Junwen Lai, Yilei Shao, Nitin Garg, Chi Zhang 0070, Ming Zhang, Fengzhou Zheng, Arvind Krishnamurthy, Randolph Y. Wang	Network-Embedded Programmable Storage and Its Applications.	NETWORKING	2004	DBLP DOI BibTeX RDF
9	Ingrid Verbauwhede, Patrick Schaumont, Christian Piguet, Bart Kienhuis	Architectures and Design Techniques for Energy Efficient Embedded DSP and Multimedia Processing.	DATE	2004	DBLP DOI BibTeX RDF
9	Luís Rolíndez, Salvador Mir, Guillaume Prenat, Ahcène Bounceur	A 0.18 µm CMOS Implementation of On-chip Analogue Test Signal Generation from Digital Test Patterns.	DATE	2004	DBLP DOI BibTeX RDF
9	Aneesh Koorapaty, V. Kheterpal, Padmini Gopalakrishnan, M. Fu, Lawrence T. Pileggi	Exploring Logic Block Granularity for Regular Fabrics.	DATE	2004	DBLP DOI BibTeX RDF
9	Adnan Iqbal, Malik Sikander Hayat Khiyal, Mohammad Sher	A Simple Practical Active Network Architecture.	CIT	2004	DBLP DOI BibTeX RDF
9	Anthony LaMarca, Maya Rodrig	Oasis: An Architecture for Simplified Data Management and Disconnected Operation.	ARCS	2004	DBLP DOI BibTeX RDF
9	Michael Uhler	The New Economics of Embedded Systems.	SCOPES	2004	DBLP DOI BibTeX RDF
9	Gordon J. Brebner	Programmable Logic Has More Computational Power than Fixed Logic.	FPL	2004	DBLP DOI BibTeX RDF
9	Erik Schüler, Luigi Carro	A Low Power FPAA for Wide Band Applications.	FPL	2004	DBLP DOI BibTeX RDF
9	Kenneth Moreland, Edward Angel	A Fast High Accuracy Volume Renderer for Unstructured Data.	VolVis	2004	DBLP DOI BibTeX RDF	volume rendering
9	David Callahan, Bradford L. Chamberlain, Hans P. Zima	The Cascade High Productivity Language.	HIPS	2004	DBLP DOI BibTeX RDF
9	Danny van Noort	A Programmable Molecular Computer in Microreactors.	DNA	2004	DBLP DOI BibTeX RDF
9	Ge Wang 0002, Perry R. Cook	ChucK: a programming language for on-the-fly, real-time audio synthesis and multimedia.	ACM Multimedia	2004	DBLP DOI BibTeX RDF	audio synthesis, multimedia, real-time, compiler, concurrency, synchronization, virtual machine, programming language, signal processing
9	Esam El-Araby, Mohamed Taher, Kris Gaj, Tarek A. El-Ghazawi, David Caliga, Nikitas A. Alexandridis	System-Level Parallelism and Throughput Optimization in Designing Reconfigurable Computing Applications.	IPDPS	2004	DBLP DOI BibTeX RDF
9	Rob F. Van der Wijngaart, Michael A. Frumkin	Evaluating the Information Power Grid Using the NAS Grid Benchmarks.	IPDPS	2004	DBLP DOI BibTeX RDF
9	Sakir Sezer, Ciaran Toal, Emi Garcia, Victoria Stewart	A Reconfigurable Tag Computation Architecture for Terabit Packet Scheduling.	IPDPS	2004	DBLP DOI BibTeX RDF	reconfigurable packet scheduling, SCFQ, Reconfigurable architectures, WFQ, network processing
9	Carolina Selva, Cosimo Torelli, Danilo Rimondi, Rita Zappa, Stefano Corbani, Giovanni Mastrodomenico, Lara Albani	A Programmable Built-in Self-Diagnosis for Embedded SRAM.	MTDT	2004	DBLP DOI BibTeX RDF
9	Ju-Ho Sohn, Ramchan Woo, Hoi-Jun Yoo	A programmable vertex shader with fixed-point SIMD datapath for low power wireless applications.	Graphics Hardware	2004	DBLP DOI BibTeX RDF
9	Youquan Liu, Xuehui Liu, Enhua Wu	Real-Time 3D Fluid Simulation on GPU with Complex Obstacles.	PG	2004	DBLP DOI BibTeX RDF
9	Gabriele Jost, Jesús Labarta, Judit Giménez	Paramedir: A Tool for Programmable Performance Analysis.	International Conference on Computational Science	2004	DBLP DOI BibTeX RDF
9	Gonggui Xu, Haydar Bilhan	A programmable gain amplifier buffer design for video applications.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
9	Alexander Bogomjakov, Craig Gotsman	GPU-Assisted Z-Field Simplification.	3DPVT	2004	DBLP DOI BibTeX RDF
9	Gordon J. Brebner, Philip James-Roxby, Eric Keller, Chidamber Kulkarni	Hyper-Programmable Architectures for Adaptable Networked Systems.	ASAP	2004	DBLP DOI BibTeX RDF
9	Luca Macchiarulo, Consolato F. Caccamo, Davide Pandini	A comparison between mask- and field-programmable routing structures on industrial FPGA architectures.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	mask-programmable, FPGA, routing, interconnect architectures
9	Seong-Kyu Song, Scott Nettles	Using Active Networking's Adaptability in Ad Hoc Routing.	IWAN	2004	DBLP DOI BibTeX RDF	Adaptation, MANET, Active Networking, Ad hoc Routing
9	Gísli Hjálmtýsson, Ólafur Ragnar Helgason, Björn Brynjúlfsson	Simple Active Mechanisms for Measuring and Monitoring Service Level Topologies.	IWAN	2004	DBLP DOI BibTeX RDF	Service aware networking, measurement, overlays, service management, VPN
9	Lukas Ruf, Ralph Keller, Bernhard Plattner	A Scalable High-performance Router Platform Supporting Dynamic Service Extensibility On Network and Host Processors.	ICPS	2004	DBLP DOI BibTeX RDF
9	John Y. Oliver, Ravishankar Rao, Paul Sultana, Jedidiah R. Crandall, Erik Czernikowski, Leslie W. Jones IV, Diana Franklin, Venkatesh Akella, Frederic T. Chong	Synchroscalar: A Multiple Clock Domain, Power-Aware, Tile-Based Embedded Processor.	ISCA	2004	DBLP DOI BibTeX RDF
9	Morgan McGuire, John F. Hughes	Hardware-determined feature edges.	NPAR	2004	DBLP DOI BibTeX RDF	GPU, NPR, contour, silhouette, shadow volume
9	Weikuan Yu, Dhabaleswar K. Panda 0001, Darius Buntinas	Scalable, high-performance NIC-based all-to-all broadcast over Myrinet/GM.	CLUSTER	2004	DBLP DOI BibTeX RDF
9	Benny Wang-Leung Cheung, Cho-Li Wang, Francis Chi-Moon Lau	LOTS: a software DSM supporting large object space.	CLUSTER	2004	DBLP DOI BibTeX RDF
9	Chris Rowen, Steve Leibson	Flexible architectures for engineering successful SOCs.	DAC	2004	DBLP DOI BibTeX RDF	processor cores, MPSOC, RISC, RTL, SOC
9	Fei Li 0003, Yan Lin 0001, Lei He 0001	FPGA power reduction using configurable dual-Vdd.	DAC	2004	DBLP DOI BibTeX RDF	FPGA, low power, configurable, power efficient, dual-Vdd
9	Ilija Hadzic, Jonathan M. Smith	Balancing performance and flexibility with hardware support for network architectures.	ACM Trans. Comput. Syst.	2003	DBLP DOI BibTeX RDF	P4, performance, FPGA, computer networking, hardware, flexibility, programmable networks, programmable logic devices, protocol processing
9	Geoff Coulson, Gordon S. Blair, David Hutchison 0001, Ackbar Joolia, Kevin Lee, Jo Ueyama, Antônio Tadeu A. Gomes, Yimin Ye	NETKIT: a software component-based approach to programmable networking.	Comput. Commun. Rev.	2003	DBLP DOI BibTeX RDF	middleware, components, reflection, programmable networking
9	John Harrison 0001	Formal Verification of Square Root Algorithms.	Formal Methods Syst. Des.	2003	DBLP DOI BibTeX RDF	formal verification, floating-point arithmetic, automated theorem proving
9	Sheng Uei Guan, Wei Liu	Self-Modifiable Color Petri Nets for Modeling User Manipulation and Network Event Handling.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	Self-Modifiable Color Petri Nets (SMCPN), color tokens, self-modifying protocols, multimedia synchronization
9	Girish Venkataramani, Walid A. Najjar, Fadi J. Kurdahi, Nader Bagherzadeh, A. P. Wim Böhm, Jeffrey Hammes	Automatic compilation to a coarse-grained reconfigurable system-opn-chip.	ACM Trans. Embed. Comput. Syst.	2003	DBLP DOI BibTeX RDF	compilers, Reconfigurable computing, SIMD
9	Tilman Glökler, Andreas Hoffmann 0002, Heinrich Meyr	Methodical Low-Power ASIP Design Space Exploration.	J. VLSI Signal Process.	2003	DBLP DOI BibTeX RDF	ICORE, low power, ASIP, application-specific instruction set processor, low energy, LISA
9	Ranieri Baraglia, Marco Danelutto, Domenico Laforenza, Salvatore Orlando 0001, Paolo Palmerini, Paolo Pesciullesi, Raffaele Perego 0001, Marco Vanneschi	AssistConf: a Grid configuration tool for the ASSIST parallel programming environment.	PDP	2003	DBLP DOI BibTeX RDF
9	Marco Vanneschi	ASSIST High-Performance Programming Environment: Application Experiences and Grid Evolution.	PVM/MPI	2003	DBLP DOI BibTeX RDF
9	Om Prakash Gangwal, Johan G. W. M. Janssen, Selliah Rathnam, Erwin B. Bellers, Marc Duranton	Understanding Video Pixel Processing Applications for Flexible Implementations.	DSD	2003	DBLP DOI BibTeX RDF
9	Abhijeet Ghosh, Poojan Prabhu, Arie E. Kaufman, Klaus Mueller 0001	Hardware Assisted Multichannel Volume Rendering.	Computer Graphics International	2003	DBLP DOI BibTeX RDF	post-classification, volume mixing, Visible Human, VolumePro 1000, graphics hardware, transfer functions, multi-modal, parallel rendering, image compositing, terrain rendering, Multichannel, distributed rendering
9	Kaoru Sugita, Takeshi Naemura, Hiroshi Harashima	Performance evaluation of programmable graphics hardware for image filtering and stereo matching.	VRST	2003	DBLP DOI BibTeX RDF	stereo matching, programmable graphics hardware, image filtering, real-time image processing
9	Brendan McAllister, Sakir Sezer, Ciaran Toal	Custom Tag Computation Circuit for a 10Gbps SCFQ Scheduler.	FPL	2003	DBLP DOI BibTeX RDF
9	Peter Bøgh Andersen, Jens Bennedsen, Steffen Brandorff, Michael E. Caspersen, Jesper Mosegaard	Teaching programming to liberal arts students: a narrative media approach.	ITiCSE	2003	DBLP DOI BibTeX RDF	literal arts students, introductory programming, programming education, non-majors, narration
9	Wei Ming Lim, Mohammed Benaissa	Design space exploration of a hardware-software co-designed GF(2m) galois field processor for forward error correction and cryptography.	CODES+ISSS	2003	DBLP DOI BibTeX RDF	GF(2m) arithmetic, forward error control coding, galois field processor, cryptography, advanced encryption standard, elliptic curve cryptography, design space exploration, Reed-Solomon code, hardware-software co-design, BCH code
9	Anthony L. Slade, Brent E. Nelson, Brad L. Hutchings	Reconfigurable Computing Application Frameworks.	FCCM	2003	DBLP DOI BibTeX RDF
9	Mario Botsch, Leif Kobbelt	High-Quality Point-Based Rendering on Modern GPUs.	PG	2003	DBLP DOI BibTeX RDF
9	David Goodwin, Darin Petkov	Automatic generation of application specific processors.	CASES	2003	DBLP DOI BibTeX RDF	automatic instruction-set generation, ASIPs, configurable processors, extensible processors
9	Nikolaus Kerö, Thilo Sauter	Efficient Analysis of Mixed-Signal ASICs for Smart Sensors.	IEEE International Workshop on Rapid System Prototyping	2003	DBLP DOI BibTeX RDF
9	E. V. Krishnamurthy	Problems and Prospects for Quantum Computational Speed-up.	International Conference on Computational Science	2003	DBLP DOI BibTeX RDF
9	Farid Boussaïd, Douglas Chai, Abdesselam Bouzerdoum	On-Chip Skin Detection for Color CMOS Imagers.	ICMENS	2003	DBLP DOI BibTeX RDF
9	José L. Ausín, J. Francisco Duque-Carrillo, Guido Torelli, Jorge Sánchez Valverde	Non-uniform sampling SC circuits based on noise-shaping feedback coding.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
9	Fausto Borghetti, Massimiliano Gobbi, Andrea Fornasari, Piero Malcovati, Franco Maloberti, M. Pagano	A particle detector fully-programmable interface circuit for satellite applications.	ISCAS (3)	2003	DBLP DOI BibTeX RDF
9	Belén Calvo, Maria Teresa Sanz, Santiago Celma, Pedro A. Martínez 0001	A CMOS digitally tunable transconductor for video frequency operation.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
9	Masahiro Fujita, Satoshi Komatsu, Hiroshi Saito, Kenshu Seto, Thanyapat Sakunkonchak, Yoshihisa Kojima	Field Modifiable Architecture with FPGAs and its Design/Verification/Debugging Methodologies.	HICSS	2003	DBLP DOI BibTeX RDF
9	Adarsh K. Jain, Lin Yuan, Pushkin R. Pari, Gang Qu 0001	Zero overhead watermarking technique for FPGA designs.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	configuration bitstream, timing analyzer, user constraint file, zero overhead, performance, FPGA, place and route, IP protection