Search results for "RISC"

Hits ?▲	Authors	Title	Venue	Year	Link
13	Ahmed Kamaleldin, Diana Göhringer	AGILER: An Adaptive Heterogeneous Tile-Based Many-Core Architecture for RISC-V Processors.	IEEE Access	2022	DBLP DOI BibTeX RDF
13	Satyam Shukla, Kailash Chandra Ray	A Low-Overhead Reconfigurable RISC-V Quad-Core Processor Architecture for Fault-Tolerant Applications.	IEEE Access	2022	DBLP DOI BibTeX RDF
13	YoungBeom Kim, Seog Chung Seo	Optimized Implementation of PIPO Block Cipher on 32-Bit ARM and RISC-V Processors.	IEEE Access	2022	DBLP DOI BibTeX RDF
13	Shahriar Hadayeghparast, Siavash Bayat Sarmadi, Shahriar Ebrahimi	High-Speed Post-Quantum Cryptoprocessor Based on RISC-V Architecture for IoT.	IEEE Internet Things J.	2022	DBLP DOI BibTeX RDF
13	Yuanhu Cheng, Libo Huang, Yi-Jun Cui, Sheng Ma, Yongwen Wang, Bingcai Sui	RV16: An Ultra-Low-Cost Embedded RISC-V Processor Core.	J. Comput. Sci. Technol.	2022	DBLP DOI BibTeX RDF
13	Sankatali Venkateswarlu, Subrat Mishra, Herman Oprins, Bjorn Vermeersch, Moritz Brunion, Jun-Han Han, Mircea R. Stan, Pieter Weckx, Francky Catthoor	Thermal Performance Analysis of Mempool RISC-V Multicore SoC.	IEEE Trans. Very Large Scale Integr. Syst.	2022	DBLP DOI BibTeX RDF
13	Kleber Stangherlin, Manoj Sachdev	Design and Implementation of a Secure RISC-V Microprocessor.	IEEE Trans. Very Large Scale Integr. Syst.	2022	DBLP DOI BibTeX RDF
13	Cristián Ramírez, Adrián Castelló 0001, Enrique S. Quintana-Ortí	A BLIS-like matrix multiplication for machine learning in the RISC-V ISA-based GAP8 processor.	J. Supercomput.	2022	DBLP DOI BibTeX RDF
13	Markku-Juhani O. Saarinen, G. Richard Newell, Ben Marshall	Development of the RISC-V entropy source interface.	J. Cryptogr. Eng.	2022	DBLP DOI BibTeX RDF
13	Atharva Kalsekar, Rasika Khade, Krupa Jariwala, Chiranjoy Chattopadhyay	RISC-Net : rotation invariant siamese convolution network for floor plan image retrieval.	Multim. Tools Appl.	2022	DBLP DOI BibTeX RDF
13	Marco Cococcioni, Federico Rossi 0003, Emanuele Ruffaldi, Sergio Saponara	A Lightweight Posit Processing Unit for RISC-V Processors in Deep Neural Network Applications.	IEEE Trans. Emerg. Top. Comput.	2022	DBLP DOI BibTeX RDF
13	David Mallasén, Raul Murillo 0001, Alberto A. Del Barrio, Guillermo Botella, Luis Piñuel, Manuel Prieto-Matías	PERCIVAL: Open-Source Posit RISC-V Core With Quire Capability.	IEEE Trans. Emerg. Top. Comput.	2022	DBLP DOI BibTeX RDF
13	Eiji Yoshiya, Tomoya Nakanishi, Tsuyoshi Isshiki	Design Verification Methodology of Pipelined RISC-V Processor Using C2RTL Framework.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2022	DBLP DOI BibTeX RDF
13	Rami Elkhatib, Brian Koziel, Reza Azarderakhsh, Mehran Mozaffari Kermani	Accelerated RISC-V for Post-Quantum SIKE.	IEEE Trans. Circuits Syst. I Regul. Pap.	2022	DBLP DOI BibTeX RDF
13	Yifan Zhao, Ruiqi Xie, Guozhu Xin, Jun Han 0003	A High-Performance Domain-Specific Processor With Matrix Extension of RISC-V for Module-LWE Applications.	IEEE Trans. Circuits Syst. I Regul. Pap.	2022	DBLP DOI BibTeX RDF
13	Yossi Eni, Shlomo Greenberg, Yehuda Ben-Shimol	Efficient Hint-Based Event (EHE) Issue Scheduling for Hardware Multithreaded RISC-V Pipeline.	IEEE Trans. Circuits Syst. I Regul. Pap.	2022	DBLP DOI BibTeX RDF
13	Rogério Paludo, Leonel Sousa	NTT Architecture for a Linux-Ready RISC-V Fully-Homomorphic Encryption Accelerator.	IEEE Trans. Circuits Syst. I Regul. Pap.	2022	DBLP DOI BibTeX RDF
13	Lang Feng, Jiayi Huang 0001, Luyi Li, Haochen Zhang, Zhongfeng Wang 0001	RvDfi: A RISC-V Architecture With Security Enforcement by High Performance Complete Data-Flow Integrity.	IEEE Trans. Computers	2022	DBLP DOI BibTeX RDF
13	Piljoo Choi, Won Bae Kong, Ji-Hoon Kim, Mun-Kyu Lee, Dong Kyue Kim	Architectural Supports for Block Ciphers in a RISC CPU Core by Instruction Overloading.	IEEE Trans. Computers	2022	DBLP DOI BibTeX RDF
13	Bruno Sá, José Martins, Sandro Pinto 0001	A First Look at RISC-V Virtualization From an Embedded Systems Perspective.	IEEE Trans. Computers	2022	DBLP DOI BibTeX RDF
13	Jipeng Zhang, Junhao Huang, Zhe Liu 0001, Sujoy Sinha Roy	Time-Memory Trade-Offs for Saber+ on Memory-Constrained RISC-V Platform.	IEEE Trans. Computers	2022	DBLP DOI BibTeX RDF
13	Yuze Wang, Peng Liu 0016, Weidong Wang, Xiaohang Wang 0001, Yingtao Jiang	On a Consistency Testing Model and Strategy for Revealing RISC Processor's Dark Instructions and Vulnerabilities.	IEEE Trans. Computers	2022	DBLP DOI BibTeX RDF
13	Hela Belhadj Amor, Carolynn Bernier, Zdenek Prikryl	A RISC-V ISA Extension for Ultra-Low Power IoT Wireless Signal Processing.	IEEE Trans. Computers	2022	DBLP DOI BibTeX RDF
13	Enrico Tabanelli, Giuseppe Tagliavini, Luca Benini	Optimizing Random Forest-Based Inference on RISC-V MCUs at the Extreme Edge.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2022	DBLP DOI BibTeX RDF
13	Jim Plusquellic, Donald E. Owen, Tom J. Mannos, Brian Dziki	Information Leakage Analysis Using a Co-Design-Based Fault Injection Technique on a RISC-V Microprocessor.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2022	DBLP DOI BibTeX RDF
13	Jubee Tada, Keiichi Sato	An Implementation of a Grid Square Codes Generator on a RISC-V Processor.	Int. J. Netw. Comput.	2022	DBLP BibTeX RDF
13	Vladimir Herdt, Rolf Drechsler	Advanced virtual prototyping for cyber-physical systems using RISC-V: implementation, verification and challenges.	Sci. China Inf. Sci.	2022	DBLP DOI BibTeX RDF
13	Vaibhav Verma, Tommy Tracy II, Mircea R. Stan	EXTREM-EDGE - EXtensions To RISC-V for Energy-efficient ML inference at the EDGE of IoT.	Sustain. Comput. Informatics Syst.	2022	DBLP DOI BibTeX RDF
13	Jhalak Sharma, Nanditha Rao	The Characterization of Errors in an FPGA-Based RISC-V Processor due to Single Event Transients.	Microelectron. J.	2022	DBLP DOI BibTeX RDF
13	Fernando Fernandes dos Santos, Angeliki Kritikakou, Olivier Sentieys	Experimental evaluation of neutron-induced errors on a multicore RISC-V platform.	CoRR	2022	DBLP DOI BibTeX RDF
13	Kleber Stangherlin, Manoj Sachdev	Design and Implementation of a Secure RISC-V Microprocessor.	CoRR	2022	DBLP DOI BibTeX RDF
13	Xuanle Ren, Xiaoxia Cui	An Enclave-based TEE for SE-in-SoC in RISC-V Industry.	CoRR	2022	DBLP DOI BibTeX RDF
13	Kevin Cheang, Cameron Rasmussen, Dayeol Lee, David W. Kohlbrenner, Krste Asanovic, Sanjit A. Seshia	Verifying RISC-V Physical Memory Protection.	CoRR	2022	DBLP DOI BibTeX RDF
13	Luca Bertaccini, Gianna Paulin, Tim Fischer 0001, Stefan Mach, Luca Benini	MiniFloat-NN and ExSdotp: An ISA Extension and a Modular Open Hardware Unit for Low-Precision Training on RISC-V cores.	CoRR	2022	DBLP DOI BibTeX RDF
13	Yvan Tortorella, Luca Bertaccini, Davide Rossi, Luca Benini, Francesco Conti 0001	RedMulE: A Compact FP16 Matrix-Multiplication Accelerator for Adaptive Deep Learning on RISC-V-Based Ultra-Low-Power SoCs.	CoRR	2022	DBLP DOI BibTeX RDF
13	Nazareno Bruschi, Germain Haugou, Giuseppe Tagliavini, Francesco Conti 0001, Luca Benini, Davide Rossi	GVSoC: A Highly Configurable, Fast and Accurate Full-Platform Simulator for RISC-V based IoT Processors.	CoRR	2022	DBLP BibTeX RDF
13	Luca Valente, Yvan Tortorella, Mattia Sinigaglia, Giuseppe Tagliavini, Alessandro Capotondi, Luca Benini, Davide Rossi	HULK-V: a Heterogeneous Ultra-low-power Linux capable RISC-V SoC.	CoRR	2022	DBLP DOI BibTeX RDF
13	Marco Bertuletti, Yichao Zhang, Alessandro Vanelli-Coralli, Luca Benini	Efficient Parallelization of 5G-PUSCH on a Scalable RISC-V Many-core Processor.	CoRR	2022	DBLP DOI BibTeX RDF
13	Vladimir Ushakov, Sampo Sovio, Qingchao Qi, Vijayanand Nayani, Valentin Manea, Philip Ginzboorg, Jan-Erik Ekberg	Trusted Hart for Mobile RISC-V Security.	CoRR	2022	DBLP DOI BibTeX RDF
13	Jiulong Wang, Ruopu Wu, Guokai Chen, Xuhao Chen 0004, Boran Liu, Jixiang Zong, Di Zhao	RISC-V Toolchain and Agile Development based Open-source Neuromorphic Processor.	CoRR	2022	DBLP DOI BibTeX RDF
13	Andrea Bartolini, Federico Ficarelli, Emanuele Parisi, Francesco Beneventi, Francesco Barchi, Daniele Gregori, Fabrizio Magugliani, Marco Cicala, Cosimo Gianfreda, Daniele Cesarini, Andrea Acquaviva, Luca Benini	Monte Cimone: Paving the Road for the First Generation of RISC-V High-Performance Computers.	CoRR	2022	DBLP DOI BibTeX RDF
13	Ralf Ramsauer, Stefan Huber, Konrad Schwarz, Jan Kiszka, Wolfgang Mauerer	Static Hardware Partitioning on RISC-V - Shortcomings, Limitations, and Prospects.	CoRR	2022	DBLP DOI BibTeX RDF
13	Francesco Daghero, Chen Xie, Daniele Jahier Pagliari, Alessio Burrello, Marco Castellano, Luca Gandolfi, Andrea Calimera, Enrico Macii, Massimo Poncino	Ultra-compact Binary Neural Networks for Human Activity Recognition on RISC-V Processors.	CoRR	2022	DBLP DOI BibTeX RDF
13	David Demicco, Matthew Cole, Gokturk Yuksek, Ravi Theja Gollapudi, Aravind Prakash, Kanad Ghose, Zerksis Umrigar	Generic Tagging for RISC-V Binaries.	CoRR	2022	DBLP DOI BibTeX RDF
13	Matteo Perotti, Matheus A. Cavalcante, Nils Wistoff, Renzo Andri, Lukas Cavigelli, Luca Benini	A "New Ara" for Vector Computing: An Open Source Highly Efficient RISC-V V 1.0 Vector Processor Design.	CoRR	2022	DBLP DOI BibTeX RDF
13	Pablo Andreu, Carles Hernández 0001, Tomás Picornell, Pedro López 0001, Sergi Alcaide, Francisco Bas, Pedro Benedicte, Guillem Cabo, Feng Chang, Francisco Fuentes, Jaume Abella 0001	End-to-End QoS for the Open Source Safety-Relevant RISC-V SELENE Platform.	CoRR	2022	DBLP DOI BibTeX RDF
13	Joseph Zuckerman, Paolo Mantovani, Davide Giri, Luca P. Carloni	Enabling Heterogeneous, Multicore SoC Research with RISC-V and ESP.	CoRR	2022	DBLP DOI BibTeX RDF
13	Ruxandra Balucea, Paul Irofti	Software Mitigation of RISC-V Spectre Attacks.	CoRR	2022	DBLP DOI BibTeX RDF
13	Md. Ashraful Islam, Kenji Kise	An Efficient Resource Shared RISC-V Multicore Architecture.	IEICE Trans. Inf. Syst.	2022	DBLP DOI BibTeX RDF
13	Takuto Kanamori, Takashi Odan, Kazuki Hirohata, Kenji Kise	RVCar: An FPGA-Based Simple and Open-Source Mini Motor Car System with a RISC-V Soft Processor.	IEICE Trans. Inf. Syst.	2022	DBLP DOI BibTeX RDF
13	Shoei Nashimoto, Daisuke Suzuki, Rei Ueno, Naofumi Homma	Bypassing Isolated Execution on RISC-V using Side-Channel-Assisted Fault-Injection and Its Countermeasure.	IACR Trans. Cryptogr. Hardw. Embed. Syst.	2022	DBLP DOI BibTeX RDF
13	Hao Cheng 0009, Johann Großschädl, Ben Marshall, Dan Page, Thinh Hung Pham	RISC-V Instruction Set Extensions for Lightweight Symmetric Cryptography.	IACR Cryptol. ePrint Arch.	2022	DBLP BibTeX RDF
13	Patrick Karl, Jonas Schupp, Tim Fritzmann, Georg Sigl	Post-Quantum Signatures on RISC-V with Hardware Acceleration.	IACR Cryptol. ePrint Arch.	2022	DBLP BibTeX RDF
13	Gheorghe Pojoga, Kostas Papagiannopoulos	Low-latency implementation of the GIFT cipher on RISC-V architectures.	IACR Cryptol. ePrint Arch.	2022	DBLP BibTeX RDF
13	Huimin Li 0004, Nele Mentens, Stjepan Picek	Maximizing the Potential of Custom RISC-V Vector Extensions for Speeding up SHA-3 Hash Functions.	IACR Cryptol. ePrint Arch.	2022	DBLP BibTeX RDF
13	Yuehai Chen, Huarun Chen, Shaozhen Chen, Chao Han, Wujian Ye, Yijun Liu, Huihui Zhou	DITES: A Lightweight and Flexible Dual-Core Isolated Trusted Execution SoC Based on RISC-V.	Sensors	2022	DBLP DOI BibTeX RDF
13	Seonghwan Park, Dongwook Kang, Jeonghwan Kang, Donghyun Kwon	Bratter: An Instruction Set Extension for Forward Control-Flow Integrity in RISC-V.	Sensors	2022	DBLP DOI BibTeX RDF
13	María José Belda, Katzalin Olcoz, Fernando Castro, Francisco Tirado	Optimization of a line detection algorithm for autonomous vehicles on a RISC-V with accelerator.	J. Comput. Sci. Technol.	2022	DBLP DOI BibTeX RDF
13	Meng Liu	A co-design method of customized ISA design space exploration and fixed-point library construction for RISC-V dedicated processor.	IEICE Electron. Express	2022	DBLP DOI BibTeX RDF
13	Davide Zoni, Andrea Galimberti	Cost-effective fixed-point hardware support for RISC-V embedded systems.	J. Syst. Archit.	2022	DBLP DOI BibTeX RDF
13	Sallar Ahmadi-Pour, Vladimir Herdt, Rolf Drechsler	The MicroRV32 framework: An accessible and configurable open source RISC-V cross-level platform for education and research.	J. Syst. Archit.	2022	DBLP DOI BibTeX RDF
13	Yu Wang, Jinting Wu, Tai Yue, Zhenyu Ning, Fengwei Zhang	RetTag: hardware-assisted return address integrity on RISC-V.	EuroSec@EUROSYS	2022	DBLP DOI BibTeX RDF
13	Milan Funck, Vladimir Herdt, Rolf Drechsler	Virtual Prototype driven Design, Implementation and Evaluation of RISC-V Instruction Set Extensions.	DDECS	2022	DBLP DOI BibTeX RDF
13	Weiyan Zhang, Mehran Goli, Rolf Drechsler	Early Performance Estimation of Embedded Software on RISC-V Processor using Linear Regression.	DDECS	2022	DBLP DOI BibTeX RDF
13	Patrick Karl, Tim Fritzmann, Georg Sigl	Hardware Accelerated FrodoKEM on RISC-V.	DDECS	2022	DBLP DOI BibTeX RDF
13	Quentin Ducasse, Guillermo Polito, Pablo Tesone, Pascal Cotret, Loïc Lagadec	Porting a JIT Compiler to RISC-V: Challenges and Opportunities.	MPLR	2022	DBLP DOI BibTeX RDF
13	Blaise Tine, Varun Saxena, Santosh Srivatsan, Joshua R. Simpson, Fadi Alzammar, Liam Paul Cooper, Sam Jijina, Swetha Rajagoplan, Tejaswini Anand Kumar, Jeffrey Young 0001, Hyesoon Kim	Accelerating Graphic Rendering on Programmable RISC-V GPUs.	HCS	2022	DBLP DOI BibTeX RDF
13	Francesco Cosimi, Fabrizio Tronci, Sergio Saponara, Paolo Gai	Analysis, Hardware Specification and Design of a Programmable Performance Monitoring Unit (PPMU) for RISC-V ECUs.	SMARTCOMP	2022	DBLP DOI BibTeX RDF
13	Davide Nadalini, Manuele Rusci, Giuseppe Tagliavini, Leonardo Ravaglia, Luca Benini, Francesco Conti 0001	PULP-TrainLib: Enabling On-Device Training for RISC-V Multi-core MCUs Through Performance-Driven Autotuning.	SAMOS	2022	DBLP DOI BibTeX RDF
13	Alessandro Ottaviano, Robert Balas, Giovanni Bambini, Corrado Bonfanti, Simone Benatti, Davide Rossi, Luca Benini, Andrea Bartolini	ControlPULP: A RISC-V Power Controller for HPC Processors with Parallel Control-Law Computation Acceleration.	SAMOS	2022	DBLP DOI BibTeX RDF
13	Keisuke Sakamoto, Masanori Natsui, Takahiro Hanyu	Energy-Efficient Nonvolatile RISC-V CPU with a Custom Instruction-Controlled Accelerator.	MWSCAS	2022	DBLP DOI BibTeX RDF
13	Hidetaro Tanaka, Tomoaki Tanaka, Ryosuke Higashi, Tsutomu Sekibe, Shuichi Takada, Hironori Nakajo	Implementation of a RISC-V SMT Core in an AI processor.	SoICT	2022	DBLP DOI BibTeX RDF
13	Lucas Klemmer, Daniel Große	An Exploration Platform for Microcoded RISC-V Cores leveraging the One Instruction Set Computer Principle.	ISVLSI	2022	DBLP DOI BibTeX RDF
13	Adeboye Stephen Oyeniran, Maksim Jenihhin, Jaan Raik, Raimund Ubar	High-Level Fault Diagnosis in RISC Processors with Implementation-Independent Functional Test.	ISVLSI	2022	DBLP DOI BibTeX RDF
13	Halil Kükner, Gökhan Kaplayan, Ahmet Efe, Mehmet Ali Gülden	RISC-V Processor Trace Encoder with Multiple Instructions Retirement Support.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
13	Nicolas Gerlin, Endri Kaja, Monideep Bora, Keerthikumara Devarajegowda, Dominik Stoffel, Wolfgang Kunz, Wolfgang Ecker	Design of a Tightly-Coupled RISC-V Physical Memory Protection Unit for Online Error Detection.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
13	Chun-Jen Tsai, Yi-De Lee	Embedded TCP/IP Controller for a RISC-V SoC.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
13	Simon Butler 0001, Jonas Gamalielsson, Björn Lundell, Christoffer Brax, Tomas Persson, Anders Mattsson, Tomas Gustavsson, Jonas Feist, Jonas Öberg	An Exploration of Openness in Hardware and Software Through Implementation of a RISC-V Based Desktop Computer.	OpenSym	2022	DBLP DOI BibTeX RDF
13	Yvan Tortorella, Luca Bertaccini, Davide Rossi, Luca Benini, Francesco Conti 0001	RedMulE: A Compact FP16 Matrix-Multiplication Accelerator for Adaptive Deep Learning on RISC-V-Based Ultra-Low-Power SoCs.	DATE	2022	DBLP DOI BibTeX RDF
13	Vincenzo Maisto, Alessandro Cilardo	A Pluggable Vector Unit for RISC-V Vector Extension.	DATE	2022	DBLP DOI BibTeX RDF
13	Dongyun Kam, Jung Gyu Min, Jongho Yoon, Sunmean Kim, Seokhyeong Kang, Youngjoo Lee	Design and Evaluation Frameworks for Advanced RISC-based Ternary Processor.	DATE	2022	DBLP DOI BibTeX RDF
13	Wolfgang Ecker, Peer Adelt, Wolfgang Müller 0003, Reinhold Heckmann, Milos Krstic, Vladimir Herdt, Rolf Drechsler, Gerhard Angst, Ralf Wimmer 0001, Andreas Mauderer, Rafael Stahl, Karsten Emrich, Daniel Mueller-Gritschneder, Bernd Becker 0001, Philipp Scholl, Eyck Jentzsch, Jan Schlamelcher, Kim Grüttner, Paul Palomero Bernardo, Oliver Bringmann 0001, Mihaela Damian, Julian Oppermann, Andreas Koch 0001, Jörg Bormann, Johannes Partzsch, Christian Mayr 0001, Wolfgang Kunz	The Scale4Edge RISC-V Ecosystem.	DATE	2022	DBLP DOI BibTeX RDF
13	Zhanyuan Gao, Laiping Zhao, Haonan Chen	A Trigonometric Function Instruction Set Extension Method Based on RISC-V.	ICIS	2022	DBLP DOI BibTeX RDF
13	Anu Verma, Priyamvada Sharma, Bishnu Prasad Das	RISC-V Core with Approximate Multiplier for Error-Tolerant Applications.	DSD	2022	DBLP DOI BibTeX RDF
13	Parangat Sud, Shekoufeh Neisarian, Elif Bilge Kavun	Evaluating Cryptographic Extensions On A RISC-V Simulation Environment.	DSD	2022	DBLP DOI BibTeX RDF
13	Víctor Soria Pardos, Max Doblas, Guillem López-Paradís, Gerard Candón, Narcís Rodas, Xavier Carril, Pau Fontova-Musté, Neiel Leyva, Santiago Marco-Sola, Miquel Moretó	Sargantana: A 1 GHz+ In-Order RISC-V Processor with SIMD Vector Extensions in 22nm FD-SOI.	DSD	2022	DBLP DOI BibTeX RDF
13	Tobias Scheipel, Florian Angermair, Marcel Baunach	moreMCU: A Runtime-reconfigurable RISC-V Platform for Sustainable Embedded Systems.	DSD	2022	DBLP DOI BibTeX RDF
13	Anthony Zgheib, Olivier Potin, Jean-Baptiste Rigaud, Jean-Max Dutertre	A CFI Verification System based on the RISC-V Instruction Trace Encoder.	DSD	2022	DBLP DOI BibTeX RDF
13	Sallar Ahmadi-Pour, Sangeet Saha, Vladimir Herdt, Rolf Drechsler, Klaus D. McDonald-Maier	Task Mapping and Scheduling in FPGA-based Heterogeneous Real-time Systems: A RISC-V Case-Study.	DSD	2022	DBLP DOI BibTeX RDF
13	Antti Nurmi, Antti Rautakoura, Henri Lunnikivi, Timo D. Hämäläinen	A Resilient System Design to Boot a RISC-V MPSoC.	DSD	2022	DBLP DOI BibTeX RDF
13	Johannes Knödtel, Sebastian Rachuj, Marc Reichenbach	Suitability of ISAs for Data Paths Based on Redundant Number Systems: Is RISC-V the best?	DSD	2022	DBLP DOI BibTeX RDF
13	Yinan Xu 0001, Zihao Yu, Dan Tang, Guokai Chen, Lu Chen, Lingrui Gou, Yue Jin, Qianruo Li, Xin Li, Zuojun Li, Jiawei Lin, Tong Liu, Zhigang Liu, Jiazhan Tan, Huaqiang Wang, Huizhe Wang, Kaifan Wang, Chuanqi Zhang, Fawang Zhang, Linjuan Zhang, Zifei Zhang, Yangyang Zhao, Yaoyang Zhou, Yike Zhou, Jiangrui Zou, Ye Cai, Dandan Huan, Zusong Li, Jiye Zhao, Zihao Chen, Wei He, Qiyuan Quan, Xingwu Liu, Sa Wang, Kan Shi, Ninghui Sun, Yungang Bao	Towards Developing High Performance RISC-V Processors Using Agile Methodology.	MICRO	2022	DBLP DOI BibTeX RDF
13	Jien Hau Ng, Chee Hong Ang, Hwa Chaw Law	A Realization of IO Physical Memory Protection for RISC-V Systems.	MCSoC	2022	DBLP DOI BibTeX RDF
13	Sih Pin Tan, Yung It Ho	Scalability of Post-Silicon Test Generation for Multi-core RISC-V SOC Validation.	MCSoC	2022	DBLP DOI BibTeX RDF
13	Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai	Evaluation of Different Microarchitectures for Energy-Efficient RISC-V Cores.	MCSoC	2022	DBLP DOI BibTeX RDF
13	Viktor Razilov, Emil Matús, Gerhard P. Fettweis	Communications Signal Processing Using RISC-V Vector Extension.	IWCMC	2022	DBLP DOI BibTeX RDF
13	Tobias Kaiser, Friedel Gerfers	Pasithea-1: An Energy-Efficient Self-contained CGRA with RISC-Like ISA.	ARCS	2022	DBLP DOI BibTeX RDF
13	Davide Bove	Secure Services for Standard RISC-V Architectures.	ARES	2022	DBLP DOI BibTeX RDF
13	Amin Sarihi, Michael A. Schoenfelder, Abdel-Hameed A. Badawy	Performance Evaluation of an Out-of-Order RISC-V CPU: A SPEC INT 2017 Study.	IPCCC	2022	DBLP DOI BibTeX RDF
13	Jihye Lee, Whijin Kim, Sohyeon Kim, Ji-Hoon Kim	Post-Quantum Cryptography Coprocessor for RISC-V CPU Core.	ICEIC	2022	DBLP DOI BibTeX RDF