Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
1 | Crina Costea, Florent Bernard, Viktor Fischer, Robert Fouquet |
Analysis and Enhancement of Ring Oscillators Based Physical Unclonable Functions in FPGAs. |
ReConFig |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Dimitris Theodoropoulos, Georgi Kuzmanov, Georgi Gaydadjiev |
A Minimalistic Architecture for Reconfigurable WFS-Based Immersive-Audio. |
ReConFig |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Laurent Sauvage, Sylvain Guilley, Florent Flament, Jean-Luc Danger, Yves Mathieu |
Cross-Correlation Cartography. |
ReConFig |
2010 |
DBLP DOI BibTeX RDF |
|
1 | G. Ramirez-Conejo, Javier Díaz-Carmona, Agustín Ramírez-Agundis, Alfredo Padilla-Medina, José G. Delgado-Frias |
FPGA Implementation of Adjustable Wideband Fractional Delay FIR Filters. |
ReConFig |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Michael Schmidt 0004, Dietmar Fey |
An Optimized FPGA Implementation for a Parallel Path Planning Algorithm Based on Marching Pixels. |
ReConFig |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Juan Carlos Díaz Martín, Carolina Gómes-Tostón Gutierrez, Álvaro Cortés Fácila, Juan A. Rico-Gallego |
Issues on Building an MPI Cluster on Microblaze. |
ReConFig |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Manuel Saldaña, Arun Patel, Hao Jun Liu, Paul Chow |
Using Partial Reconfiguration in an Embedded Message-Passing System. |
ReConFig |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Ali Akbar Zarezadeh, Christophe Bobda |
Performance Analysis of Hardware/Software Middleware in Network of Smart Camera Systems. |
ReConFig |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Dmitri Mihhailov, Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson |
Parallel FPGA-Based Implementation of Recursive Sorting Algorithms. |
ReConFig |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Christoforos Kachris, George Nikiforos, Stamatis G. Kavadias, Vassilis Papaefstathiou, Manolis Katevenis |
Network Processing in Multi-core FPGAs with Integrated Cache-Network Interface. |
ReConFig |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Luis A. Vera-Salas, Sandra V. Moreno-Tapia, Roque Alfredo Osornio-Rios, René de Jesús Romero-Troncoso |
Reconfigurable Node Processing Unit for a Low-Power Wireless Sensor Network. |
ReConFig |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Kaveh Aasaraai, Andreas Moshovos |
An Efficient Non-blocking Data Cache for Soft Processors. |
ReConFig |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Ludovic Devaux, Sébastien Pillement, Daniel Chillet, Didier Demigny |
R2NoC: Dynamically Reconfigurable Routers for Flexible Networks on Chip. |
ReConFig |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Holger Flatt, Holger Blume, Peter Pirsch |
Mapping of a Real-Time Object Detection Application onto a Configurable RISC/Coprocessor Architecture at Full HD Resolution. |
ReConFig |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Mohamed El-Hadedy 0001, Martin Margala, Danilo Gligoroski, Svein J. Knapskog |
Implementing the Blue Midnight Wish Hash Function on Xilinx Virtex-5 FPGA Platform. |
ReConFig |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Christian de Schryver, Daniel Schmidt 0001, Norbert Wehn, Elke Korn, Henning Marxen, Ralf Korn |
A New Hardware Efficient Inversion Based Random Number Generator for Non-uniform Distributions. |
ReConFig |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Eduardo Cabal-Yepez, Ricardo Saucedo-Gallaga, Armando G. Garcia-Ramirez, Arturo A. Fernandez-Jaramillo, Marcos Pena-Anaya, Martin Valtierra-Rodriguez |
FPGA-Based Online Detection of Multiple-Combined Faults through Information Entropy and Neural Networks. |
ReConFig |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Joshua S. Monson, Michael J. Wirthlin, Brad L. Hutchings |
Fault Injection Results of Linux Operating on an FPGA Embedded Platform. |
ReConFig |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Khaled Sobaihi, Akram Hammoudeh, David Scammell |
FPGA Implementation of OFDM Transceiver for a 60GHz Wireless Mobile Radio System. |
ReConFig |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Zouha Cherif, Florent Flament, Jean-Luc Danger, Shivam Bhasin, Sylvain Guilley, Hervé Chabanne |
Evaluation of White-Box and Grey-Box Noekeon Implementations in FPGA. |
ReConFig |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Séamas McGettrick, Dermot Geraghty |
Hardware Computation of the PageRank Eigenvector. |
ReConFig |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Angelo Kuti Lusala, Jean-Didier Legat |
A Hybrid Router Combining SDM-Based Circuit Swictching with Packet Switching for On-chip Networks. |
ReConFig |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Valery Sklyarov, Iouliia Skliarova, Dmitri Mihhailov, Alexander Sudnitson |
Synthesis and Implementation of Hierarchical Finite State Machines with Implicit Modules. |
ReConFig |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Michael Schaeferling, Gundolf Kiefer |
Flex-SURF: A Flexible Architecture for FPGA-Based Robust Feature Extraction for Optical Tracking Systems. |
ReConFig |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Yue Wang, Kevin Cunningham, Prawat Nagvajara, Jeremy Johnson |
Singular Value Decomposition Hardware for MIMO: State of the Art and Custom Design. |
ReConFig |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Faisal Nadeem, Mahmood Ahmadi, Muhammad Faisal Nadeem, Stephan Wong |
Modeling and Simulation of Reconfigurable Processors in Grid Networks. |
ReConFig |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Azad Fakhari, Mahmood Fathy |
A Two Level Architecture for High Throughput DCT-Processor and Implementing on FPGA. |
ReConFig |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Josef Angermeier, Stefan Wildermann, Eugen Sibirko, Jürgen Teich |
Placing Streaming Applications with Similarities on Dynamically Partially Reconfigurable Architectures. |
ReConFig |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Janardhan Singaraju, John A. Chandy |
Parallel Data Sort Using Networked FPGAs. |
ReConFig |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Daniel M. Muñoz, Carlos H. Llanos, Leandro dos Santos Coelho, Mauricio Ayala-Rincón |
Hardware Particle Swarm Optimization Based on the Attractive-Repulsive Scheme for Embedded Applications. |
ReConFig |
2010 |
DBLP DOI BibTeX RDF |
|
1 | J. Pindter-Medina, Samuel Pichardo, Laura Curiel, Andrés David García García, Jesús Enrique Chong-Quero |
Multi-channel Driving Systems for Therapeutic Applications Based-on Focused Ultrasound. |
ReConFig |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Sébastien Guillet, Florent de Lamotte, Éric Rutten, Guy Gogniat, Jean-Philippe Diguet |
Modeling and Formal Control of Partial Dynamic Reconfiguration. |
ReConFig |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Xiang Tian 0001, Khaled Benkrid |
Fixed-Point Arithmetic Error Estimation in Monte-Carlo Simulations. |
ReConFig |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Jochen Strunk, Johannes Hiltscher, Wolfgang Rehm, Heiko Schick |
Communication Architectures for Run-Time Reconfigurable Modules in a 2-D Mesh on FPGAs. |
ReConFig |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Gabriel Marchesan Almeida, Sameer Varyani, Rémi Busseuil, Nicolas Hebert, Gilles Sassatelli, Pascal Benoit, Lionel Torres, Michel Robert |
Providing Better Multi-processor Systems-on-Chip Resources Utilization by Means of Using a Control-Loop Feedback Mechanism. |
ReConFig |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Ricardo P. Jasinski, Volnei A. Pedroni, Antonio Gortan, Walter Godoy Jr. |
An Improved GF(2) Matrix Inverter with Linear Time Complexity. |
ReConFig |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Rajesh Kannan Megalingam, Ashwin Mohan, Shekhil Hassan Thavalengal, Tanmay Muralidhar Rao, Vivek Periye |
Low Power Dual Core Microcontroller. |
ReConFig |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Daniel Kriesten, Volker Pankalla, Ulrich Heinkel |
An Application Example of a Run-Time Reconfigurable Embedded System. |
ReConFig |
2010 |
DBLP DOI BibTeX RDF |
|
1 | M. Ashfaquzzaman Khan, Richard Neil Pittman, Alessandro Forin |
gNOSIS: A Board-Level Debugging and Verification Tool. |
ReConFig |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Shady O. Agwa, Hany H. Ahmad, Awad I. Saleh |
Hardware Pessimistic Run-Time Profiling for a Self-Reconfigurable Embedded Processor Architecture. |
ReConFig |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Oliver Sander, Benjamin Glas, Lars Braun, Klaus D. Müller-Glaser, Jürgen Becker 0001 |
Intrinsic Identification of Xilinx Virtex-5 FPGA Devices Using Uninitialized Parts of Configuration Memory Space. |
ReConFig |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Yohei Hori, Takahiro Yoshida, Toshihiro Katashita, Akashi Satoh |
Quantitative and Statistical Performance Evaluation of Arbiter Physical Unclonable Functions on FPGAs. |
ReConFig |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Miaoqing Huang, David Andrews 0001, Jason Agron |
Operating System Structures for Multiprocessor Systems on Programmable Chip. |
ReConFig |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Wendi Wang, Bo Duan, Chunming Zhang, Peiheng Zhang, Ninghui Sun |
Accelerating 2D FFT with Non-Power-of-Two Problem Size on FPGA. |
ReConFig |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Bernhard Jungk, Steffen Reith |
On FPGA-Based Implementations of the SHA-3 Candidate Grøstl. |
ReConFig |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Marco Antonio Soto Hernandez, Oscar Alvarado Nava, Francisco Javier Zaragoza Martínez |
Huffman Coding-Based Compression Unit for Embedded Systems. |
ReConFig |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Hamid Mushtaq, Mojtaba Sabeghi, Koen Bertels |
A Runtime Profiler: Toward Virtualization of Polymorphic Computing Platforms. |
ReConFig |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Mieczyslaw Jessa, Michal Jaworski |
High-Speed FPGA-Based Pseudorandom Generators with Extremely Long Periods. |
ReConFig |
2010 |
DBLP DOI BibTeX RDF |
|
1 | David Pedrosa Branco, Iouliia Skliarova, José Vieira 0001 |
Reconfigurable Digital Audio Mixer for Electroacoustic Music. |
ReConFig |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Mingjie Lin, Shaoyi Cheng, John Wawrzynek |
Cascading Deep Pipelines to Achieve High Throughput in Numerical Reduction Operations. |
ReConFig |
2010 |
DBLP DOI BibTeX RDF |
|
1 | A. D. Santana Gil, José Ignacio Benavides Benítez, Manuel Hernandez Calviño, Ezequiel Herruzo Gomez |
Reconfigurable Cache Implemented on an FPGA. |
ReConFig |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Shaunak Shah, Rajesh Velegalati, Jens-Peter Kaps, David Hwang |
Investigation of DPA Resistance of Block RAMs in Cryptographic Implementations on FPGAs. |
ReConFig |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Luis Vitório Cargnini, Yoann Guillemenet, Lionel Torres, Gilles Sassatelli |
Improving the Reliability of a FPGA Using Fault-Tolerance Mechanism Based on Magnetic Memory (MRAM). |
ReConFig |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Mariusz Grad, Christian Plessl |
Pruning the Design Space for Just-in-Time Processor Customization. |
ReConFig |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Sascha Mühlbach, Andreas Koch 0001 |
A Dynamically Reconfigured Network Platform for High-Speed Malware Collection. |
ReConFig |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Kamana Sigdel, Carlo Galuzzi, Koen Bertels, Mark Thompson 0001, Andy D. Pimentel |
Runtime Task Mapping Based on Hardware Configuration Reuse. |
ReConFig |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Ali Reza Akoushideh, Asadollah Shahbahrami |
Accelerating Texture Features Extraction Algorithms Using FPGA Architecture. |
ReConFig |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Sasmita Deo |
Power Consumption Calculation of AP-DCD Algorithm Using FPGA Platform. |
ReConFig |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Tom Davidson, Karel Bruneel, Dirk Stroobandt |
Run-Time Reconfiguration for Automatic Hardware/Software Partitioning. |
ReConFig |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Lubos Gaspar, Viktor Fischer, Florent Bernard, Lilian Bossuet, Pascal Cotret |
HCrypt: A Novel Concept of Crypto-processor with Secured Key Management. |
ReConFig |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Nicolas Hebert, Gabriel Marchesan Almeida, Pascal Benoit, Gilles Sassatelli, Lionel Torres |
A Cost-Effective Solution to Increase System Reliability and Maintain Global Performance under Unreliable Silicon in MPSoC. |
ReConFig |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Cristinel Ababei |
Efficient Congestion-Oriented Custom Network-on-Chip Topology Synthesis. |
ReConFig |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Rui A. L. de Cristo, Ricardo P. Jasinski, Volnei A. Pedroni |
Analysis and Preliminary Measurements of Radiated Emissions in an Asynchronous Circuit versus its Synchronous Counterpart. |
ReConFig |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Ilia A. Lebedev, Shaoyi Cheng, Austin Doupnik, James C. Martin, Christopher W. Fletcher, Daniel Burke, Mingjie Lin, John Wawrzynek |
MARC: A Many-Core Approach to Reconfigurable Computing. |
ReConFig |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Marco A. Moreno-Armendáriz, Nareli Cruz Cortés, Alejandro León-Javier |
A Novel Hardware Implementation of the Compact Genetic Algorithm. |
ReConFig |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Eduardo Romero-Aguirre, Ramón Parra-Michel, Omar Humberto Longoria-Gandara, M. Aguirre-Hernandez |
A Hardware-Efficient Frequency Domain Correlator Architecture for Acquisition Stage in GPS. |
ReConFig |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Fadi El-Hassan, Dan Ionescu |
A Hardware Architecture of an XML/XPath Broker for Content-Based Publish/Subscribe Systems. |
ReConFig |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Marco A. Moreno-Armendáriz, Elsa Rubio, César A. Pérez-Olvera |
Design and Implementation of a Visual Fuzzy Control in FPGA for the Ball and Plate System. |
ReConFig |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Ling Liu, Oleksii Morozov |
A Process-Oriented Streaming System Design Paradigm for FPGAs. |
ReConFig |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Viktor K. Prasanna, Jürgen Becker 0001, René Cumplido (eds.) |
ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, Cancun, Quintana Roo, Mexico, 13-15 December 2010, Proceedings |
ReConFig |
2010 |
DBLP BibTeX RDF |
|
1 | Bruno A. Silva, Maurício Acconcia Dias, Jorge L. Silva, Fernando Santos Osório |
Genetic Algorithms and Artificial Neural Networks to Combinational Circuit Generation on Reconfigurable Hardware. |
ReConFig |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Aric Schorr, Marcin Lukowiak |
Skein Tree Hashing on FPGA. |
ReConFig |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Stephen D. Craven, Daniel Long, Jason Smith |
Open Source Precision Timed Soft Processor for Cyber Physical System Applications. |
ReConFig |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Ronald Hurtado-Velasco, Sadek Crisóstomo Absi Alfaro, Carlos H. Llanos |
FPGA-Based Platform Development for Change Detection in GTAW Welding Process. |
ReConFig |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Mark E. Dunham, Zachary K. Baker, Matthew Stettler, Michael Pigue, Paul S. Graham, Eric N. Schmierer, John Power |
High Efficiency Space-Based Software Radio Architectures: A Minimum Size, Weight, and Power TeraOps Processor. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
satellite hardware, FPGA, reconfigurable hardware, software-defined radio |
1 | Malte Baesler, Thomas Teufel |
FPGA Implementation of a Decimal Floating-Point Accurate Scalar Product Unit with a Parallel Fixed-Point Multiplier. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
decimal multiplier, IEEE 754-2008, accurate scalar product, FPGA, floating point |
1 | Tobias Schumacher 0001, Tim Süß, Christian Plessl, Marco Platzner |
Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
|
1 | Leonard Colavito, Dennis Silage |
Composite Look-Up Table Gaussian Pseudo-Random Number Generator. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
FPGA, Gaussian, Pseudo-Random Number |
1 | Eduardo Cabal-Yepez, Roque Alfredo Osornio-Rios, René de Jesús Romero-Troncoso, J. R. Razo-Hernandez, R. Lopez-Garcia |
FPGA-Based Online Induction Motor Multiple-Fault Detection with Fused FFT and Wavelet Analysis. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
Wavelet, FFT, Vibration, Induction motor, Multiple-fault detection, Current |
1 | Laurent Gantel, Salah Layouni, Mohamed El Amine Benkhelifa, François Verdier, Stéphanie Chauvet |
Multiprocessor Task Migration Implementation in a Reconfigurable Platform. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
RTOS for embedded platforms, Dynamic and partial reconfigurable systems, FPGA, MPSoC, Task migration |
1 | Çaglar Yilmaz, Mustafa Gök |
An Optimized System for Multiple Sequence Alignment. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
ClustalW, Hardware, Multiple Sequence Alignment |
1 | Brian Baldwin, William P. Marnane, Robert Granger |
Reconfigurable Hardware Implementation of Arithmetic Modulo Minimal Redundancy Cyclotomic Primes for ECC. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
Minimal Redundancy Cyclotomic Primes, Elliptic Curve Cryptography, Modular Multiplication |
1 | Mark G. Arnold, Jung H. Cho |
Parallax-Docking and Reconfiguration of Field Programmable Robot Arrays Using an Intermittently-Powered One-Hot Controller. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
SDA, reconfigurable micro-robot, one-hot, MEMS |
1 | Alireza Rohani, Hamid R. Zarandi |
A New CLB Architecture for Tolerating SEU in SRAM-Based FPGAs. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
Dependability, FPGA-Test |
1 | Javier Soto Vargas, Juan Manuel Moreno, Jordi Madrenas, Joan Cabestany |
Implementation of a Dynamic Fault-Tolerance Scaling Technique on a Self-Adaptive Hardware Architecture. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
selforganization, self-placement, dynamic fault tolerance, self-adaptive, self-configuration, self-routing |
1 | Julien Bringer, Hervé Chabanne, Jean-Luc Danger |
Protecting the NOEKEON Cipher against SCARE Attacks in FPGAs by Using Dynamic Implementations. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
SCARE attacks, white-box cryptography, FPGA |
1 | Marcio Juliato, Catherine H. Gebotys |
Tailoring a Reconfigurable Platform to SHA-256 and HMAC through Custom Instructions and Peripherals. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
Processor Specialization, SHA-2, Cryptography, HMAC, HW/SW Partitioning, Co-Processor, Custom Instruction |
1 | Sergio Ruben Geninatti, José Ignacio Benavides Benítez, Manuel Hernandez Calviño, Nicolás Guil Mata, Juan Gómez-Luna |
FPGA Implementation of the Generalized Hough Transform. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
concurrent calculation, FPGA, edge detection, video analysis, Hough Transform, video segmentation |
1 | Mathieu Allard, Patrick Grogan, Jean-Pierre David |
A Scalable Architecture for Multivariate Polynomial Evaluation on FPGA. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
High performance computing, ASIP, multivariate, Polynomial evaluation |
1 | Ming Liu 0011, Zhonghai Lu, Wolfgang Kuehn, Shuo Yang, Axel Jantsch |
A Reconfigurable Design Framework for FPGA Adaptive Computing. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
hardware process scheduling, hardware context switching, partial reconfiguration, adaptive computing |
1 | Johann Großschädl, Erkay Savas, Kazim Yumbul |
Realizing Arbitrary-Precision Modular Multiplication with a Fixed-Precision Multiplier Datapath. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
Bit-serial multiplier architecture, Scalability, Montgomery modular multiplication |
1 | Jochen Strunk, Toni Volkmer, Wolfgang Rehm, Heiko Schick |
Design and Performance of a Grid of Asynchronously Clocked Run-Time Reconfigurable Modules on a FPGA. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
asynchronous FIFO, FPGA, grid, dynamic reconfiguration, NoC, run-time reconfiguration |
1 | Vitor de Paulo, Cristinel Ababei |
A Framework for 2.5D NoC Exploration Using Homogeneous Networks over Heterogeneous Floorplans. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
Homogeneous Network-on-Chip, heterogeneous floorplan, 3D circuits |
1 | Fritz Mayer-Lindenberg |
High-Level FPGA Programming through Mapping Process Networks to FPGA Resources. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
|
1 | Panasayya Yalla, Jens-Peter Kaps |
Lightweight Cryptography for FPGAs. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
HIGHT, FPGA, Present |
1 | C. Yesid E. Castro, Carlos H. Llanos, Walter de Britto Vidal Filho, Leandro dos Santos Coelho |
Fuzzy Control for Cyclist Robot Stability Using FPGAs. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
SoC (System On Chip), harward/software codesign, fuzzy logic, embedded processor |
1 | Lev Kirischian, Victor Dumitriu, Pil Woo Chun |
Virtualization of Computing Resources in RCS for Multi-task Stream Applications. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
Virtual component, component relocation, on-chip assembly, FPGA, Reconfigurable systems, Run-time reconfiguration (RTR), Virtual processor, Resources virtualization |
1 | Mark Hamilton, William P. Marnane |
FPGA Implementation of an Elliptic Curve Processor Using the GLV Method. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
GLV method, Hiasat Multiplier, Elliptic curve processor, FPGA, Mersenne prime |
1 | Mondrian Nüssle, Benjamin Geib, Holger Fröning, Ulrich Brüning 0001 |
An FPGA-Based Custom High Performance Interconnection Network. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
hypertransport, network, interconnect, switching, crossbar |
1 | Hung-Manh Pham, Sébastien Pillement, Didier Demigny |
A Fault-Tolerant Layer for Dynamically Reconfigurable Multi-processor System-on-Chip. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
|